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| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-11-22 15:38:05 +0000 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-11-22 15:54:58 +0000 |
| commit | c4cdd9e464b36944e6b274b141ebea36828bc136 (patch) | |
| tree | 9c16784253ee8770f4c85ed5ccddf881d3934512 /include | |
| parent | 5c04fc789908f81d62886d83adee7e6c5cf356de (diff) | |
| download | platform_external_arm-trusted-firmware-c4cdd9e464b36944e6b274b141ebea36828bc136.tar.gz platform_external_arm-trusted-firmware-c4cdd9e464b36944e6b274b141ebea36828bc136.tar.bz2 platform_external_arm-trusted-firmware-c4cdd9e464b36944e6b274b141ebea36828bc136.zip | |
Revert "aarch32: Apply workaround for errata 813419 of Cortex-A57"
This reverts commit 6f512a3dfd61662dbdae4912fb6a320ae4d754d5.
According to the 'Cortex-A57 MPCore Software Developers Errata Notice':
This bug will only affect secure AArch64 EL3. If the above
conditions occur, the CPU will not invalidate the targeted EL3 TLB
entries and incorrect translations might occur.
For this reason it is not needed in AArch32.
Change-Id: I6f7b333817515499723e8f306145790ad6af9975
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/aarch32/arch_helpers.h | 27 |
1 files changed, 2 insertions, 25 deletions
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index 03f0e869b..1f69bb2b7 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -101,30 +101,15 @@ static inline void write_ ## _name(const u_register_t v) \ * Macros to create inline functions for tlbi operations *********************************************************************/ -#if ERRATA_A57_813419 -/* - * Define function for TLBI instruction with type specifier that - * implements the workaround for errata 813419 of Cortex-A57 - */ #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ static inline void tlbi##_op(void) \ { \ u_register_t v = 0; \ __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ - __asm__ volatile ("dsb ish");\ - __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ } -#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ -static inline void tlbi##_op(u_register_t v) \ -{ \ - __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ - __asm__ volatile ("dsb ish");\ - __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ -} -#else -#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ -static inline void tlbi##_op(void) \ +#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void bpi##_op(void) \ { \ u_register_t v = 0; \ __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ @@ -135,14 +120,6 @@ static inline void tlbi##_op(u_register_t v) \ { \ __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ } -#endif /* ERRATA_A57_813419 */ - -#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ -static inline void bpi##_op(void) \ -{ \ - u_register_t v = 0; \ - __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ -} /* Define function for simple TLBI operation */ #define DEFINE_TLBIOP_FUNC(_op, ...) \ |