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* Merge pull request #1386 from soby-mathew/sm/dyn_bl31Dimitris Papastamos2018-05-236-6/+25
|\ | | | | Extend dynamic configuration
| * FVP: Add dummy configs for BL31, BL32 and BL33Soby Mathew2018-05-213-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds soc_fw_config, tos_fw_config and nt_fw_config to the FVP. The config files are placeholders and do not have any useful bindings defined. The tos_fw_config is packaged in FIP and loaded by BL2 only if SPD=tspd. The load address of these configs are specified in tb_fw_config via new bindings defined for these configs. Currently, in FVP, the soc_fw_config and tos_fw_config is loaded in the page between BL2_BASE and ARM_SHARED_RAM. This memory was typically used for BL32 when ARM_TSP_RAM_LOCATION=tsram but since we cannot fit BL32 in that space anymore, it should be safe to use this memory for these configs. There is also a runtime check in arm_bl2_dyn_cfg_init() which ensures that this overlap doesn't happen. The previous arm_dyn_get_hwconfig_info() is modified to accept configs other than hw_config and hence renamed to arm_dyn_get_config_load_info(). The patch also corrects the definition of ARM_TB_FW_CONFIG_LIMIT to be BL2_BASE. Change-Id: I03a137d9fa1f92c862c254be808b8330cfd17a5a Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * Dynamic cfg: Enable support on CoT for other configsSoby Mathew2018-05-182-2/+12
| | | | | | | | | | | | | | | | | | | | This patch implements support for adding dynamic configurations for BL31 (soc_fw_config), BL32 (tos_fw_config) and BL33 (nt_fw_config). The necessary cert tool support and changes to default chain of trust are made for these configs. Change-Id: I25f266277b5b5501a196d2f2f79639d838794518 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * FVP: Enable capability to disable auth via dynamic configSoby Mathew2018-05-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds capability to FVP to disable authentication dynamically via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 parses the TB_FW_CONFIG for the `disable_auth` property and invokes the `load_dyn_disable_auth()` API to disable authentication if the property is set to 1. The DYN_DISABLE_AUTH is enabled by default for FVP as it is a development platform. Note that the TB_FW_CONFIG has to be authenticated by BL1 irrespective of these settings. The arm_bl2_dyn_cfg_init() is now earlier in bl2_plat_preload_setup() rather than in bl2_platform_setup() as we need to get the value of `disable_auth` property prior to authentication of any image by BL2. Change-Id: I734acd59572849793e5020ec44c6ac51f654a4d1 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * Allow disabling authentication dynamicallySoby Mathew2018-05-181-0/+8
| | | | | | | | | | | | | | | | | | | | This patch allows platforms to dynamically disable authentication of images during cold boot. This capability is controlled via the DYN_DISABLE_AUTH build flag and is only meant for development purposes. Change-Id: Ia3df8f898824319bb76d5cc855b5ad6c3d227260 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1393 from geesun/correct_commentDimitris Papastamos2018-05-221-2/+2
|\ \ | | | | | | Correct some typo errors in comment
| * | Correct some typo errors in commentQixiang Xu2018-05-221-2/+2
| |/ | | | | | | | | | | | | File: include/common/aarch64/el3_common_macros.S Change-Id: I619401e961a3f627ad8864781b5f90bc747c3ddb Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* / Ensure read and write of flags are 32 bitDaniel Boulby2018-05-171-1/+5
|/ | | | | | | | | | In 'console_set_scope' and when registering a console, field 'flags' of 'console_t' is assigned a 32-bit value. However, when it is actually used, the functions perform 64-bit reads to access its value. This patch changes all 64-bit reads to 32-bit reads. Change-Id: I181349371409e60065335f078857946fa3c32dc1 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* Merge pull request #1380 from CJKay/mmap-fixDimitris Papastamos2018-05-152-6/+14
|\ | | | | Fix incorrect number of reserved memory map entries for Arm platforms
| * plat/arm: Fix incorrect bounds check in ARM_CASSERT_MMAPChris Kay2018-05-111-3/+5
| | | | | | | | | | | | | | | | | | | | The bounds check in ARM_CASSERT_MMAP does not take into account the array sentinel in plat_arm_mmap. This commit fixes this, and adds an additional check to ensure the number of entries in the array is within the bounds of PLAT_ARM_MMAP_ENTRIES. Change-Id: Ie6df10c0aa0890d62826bc3224ad7b3e36fd53e2 Signed-off-by: Chris Kay <chris.kay@arm.com>
| * plat/arm: Fix incorrect number of reserved memory map entriesChris Kay2018-05-111-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | There are three calls to mmap_add_region() that always occur in arm_setup_page_tables(), and two further calls based on whether coherent memory is enabled, and whether SPM is enabled in BL31. This commit adapts the ARM_BL_REGIONS definition to match the number of calls made inside arm_setup_page_tables() so that the MAX_MMAP_REGIONS is realigned with what is actually occurring. Change-Id: I7adc05951abccf2cbd5c86280eb874911e6a1566 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Merge pull request #1379 from CJKay/nsram-fixDimitris Papastamos2018-05-151-4/+1
|\ \ | | | | | | Fix incorrect NSRAM memory map region for SGI-575
| * | css: Do not map the non-secure RAM as secureChris Kay2018-05-111-1/+1
| | | | | | | | | | | | | | | Change-Id: I7e73c0ab134da11c49f990b739245110c59eac2b Signed-off-by: Chris Kay <chris.kay@arm.com>
| * | css: Fix erroneous non-secure RAM base address/size for SGI-575Chris Kay2018-05-111-3/+0
| |/ | | | | | | | | | | | | SGI-575's NSRAM is neither in the same place nor the same size as Juno's. Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Merge pull request #1373 from jeenu-arm/ras-supportDimitris Papastamos2018-05-1510-7/+512
|\ \ | | | | | | RAS support
| * | ARM Platforms: Support RASJeenu Viswambharan2018-05-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Assign 0x10 for RAS exceptions on ARM platforms, and install EHF priority descriptor. - Call the common RAS initialisation from ARM BL31 setup. - Add empty definitions for platform error records and RAS interrupts. Change-Id: I0675f299b7840be4c83a9c7a81073a95c605dc90 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | RAS: Add fault injection supportJeenu Viswambharan2018-05-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv8.4 RAS extensions introduce architectural support for software to inject faults into the system in order to test fault-handling software. This patch introduces the build option FAULT_HANDLING_SUPPORT to allow for lower ELs to use registers in the Standard Error Record to inject fault. The build option RAS_EXTENSIONS must also be enabled along with fault injection. This feature is intended for testing purposes only, and is advisable to keep disabled for production images. Change-Id: I6f7a4454b15aec098f9505a10eb188c2f928f7ea Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | RAS: Allow individual interrupt registrationJeenu Viswambharan2018-05-042-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EHF currently allows for registering interrupt handlers for a defined priority ranges. This is primarily targeted at various EL3 dispatchers to own ranges of secure interrupt priorities in order to delegate execution to lower ELs. The RAS support added by earlier patches necessitates registering handlers based on interrupt number so that error handling agents shall receive and handle specific Error Recovery or Fault Handling interrupts at EL3. This patch introduces a macro, RAS_INTERRUPTS() to declare an array of interrupt numbers and handlers. Error handling agents can use this macro to register handlers for individual RAS interrupts. The array is expected to be sorted in the increasing order of interrupt numbers. As part of RAS initialisation, the list of all RAS interrupts are sorted based on their ID so that, given an interrupt, its handler can be looked up with a simple binary search. For an error handling agent that wants to handle a RAS interrupt, platform must: - Define PLAT_RAS_PRI to be the priority of all RAS exceptions. - Enumerate interrupts to have the GIC driver program individual EL3 interrupts to the required priority range. This is required by EHF even before this patch. Documentation to follow. Change-Id: I9471e4887ff541f8a7a63309e9cd8f771f76aeda Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | RAS: Add support for node registrationJeenu Viswambharan2018-05-041-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous patches added frameworks for handling RAS errors. This patch introduces features that the platform can use to enumerate and iterate RAS nodes: - The REGISTER_RAS_NODES() can be used to expose an array of ras_node_info_t structures. Each ras_node_info_t describes a RAS node, along with handlers for probing the node for error, and if did record an error, another handler to handle it. - The macro for_each_ras_node() can be used to iterate over the registered RAS nodes, probe for, and handle any errors. The common platform EA handler has been amended using error handling primitives introduced by both this and previous patches. Change-Id: I2e13f65a88357bc48cd97d608db6c541fad73853 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | RAS: Add helpers to access Standard Error RecordsJeenu Viswambharan2018-05-044-1/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv8 RAS Extensions introduced Standard Error Records which are a set of standard registers through which: - Platform can configure RAS node policy; e.g., notification mechanism; - RAS nodes can record and expose error information for error handling agents. Standard Error Records can either be accessed via. memory-mapped or System registers. This patch adds helper functions to access registers and fields within an error record. Change-Id: I6594ba799f4a1789d7b1e45b3e17fd40e7e0ba5c Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | AArch64: Introduce RAS handlingJeenu Viswambharan2018-05-043-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RAS extensions are mandatory for ARMv8.2 CPUs, but are also optional extensions to base ARMv8.0 architecture. This patch adds build system support to enable RAS features in ARM Trusted Firmware. A boolean build option RAS_EXTENSION is introduced for this. With RAS_EXTENSION, an Exception Synchronization Barrier (ESB) is inserted at all EL3 vector entry and exit. ESBs will synchronize pending external aborts before entering EL3, and therefore will contain and attribute errors to lower EL execution. Any errors thus synchronized are detected via. DISR_EL1 register. When RAS_EXTENSION is set to 1, HANDLE_EL3_EA_FIRST must also be set to 1. Change-Id: I38a19d84014d4d8af688bd81d61ba582c039383a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | AArch64: Introduce External Abort handlingJeenu Viswambharan2018-05-044-5/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, any External Abort routed to EL3 is reported as an unhandled exception and cause a panic. This patch enables ARM Trusted Firmware to handle External Aborts routed to EL3. With this patch, when an External Abort is received at EL3, its handling is delegated to plat_ea_handler() function. Platforms can provide their own implementation of this function. This patch adds a weak definition of the said function that prints out a message and just panics. In order to support handling External Aborts at EL3, the build option HANDLE_EA_EL3_FIRST must be set to 1. Before this patch, HANDLE_EA_EL3_FIRST wasn't passed down to compilation; this patch fixes that too. Change-Id: I4d07b7e65eb191ff72d63b909ae9512478cd01a1 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | Revert "plat/arm: Migrate AArch64 port to the multi console driver"Antonio Nino Diaz2018-05-153-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f18aa1fa35305f8feec25867473d30975b242fe. It is causing some tests to fail. Until the cause is found and fixed, it is needed to remove this commit from master. Change-Id: Ic5ff7a841903a15613e00379e87cbbd8a0e85152 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: Migrate AArch64 port to the multi console driverAntonio Nino Diaz2018-05-113-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old API is deprecated and will eventually be removed. Arm platforms now use the multi console driver for boot and runtime consoles. However, the crash console uses the direct console API because it doesn't need any memory access to work. This makes it more robust during crashes. The AArch32 port of the Trusted Firmware doesn't support this new API yet, so it is only enabled in AArch64 builds. Because of this, the common code must maintain compatibility with both systems. SP_MIN doesn't have to be updated because it's only used in AArch32 builds. The TSP is only used in AArch64, so it only needs to support the new API without keeping support for the old one. Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this causes the UARTs to reset (except for the one used by the TSP). This means that they must be unregistered when suspending and re-registered when resuming. This wasn't a problem with the old driver because it just restarted the UART, and there were no problems associated with registering and unregistering consoles. The size of BL31 has been increased in builds with SPM. Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | multi console: Assert that consoles aren't registered twiceAntonio Nino Diaz2018-05-111-1/+6
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the multi console driver, allowing to register the same console more than once may result in an infinte loop when putc is called. If, for example, a boot message is trying to be printed, but the consoles in the loop in the linked list are runtime consoles, putc will iterate forever looking for a console that can print boot messages (or a NULL pointer that will never come). This loop in the linked list can occur after restoring the system from a system suspend. The boot console is registered during the cold boot in BL31, but the runtime console is registered even in the warm boot path. Consoles are always added to the start of the linked list when they are registered, so this it what should happen if they were actually different structures: console_list -> NULL console_list -> BOOT -> NULL console_list -> RUNTIME -> BOOT -> NULL console_list -> RUNTIME -> RUNTIME -> BOOT -> NULL In practice, the two runtime consoles are the same one, so they create this loop: console_list -> RUNTIME -. X -> BOOT -> NULL ^ | `----' This patch adds an assertion to detect this problem. The assertion will fail whenever the same structure tries to be registered while being on the list. In order to assert this, console_is_registered() has been implemented. It returns 1 if the specified console is registered, 0 if not. Change-Id: I922485e743775ca9bd1af9cbd491ddd360526a6d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1377 from robertovargas-arm/compiler-warningsDimitris Papastamos2018-05-091-2/+2
|\ \ | | | | | | Compiler warnings
| * | xlat: Fix warning in CHECK_VIRT_ADDR_SPACE_SIZERoberto Vargas2018-05-091-2/+2
| |/ | | | | | | | | | | | | | | | | When TF is compiled for aarch32 MAX_VIRT_ADDR_SPACE_SIZE is 2^32 in some cases, which makes the test (size) <= MAX_VIRT_ADDR_SPACE_SIZE a tautology because uintptr_t is a 32 bit value. The cast remove the warning for clang. Change-Id: I1345f3400f8fbbe4ffd3caa990a90e7ba593dba5 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1354 from robertovargas-arm/mem_protectdanh-arm2018-05-084-5/+22
|\ \ | |/ |/| ARM platforms: Demonstrate mem_protect from el3_runtime
| * ARM platforms: Demonstrate mem_protect from el3_runtimeRoberto Vargas2018-05-014-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously mem_protect used to be only supported from BL2. This is not helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates mem_protect from el3_runtime firmware on ARM Platforms specifically when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap tables temporarily and then the protected regions are then cleared. This avoids the need to map the non secure DRAM permanently to BL31/sp_min. The stack size is also increased, because DYNAMIC_XLAT_TABLES require a bigger stack. Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | smccc: Fix checkpatch error in header fileAntonio Nino Diaz2018-05-021-2/+4
| | | | | | | | | | Change-Id: Ice141dcc17f504025f922acace94d98f84acba9e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1363 from antonio-nino-diaz-arm/an/res1-apdanh-arm2018-05-011-4/+4
|\ \ | | | | | | xlat: Set AP[1] to 1 when it is RES1
| * | xlat: Set AP[1] to 1 when it is RES1Antonio Nino Diaz2018-04-261-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the ARMv8 ARM issue C.a: AP[1] is valid only for stage 1 of a translation regime that can support two VA ranges. It is RES 1 when stage 1 translations can support only one VA range. This means that, even though this bit is ignored, it should be set to 1 in the EL3 and EL2 translation regimes. For translation regimes consisting on EL0 and a higher regime this bit selects between control at EL0 or at the higher Exception level. The regimes that support two VA ranges are EL1&0 and EL2&0 (the later one is only available since ARMv8.1). This fix has to be applied to both versions of the translation tables library. Change-Id: If19aaf588551bac7aeb6e9a686cf0c2068e7c181 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1360 from antonio-nino-diaz-arm/an/smccc-v2danh-arm2018-05-014-81/+264
|\ \ | | | | | | Add support for the SMC Calling Convention 2.0
| * | Add support for the SMC Calling Convention 2.0Antonio Nino Diaz2018-04-234-81/+264
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to differences in the bitfields of the SMC IDs, it is not possible to support SMCCC 1.X and 2.0 at the same time. The behaviour of `SMCCC_MAJOR_VERSION` has changed. Now, it is a build option that specifies the major version of the SMCCC that the Trusted Firmware supports. The only two allowed values are 1 and 2, and it defaults to 1. The value of `SMCCC_MINOR_VERSION` is derived from it. Note: Support for SMCCC v2.0 is an experimental feature to enable prototyping of secure partition specifications. Support for this convention is disabled by default and could be removed without notice. Change-Id: I88abf9ccf08e9c66a13ce55c890edea54d9f16a7 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | types: use int-ll64 for both aarch32 and aarch64Masahiro Yamada2018-04-271-40/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arch_helpers: use u_register_t for register read/writeMasahiro Yamada2018-04-271-3/+3
|/ | | | | | | u_register_t is preferred rather than uint64_t. This is more consistent with the aarch32 implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge pull request #1357 from antonio-nino-diaz-arm/an/fix-misraDimitris Papastamos2018-04-184-14/+14
|\ | | | | Fix some MISRA defects in SPM code
| * Fix some MISRA defects in SPM codeAntonio Nino Diaz2018-04-174-14/+14
| | | | | | | | | | Change-Id: I989c1f4aef8e3cb20d5d19e6347575e6449bb60b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1356 from robertovargas-arm/misra-changesDimitris Papastamos2018-04-165-10/+16
|\ \ | | | | | | Misra changes
| * | Fix MISRA rule 8.4 Part 4Roberto Vargas2018-04-132-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ie4cd6011b3e4fdcdd94ccb97a7e941f3b5b7aeb8 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * | Fix MISRA rule 8.3 Part 4Roberto Vargas2018-04-134-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ia34fe1ae1f142e89c9a6c19831e3daf4d28f5831 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * | Fix MISRA rule 8.5 in common codeRoberto Vargas2018-04-131-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Rule 8.5: An external object or function shall be declared once in one and only one file. Change-Id: I7c3d4ec7d3ba763fdb4600008ba10b4b93ecdfce Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Check presence of fix for errata 843419 in Cortex-A53Jonathan Wright2018-04-121-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | A fix for errata 843419 may be available in revision r0p4 of the Cortex-A53 processor. The presence of the fix is determined by checking bit 8 in the REVIDR register. If the fix is present we report ERRATA_NOT_APPLIES which silences the erroneous 'missing workaround' warning. Change-Id: Ibd2a478df3e2a6325442a6a48a0bb0259dcfc1d7 Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | Merge pull request #1342 from Summer-ARM/sq/support-tzmp1Dimitris Papastamos2018-04-111-2/+41
|\ \ | | | | | | support tzmp1
| * | plat/arm: Allow override of default TZC regionsSummer Qin2018-04-101-2/+41
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch allows the ARM Platforms to specify the TZC regions to be specified to the ARM TZC helpers in arm_tzc400.c and arm_tzc_dmc500.c. If the regions are not specified then the default TZC region will be configured by these helpers. This override mechanism allows specifying special regions for TZMP1 usecase. Signed-off-by: Summer Qin <summer.qin@arm.com>
* | Merge pull request #1348 from amitdanielkachhap/dmc500_single_if_v2Dimitris Papastamos2018-04-101-0/+1
|\ \ | | | | | | DMC500: Add platform support to set system interface count
| * | DMC500: Add platform support to set system interface countAmit Daniel Kachhap2018-04-091-0/+1
| |/ | | | | | | | | | | | | | | | | | | Some low end platforms using DMC500 memory controller do not have CCI(Cache Coherent Interconnect) interface and only have non-coherent system interface support. Hence this patch makes the system interface count configurable from the platforms. Change-Id: I6d54c90eb72fd18026c6470c1f7fd26c59dc4b9a Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
* | fix instruction address range limitationJiafei Pan2018-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | For the adr instruction, it require the label's offset from the address of this instruction must be in the range +/-1MB. If the option "BL2_IN_XIP_MEM" is set to '1', in some cases, BL2's RW memory will not in the range of +/-1MB from BL2's RO memory region. so we need to use ldr instruction to cover this case. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
* | Add support for BL2 in XIP memoryJiafei Pan2018-04-072-2/+12
|/ | | | | | | | | | In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This patch enable this use-case with a new build option, BL2_IN_XIP_MEM. For now, this option is only supported when BL2_AT_EL3 is 1. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
* Merge pull request #1334 from ↵Dimitris Papastamos2018-04-031-2/+0
|\ | | | | | | | | michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console qemu: don't use C functions for the crash console callbacks
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