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* pmf: Make the runtime instrumentation work on AArch32Bence Szépkúti2019-12-172-0/+28
| | | | | | | | | | | Ported the pmf asm macros and the asm code in the bl31 entrypoint necessary for the instrumentation to AArch32. Since smc dispatch is handled by the bl32 payload on AArch32, we provide this service only if AARCH32_SP=sp_min is set. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
* Merge changes from topic "aa/sel2_support" into integrationOlivier Deprez2019-12-131-0/+3
|\ | | | | | | | | | | * changes: S-EL2 Support: Check for AArch64 Add support for enabling S-EL2
| * S-EL2 Support: Check for AArch64Artsem Artsemenka2019-12-061-1/+1
| | | | | | | | | | | | | | | | Check that entry point information requesting S-EL2 has AArch64 as an execution state during context setup. Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7
| * Add support for enabling S-EL2Achin Gupta2019-12-061-0/+3
| | | | | | | | | | | | | | | | | | | | This patch adds support for enabling S-EL2 if this EL is specified in the entry point information being used to initialise a secure context. It is the caller's responsibility to check if S-EL2 is available on the system before requesting this EL through the entry point information. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1
* | Merge "PIE: make call to GDT relocation fixup generalized" into integrationSoby Mathew2019-12-121-1/+28
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| * | PIE: make call to GDT relocation fixup generalizedManish Pandey2019-12-121-1/+28
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead806 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | Merge "libc: add memrchr" into integrationAlexei Fedorov2019-12-111-0/+1
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| * | libc: add memrchrAmbroise Vincent2019-12-111-1/+2
| |/ | | | | | | | | | | | | | | This function scans a string backwards from the end for the first instance of a character. Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integrationSandrine Bailleux2019-12-101-3/+2
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| * | arm: Fix current RECLAIM_INIT_CODE behaviorAmbroise Vincent2019-12-091-3/+2
| |/ | | | | | | | | | | | | | | | | Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Zelalem Aweke <zelalem.aweke@arm.com>
* | Merge changes from topic "bs/libc" into integrationSoby Mathew2019-12-0618-387/+145
|\ \ | |/ |/| | | | | | | | | * changes: libc: Consolidate the size_t and NULL definitions libc: Consolidate unified definitions libc: Unify intmax_t and uintmax_t on AArch32/64
| * libc: Consolidate the size_t and NULL definitionsBence Szépkúti2019-12-0612-123/+8
| | | | | | | | | | | | | | | | Consolidate the definition of size_t to one header per AArch, and the definition of NULL to one header Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82
| * libc: Consolidate unified definitionsBence Szépkúti2019-12-0612-278/+143
| | | | | | | | | | | | | | | | | | | | | | | | As supporting architectures aside from AArch32 and AArch64 is not a concern, keeping identical definitions in two places for a large part of the libc seems counterproductive The int128 types were left un-unified as __int128 is not supported by gcc on AArch32 Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf
| * libc: Unify intmax_t and uintmax_t on AArch32/64Bence Szépkúti2019-12-062-4/+12
| | | | | | | | | | | | | | | | | | Conceptually, these are supposed to be the largest integers representable in C, but GCC and Clang define them as long long for compatibility. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: I7c0117f3be167342814d260a371889120dcf6576
* | Changes to support updated register usage in SMCCC v1.2Madhukar Pappireddy2019-11-262-2/+24
|/ | | | | | | | | | | | | | | | | From AArch64 state, arguments are passed in registers W0-W7(X0-X7) and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls. From AArch32 state, arguments are passed in registers R0-R7 and results are returned in registers R0-R7 for SMC32 calls. Most of the functions and macros already existed to support using upto 8 registers for passing/returning parameters/results. Added few helper macros for SMC calls from AArch32 state. Link to the specification: https://developer.arm.com/docs/den0028/c Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integrationPaul Beesley2019-11-121-9/+4
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| * plat/arm: Re-enable PIE when RESET_TO_BL31=1Manish Pandey2019-11-071-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | Earlier PIE support was enabled for all arm platforms when RESET_TO_BL31=1, but later on it was restricted only to FVP with patch SHA d4580d17 because of n1sdp platform. Now it has been verified that PIE does work for n1sdp platform also, so enabling it again for all arm platforms. Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | gic/gic600: add support for multichip configurationVijayenthiran Subramaniam2019-11-111-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
* | plat/arm/gicv3: add support for probing multiple GIC Redistributor framesVijayenthiran Subramaniam2019-11-051-0/+5
|/ | | | | | | | | | | | | | ARM platform can have a non-contiguous GICR frames. For instance, a multi socket platform can have two or more GIC Redistributor frames which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe` function to probe all the GICR frames available in the platform. Introduce `plat_arm_override_gicr_frames` function which platforms can use to override the default gicr_frames which holds the GICR base address of the primary cpu. Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
* Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__Balint Dobszay2019-10-112-4/+4
| | | | | Change-Id: I497072575231730a216220f84a6d349a48eaf5e3 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
* delay: correct timeout_init_us()Yann Gautier2019-10-081-1/+1
| | | | | | | | The function has to use read_cntpct_el0() to update the counter, and not read_cntfrq_el0(). Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Merge "Explicitly disable the SPME bit in MDCR_EL3" into integrationSoby Mathew2019-10-071-1/+8
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| * Explicitly disable the SPME bit in MDCR_EL3Petre-Ionut Tudor2019-10-071-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Currently the MDCR_EL3 initialisation implicitly disables MDCR_EL3.SPME by using mov_imm. This patch makes the SPME bit more visible by explicitly disabling it and documenting its use in different versions of the architecture. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3
* | Merge "Neoverse N1 Errata Workaround 1542419" into integrationSoby Mathew2019-10-072-4/+18
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| * | Neoverse N1 Errata Workaround 1542419laurenw-arm2019-10-042-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
* | | delay: timeout detection supportLionel Debieve2019-10-031-1/+24
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
* | Introducing support for Cortex-A65AEImre Kis2019-10-031-0/+31
| | | | | | | | | | Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis <imre.kis@arm.com>
* | Merge changes from topic "stm32mp_corrections_w40" into integrationSoby Mathew2019-10-031-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: gpio: stm32_gpio: do not mix error code types fdts: stm32mp1: move FDCAN to PLL4_R mmc: increase delay between ACMD41 retries crypto: stm32_hash: align stm32_hash_update() prototype
| * | crypto: stm32_hash: align stm32_hash_update() prototypeYann Gautier2019-10-031-1/+1
| |/ | | | | | | | | | | | | Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge "Add missing support for BL2_AT_EL3 in XIP memory" into integrationSoby Mathew2019-10-032-2/+2
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| * | Add missing support for BL2_AT_EL3 in XIP memoryLionel Debieve2019-10-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing flag for aarch32 XIP memory mode. It was previously added in aarch64 only. Minor: Correct the aarch64 missing flag. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iac0a7581a1fd580aececa75f97deb894858f776f
* | | Introducing support for Cortex-A65Imre Kis2019-10-021-0/+31
| |/ |/| | | | | | | Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis <imre.kis@arm.com>
* | Merge "Cortex_hercules: Add support for Hercules-AE" into integrationSoby Mathew2019-10-011-0/+14
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| * Cortex_hercules: Add support for Hercules-AEArtsem Artsemenka2019-09-301-0/+14
| | | | | | | | | | | | | | Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
* | Merge "AArch32: Disable Secure Cycle Counter" into integrationSoby Mathew2019-09-273-8/+81
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| * AArch32: Disable Secure Cycle CounterAlexei Fedorov2019-09-263-8/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge changes from topic "ld/stm32-authentication" into integrationSoby Mathew2019-09-272-1/+24
|\ \ | | | | | | | | | | | | | | | | | | * changes: stm32mp1: add authentication support for stm32image bsec: move bsec_mode_is_closed_device() service to platform crypto: stm32_hash: Add HASH driver
| * | bsec: move bsec_mode_is_closed_device() service to platformLionel Debieve2019-09-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
| * | crypto: stm32_hash: Add HASH driverLionel Debieve2019-09-201-0/+24
| | | | | | | | | | | | | | | | | | | | | The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
* | | Merge changes from topic "mp/giv3-discovery" into integrationSoby Mathew2019-09-273-2/+6
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | * changes: Migrate ARM platforms to use the new GICv3 API Adding new optional PSCI hook pwr_domain_on_finish_late GICv3: Enable multi socket GIC redistributor frame discovery
| * | Migrate ARM platforms to use the new GICv3 APIMadhukar Pappireddy2019-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch invokes the new function gicv3_rdistif_probe() in the ARM platform specific gicv3 driver. Since this API modifies the shared GIC related data structure, it must be invoked coherently by using the platform specific pwr_domain_on_finish_late hook. Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | Adding new optional PSCI hook pwr_domain_on_finish_lateMadhukar Pappireddy2019-09-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This PSCI hook is similar to pwr_domain_on_finish but is guaranteed to be invoked with the respective core and cluster are participating in coherency. This will be necessary to safely invoke the new GICv3 API which modifies shared GIC data structures concurrently. Change-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | GICv3: Enable multi socket GIC redistributor frame discoveryMadhukar Pappireddy2019-09-251-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge changes I0283fc2e,Ib476d024,Iada05f7c into integrationPaul Beesley2019-09-262-3/+11
|\ \ | |/ |/| | | | | | | | | * changes: hikey: fix to load FIP by partition table. hikey960: fix to load FIP by partition table drivers: partition: support different block size
| * drivers: partition: support different block sizeHaojian Zhuang2019-09-182-3/+11
| | | | | | | | | | | | | | | | | | The block size of some storage device is 4096-byte long, such as UFS. But PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3
* | Merge changes from topic "raspberry-pi-4-support" into integrationSandrine Bailleux2019-09-161-0/+15
|\ \ | | | | | | | | | | | | | | | * changes: Add fdt_add_reserved_memory() helper function qemu: Move and generalise FDT PSCI fixup
| * | Add fdt_add_reserved_memory() helper functionAndre Przywara2019-09-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a firmware component like TF-A reserves special memory regions for its own or secure payload services, it should announce the location and size of those regions to the non-secure world. This will avoid disappointment when some rich OS tries to acccess this memory, which will likely end in a crash. The traditional way of advertising reserved memory using device tree is using the special memreserve feature of the device tree blob (DTB). However by definition those regions mentioned there do not prevent the rich OS to map this memory, which may lead to speculative accesses to this memory and hence spurious bus errors. A safer way of carving out memory is to use the /reserved-memory node as part of the normal DT structure. Besides being easier to setup, this also defines an explicit "no-map" property to signify the secure-only nature of certain memory regions, which avoids the rich OS to accidentally step on it. Add a helper function to allow platform ports to easily add a region. Change-Id: I2b92676cf48fd3bdacda05b5c6b1c7952ebed68c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | qemu: Move and generalise FDT PSCI fixupAndre Przywara2019-09-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QEMU platform port scans its device tree to advertise PSCI as the CPU enable method. It does this by scanning *every* node in the DT and check whether its compatible string starts with "arm,cortex-a". Then it sets the enable-method to PSCI, if it doesn't already have one. Other platforms might want to use this functionality as well, so let's move it out of the QEMU platform directory and make it more robust by fixing some shortcomings: - A compatible string starting with a certain prefix is not a good way to find the CPU nodes. For instance a "arm,cortex-a72-pmu" node will match as well and is in turn favoured with an enable-method. - If the DT already has an enable-method, we won't change this to PSCI. Those two issues will for instance fail on the Raspberry Pi 4 DT. To fix those problems, we adjust the scanning method: The DT spec says that all CPU nodes are subnodes of the mandatory /cpus node, which is a subnode of the root node. Also each CPU node has to have a device_type = "cpu" property. So we find the /cpus node, then scan for a subnode with the proper device_type, forcing the enable-method to "psci". We have to restart this search after a property has been patched, as the node offsets might have changed meanwhile. This allows this routine to be reused for the Raspberry Pi 4 later. Change-Id: I00cae16cc923d9f8bb96a9b2a2933b9a79b06139 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "raspberry-pi-4-support" into integrationSandrine Bailleux2019-09-162-0/+51
|\| | | |/ |/| | | | | | | | | * changes: rpi3: Move rng driver to drivers rpi3: Move VC mailbox driver into generic drivers directory rpi3: Move rpi3_hw.h header file to include/rpi_hw.h
| * rpi3: Move rng driver to driversAndre Przywara2019-09-131-0/+12
| | | | | | | | | | | | | | | | To allow sharing the driver between the RPi3 and RPi4, move the random number generator driver into the generic driver directory. Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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