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* Fix pointer type mismatch of handlersMasahiro Yamada2018-04-271-1/+1
| | | | | | | | Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge pull request #1356 from robertovargas-arm/misra-changesDimitris Papastamos2018-04-163-5/+5
|\ | | | | Misra changes
| * Fix MISRA rule 8.4 Part 4Roberto Vargas2018-04-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ie4cd6011b3e4fdcdd94ccb97a7e941f3b5b7aeb8 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * Fix MISRA rule 8.3 Part 4Roberto Vargas2018-04-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ia34fe1ae1f142e89c9a6c19831e3daf4d28f5831 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | DMC500: Add platform support to set system interface countAmit Daniel Kachhap2018-04-091-4/+14
|/ | | | | | | | | | Some low end platforms using DMC500 memory controller do not have CCI(Cache Coherent Interconnect) interface and only have non-coherent system interface support. Hence this patch makes the system interface count configurable from the platforms. Change-Id: I6d54c90eb72fd18026c6470c1f7fd26c59dc4b9a Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
* Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statementsDimitris Papastamos2018-03-295-10/+24
|\ | | | | Fix switch statements to comply with MISRA rules
| * drivers: fix switch statements to comply with MISRA rulesJonathan Wright2018-03-265-10/+24
| | | | | | | | | | | | | | | | Ensure (where possible) that switch statements in drivers comply with MISRA rules 16.1 - 16.7. Change-Id: I7a91e04b02af80fbc4673a52293386c0f81a0f7a Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | Merge pull request #1333 from jeenu-arm/icfg-fixDimitris Papastamos2018-03-292-11/+20
|\ \ | | | | | | GIC: Fix interrupt setting interrupt configuration
| * | GIC: Fix setting interrupt configurationJeenu Viswambharan2018-03-262-11/+20
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Interrupt configuration is a 2-bit field, so the field shift has to be double that of the bit number. - Interrupt configuration (level- or edge-trigger) is specified in the MSB of the field, not LSB. Fixes applied to both GICv2 and GICv3 drivers. Fixes ARM-software/tf-issues#570 Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | Merge pull request #1329 from antonio-nino-diaz-arm/an/rpi3-multi-consoleDimitris Papastamos2018-03-291-7/+36
|\ \ | | | | | | rpi3: Migrate to the multi console API
| * | drivers: ti: 16550: Implement console flushAntonio Nino Diaz2018-03-221-7/+36
| |/ | | | | | | | | | | | | Replace placeholder by actual implementation. Change-Id: I0861b1ac5304b0d2d7c32d7d9a48bd985e258e92 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* / Clean usage of void pointers to access symbolsJoel Hutton2018-03-271-5/+4
|/ | | | | | | | | | | Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type. Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* [PATCH 1/2] qemu: Support MULTI_CONSOLE_APIMichalis Pappas2018-03-051-0/+1
| | | | | | | Include missing plat_helpers.S into pl011_console.S, to build successfully when MULTI_CONSOLE_API is enabled. Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* Emit warnings when using deprecated GIC initDan Handley2018-03-012-0/+55
| | | | | | | | | | | | | | | | Emit runtime warnings when intializing the GIC drivers using the deprecated method of defining integer interrupt arrays in the GIC driver data structures; interrupt_prop_t arrays should be used instead. This helps platforms detect that they have migration work to do. Previously, no warning was emitted in this case. This affects both the GICv2 and GICv3 drivers. Also use the __deprecated attribute to emit a build time warning if these deprecated fields are used. These warnings are suppressed in the GIC driver compatibility functions but will be visible if platforms use them. Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a Signed-off-by: Dan Handley <dan.handley@arm.com>
* Improve MULTI_CONSOLE_API deprecation warningsDan Handley2018-03-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms that have not migrated to MULTI_CONSOLE_API == 1, there are a lot of confusing deprecated declaration warnings relating to use of console_init() and console_uninit(). Some of these relate to use by the generic code, not the platform code. These functions are not really deprecated but *removed* when MULTI_CONSOLE_API == 1. This patch consolidates these warnings into a single preprocessor warning. The __deprecated attribute is removed from the console_init() and console_uninit() declarations. For preprocessor warnings like this to not cause fatal build errors, this patch adds -Wno-error=cpp to the build flags when ERROR_DEPRECATED == 0. This option (and -Wno-error=deprecated-declarations) is now added to CPPFLAGS instead of TF_CFLAGS to ensure the build flags are used in the assembler as well as the compiler. This patch also disentangles the MULTI_CONSOLE_API and ERROR_DEPRECATED build flags by defaulting MULTI_CONSOLE_API to 0 instead of ERROR_DEPRECATED. This allows platforms that have not migrated to MULTI_CONSOLE_API to use ERROR_DEPRECATED == 1 to emit a more meaningful build error. Finally, this patch bans use of MULTI_CONSOLE_API == 1 and AARCH32, since the AArch32 console implementation does not support MULTI_CONSOLE_API == 1. Change-Id: If762165ddcb90c28aa7a4951aba70cb15c2b709c Signed-off-by: Dan Handley <dan.handley@arm.com>
* Fix MISRA rule 8.4 Part 1Roberto Vargas2018-02-284-7/+9
| | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Fix MISRA rule 8.4 in common codeRoberto Vargas2018-02-286-8/+17
| | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Fix MISRA rule 8.3 in common codeRoberto Vargas2018-02-281-11/+12
| | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Dynamic cfg: Add HW and TB_FW configs to CoTSoby Mathew2018-02-261-1/+51
| | | | | | | | This patch adds image IDs to `hw_config` and `tb_fw_config` and includes them in the default Chain Of Trust (CoT). Change-Id: If7bb3e9be8a5e48be76614b35bf43d58fc7fed12 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Merge pull request #1264 from fengbaopeng/integrationdavidcunado-arm2018-02-242-1/+35
|\ | | | | drivers:ufs: fix hynix ufs bug with quirk on hi36xx SoC
| * drivers:ufs: fix hynix ufs bug with quirk on hi36xx SoCfengbaopeng2018-02-242-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | Hynix ufs has deviations on hi36xx platform which will result in ufs bursts transfer failures at a very low probability. To fix the problem, the Hynix device must set the register VS_DebugSaveConfigTime to 0x10, which will set time reference for SaveConfigTime is 250 ns. The time reference for SaveConfigTime is 40 ns by default. Signed-off-by: fengbaopeng <fengbaopeng@hisilicon.com>
* | Resolve TZC400 build issue when DEBUG=1 and ENABLE_ASSERTIONS=0Soby Mathew2018-02-211-2/+1
| | | | | | | | | | | | | | | | | | | | Previously the definition of `_tzc_read_peripheral_id()` was wrapped in ENABLE_ASSERTIONS build flag. This causes build issue for TZC400 driver when DEBUG=1 and ENABLE_ASSERTIONS=0. This patch fixes the same by moving the definitions outside the ENABLE_ASSERTIONS build flag. Change-Id: Ic1cad69f02ce65ac34aefd39eaa96d5781043152 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Remove URLs from commentsAntonio Nino Diaz2018-02-142-10/+9
|/ | | | | | | | | | | | | | | | | | | | | | This fixes all defects according to MISRA Rule 3.1: "The character sequences /* and // shall not be used within a comment". This affects all URLs in comments, so they have been removed: - The link in `sdei_state.c` can also be found in the documentation file `docs/sdei.rst`. - The bug that the file `io_fip.c` talks about doesn't affect the currently supported version of GCC, so it doesn't make sense to keep the comment. Note that the version of GCC officially supported is the one that comes with Linaro Release 17.10, which is GCC 6.2. - The link in `tzc400.c` was broken, and it didn't correctly direct to the Technical Reference Manual it should. The link has been replaced by the title of the document, which is more convenient when looking for the document. Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1236 from dbasehore/gic-save-restoredavidcunado-arm2018-02-011-0/+9
|\ | | | | RK3399 GIC save/restore
| * GICv3: Fix Dist restore for when the GIC is resetDerek Basehore2018-01-231-0/+9
| | | | | | | | | | | | | | | | | | If the GIC loses power during suspend, which the restore code was written for, exit early in the post restore power sequence. This prevents an assert from tripping, and the power sequence isn't needed in this case anyways. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
* | Merge pull request #1235 from jwerner-chromium/JW_udelaydavidcunado-arm2018-01-301-1/+3
|\ \ | | | | | | Fix udelay issues that can make duration slightly too short
| * | delay_timer: Guarantee that delay time can never be undershotJulius Werner2018-01-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delay functions like udelay() are often used to ensure that the necessary time passed to allow some asynchronous event to finish, such as the stabilization delay for a power rail. For these use cases it is not very problematic if the delay is slightly longer than requested, but it is critical that the delay must never be shorter. The current udelay() implementation contains two hazards that may cause the delay to be slightly shorter than intended: Firstly, the amount of ticks to wait is calculated with an integer division, which may cut off the last fraction of ticks needed. Secondly, the delay may be short by a fraction of a tick because we do not know whether the initial ("start") sample of the timer was near the start or near the end of the current tick. Thus, if the code intends to wait for one tick, it might read the timer value close to the end of the current tick and then read it again right after the start of the next tick, concluding that the duration of a full tick has passed when it in fact was just a fraction of it. This patch rounds up the division and always adds one extra tick to counteract both problems and ensure that delays will always be larger but never smaller than requested. Change-Id: Ic5fe5f858b5cdf3c0dbf3e488d4d5702d9569433 Signed-off-by: Julius Werner <jwerner@chromium.org>
* | | Merge pull request #1193 from jwerner-chromium/JW_corebootdavidcunado-arm2018-01-248-244/+985
|\ \ \ | |_|/ |/| | New console API and coreboot support [v4]
| * | coreboot: Add support for CBMEM consoleJulius Werner2018-01-191-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot supports an in-memory console to store firmware logs even when no serial console is available. It is widely supported by coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be read by the Linux kernel. This patch allows BL31 to add its own log messages to this console. The driver will be registered automatically if coreboot support is compiled in and detects the presence of a console buffer in the coreboot tables. Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907 Signed-off-by: Julius Werner <jwerner@chromium.org>
| * | drivers: cadence: cdns: Update CDNS driver to support MULTI_CONSOLE_APIJulius Werner2018-01-191-30/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Cadence CDNS console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: I2ef8fb0d6ab72696997db1e0243a533499569d6b Signed-off-by: Julius Werner <jwerner@chromium.org>
| * | drivers: arm: pl011: Update PL011 driver to support MULTI_CONSOLE_APIJulius Werner2018-01-191-33/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the ARM PL011 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: Ic34e4158addbb0c5fae500c9cff899c05a4f4206 Signed-off-by: Julius Werner <jwerner@chromium.org>
| * | drivers: ti: uart: Update 16550 UART driver to support MULTI_CONSOLE_APIJulius Werner2018-01-191-25/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the TI 16550 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: I60a44b7ba3c35c74561824c04b8dbe3e3039324c Signed-off-by: Julius Werner <jwerner@chromium.org>
| * | Add new function-pointer-based console APIJulius Werner2017-12-124-156/+504
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch overhauls the console API to allow for multiple console instances of different drivers that are active at the same time. Instead of binding to well-known function names (like console_core_init), consoles now provide a register function (e.g. console_16550_register()) that will hook them into the list of active consoles. All console operations will be dispatched to all consoles currently in the list. The new API will be selected by the build-time option MULTI_CONSOLE_API, which defaults to ${ERROR_DEPRECATED} for now. The old console API code will be retained to stay backwards-compatible to older platforms, but should no longer be used for any newly added platforms and can hopefully be removed at some point in the future. The new console API is intended to be used for both normal (bootup) and crash use cases, freeing platforms of the need to set up the crash console separately. Consoles can be individually configured to be active active at boot (until first handoff to EL2), at runtime (after first handoff to EL2), and/or after a crash. Console drivers should set a sane default upon registration that can be overridden with the console_set_scope() call. Code to hook up the crash reporting mechanism to this framework will be added with a later patch. This patch only affects AArch64, but the new API could easily be ported to AArch32 as well if desired. Change-Id: I35c5aa2cb3f719cfddd15565eb13c7cde4162549 Signed-off-by: Julius Werner <jwerner@chromium.org>
* | Merge pull request #1227 from geesun/qx/emmc_macrosdavidcunado-arm2018-01-191-2/+4
|\ \ | | | | | | emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8
| * | emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8Qixiang Xu2018-01-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add some macros according to JEDEC Standard Embedded Multi-Media Card (eMMC) Electrical Standard (5.1)": Table 145 - Bus Mode Selection. Change-Id: Iaa45e0582653ef4290efd60d039f0bdc420eeb47 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | | Merge pull request #1200 from robertovargas-arm/bl2-el3davidcunado-arm2018-01-193-9/+0
|\ \ \ | | | | | | | | Add BL2_AT_EL3 build option
| * | | bl2-el3: Don't compile BL1 when BL2_AT_EL3 is defined in FVPRoberto Vargas2018-01-183-9/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the makefiles to avoid the definition of BL1_SOURCES and BL2_SOURCES in the tbbr makefiles, and it lets to the platform makefiles to define them if they actually need these images. In the case of BL2_AT_EL3 BL1 will not be needed usually because the Boot ROM will jump directly to BL2. Change-Id: Ib6845a260633a22a646088629bcd7387fe35dcf9 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* / / emmc/dw_mmc: fix the assert on HLE bitHaojian Zhuang2018-01-111-1/+1
|/ / | | | | | | | | | | | | When check HLE bit in interrupt register, it should check whether HLE bit is set, not clear. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | Merge pull request #1194 from robertovargas-arm/io-fixdavidcunado-arm2017-12-191-140/+260
|\ \ | |/ |/| io: block: fix block_read/write may read/write overlap buffer
| * io: block: fix block_read/write may read/write overlap bufferRoberto Vargas2017-12-131-140/+260
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The block operations were trying to optimize the number of memory copies, and it tried to use directly the buffer supplied by the user to them. This was a mistake because it created too many corner cases: 1- It was possible to generate unaligned operations to unaligned buffers. Drivers that were using DMA transfer failed in that case. 2- It was possible to generate read operations with sizes that weren't a multiple of the block size. Some low level drivers assumed that condition and they calculated the number of blocks dividing the number of bytes by the size of the block, without considering the remaining bytes. 3- The block_* operations didn't control the number of bytes actually copied to memory, because the low level drivers were writing directly to the user buffer. This patch rewrite block_read and block_write to use always the device buffer, which the platform ensures that has the correct aligment and the correct size. Change-Id: I5e479bb7bc137e6ec205a8573eb250acd5f40420 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com> Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm2017-11-231-1/+13
|\ \ | |/ |/| Support ARMv7 architectures
| * ARMv7: GICv2 driver can manage GICv1 with security extensionEtienne Carriere2017-11-081-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs integrate a GIC in version 1 that is currently not supported by the trusted firmware. This change hijacks GICv2 driver to handle the GICv1 as GICv1 is compatible enough with GICv2 as far as the platform does not attempt to play with virtualization support or some GICv2 specific power features. Note that current trusted firmware does not use these GICv2 features that are not available in GICv1 Security Extension. Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | tbbr: Add build flag HASH_ALG to let the user to select the SHAQixiang Xu2017-11-213-3/+26
| | | | | | | | | | | | | | | | | | | | The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | GIC: Fix Group 0 enablingJeenu Viswambharan2017-11-134-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | At present, the GIC drivers enable Group 0 interrupts only if there are Secure SPIs listed in the interrupt properties/list. This means that, even if there are Group 0 SGIs/PPIs configured, the group remained disabled in the absence of a Group 0 SPI. Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when corresponding SGIs/PPIs are present. Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | GICv2: Fix populating PE target dataJeenu Viswambharan2017-11-131-3/+20
|/ | | | | | | | | | | | | This patch brings in the following fixes: - The per-PE target data initialized during power up needs to be flushed so as to be visible to other PEs. - Setup per-PE target data for the primary PE as well. At present, this was only setup for secondary PEs when they were powered on. Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Allow specifying interrupt propertiesJeenu Viswambharan2017-10-166-59/+356
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC driver initialization currently allows an array of interrupts to be configured as secure. Future use cases would require more interrupt configuration other than just security, such as priority. This patch introduces a new interrupt property array as part of both GICv2 and GICv3 driver data. The platform can populate the array with interrupt numbers and respective properties. The corresponding driver initialization iterates through the array, and applies interrupt configuration as required. This capability, and the current way of supplying array (or arrays, in case of GICv3) of secure interrupts, are however mutually exclusive. Henceforth, the platform should supply either: - A list of interrupts to be mapped as secure (the current way). Platforms that do this will continue working as they were. With this patch, this scheme is deprecated. - A list of interrupt properties (properties include interrupt group). Individual interrupt properties are specified via. descriptors of type 'interrupt_prop_desc_t', which can be populated with the macro INTR_PROP_DESC(). A run time assert checks that the platform doesn't specify both. Henceforth the old scheme of providing list of secure interrupts is deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require that the interrupt properties are supplied instead of an array of secure interrupts. Add a section to firmware design about configuring secure interrupts. Fixes ARM-software/tf-issues#262 Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add helpers to set interrupt configurationJeenu Viswambharan2017-10-163-0/+45
| | | | | | | | | The helpers perform read-modify-write on GIC*_ICFGR registers, but don't serialise callers. Any serialisation must be taken care of by the callers. Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set priority maskJeenu Viswambharan2017-10-162-0/+46
| | | | | | | API documentation updated. Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set/clear interrupt pendingJeenu Viswambharan2017-10-164-0/+119
| | | | | | | | API documentation updated. Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set interrupt routingJeenu Viswambharan2017-10-164-10/+85
| | | | | | | | | | | SPIs can be routed to either a specific PE, or to any one of all available PEs. API documentation updated. Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963ed Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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