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* Merge changes from topic "bs/libc" into integrationSoby Mathew2019-12-061-3/+3
|\ | | | | | | | | | | | | * changes: libc: Consolidate the size_t and NULL definitions libc: Consolidate unified definitions libc: Unify intmax_t and uintmax_t on AArch32/64
| * libc: Consolidate unified definitionsBence Szépkúti2019-12-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | As supporting architectures aside from AArch32 and AArch64 is not a concern, keeping identical definitions in two places for a large part of the libc seems counterproductive The int128 types were left un-unified as __int128 is not supported by gcc on AArch32 Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf
* | Merge "Enable -Wlogical-op always" into integrationManish Pandey2019-12-031-2/+2
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| * | Enable -Wlogical-op alwaysJustin Chadwell2019-11-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Wlogical-op prevents common errors with using numerical constants where a boolean one is expected as well as when the operands of a logical operator are the same. While these are perfectly valid behavior, they can be a sign that something is slightly off. This patch adds this warning to gcc and it's closest equivalent to clang, while also fixing any warnings that enabling them causes. Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | | Merge "Enable -Wshadow always" into integrationManish Pandey2019-12-031-12/+12
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| * Enable -Wshadow alwaysJustin Chadwell2019-11-191-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | GIC-600: Fix include ordering according to the coding styleMax Shvetsov2019-11-191-3/+3
|/ | | | | Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
* GIC-600: Fix power up sequenceAlexei Fedorov2019-11-151-26/+39
| | | | | | | | | | | | | | | | | | Arm's GIC-600 features a Power Register (GICR_PWRR), which needs to be programmed to enable redistributor operation. Section 3.6.1 in the GIC-600 TRM describes the power-up and power-down sequence in pseudo code, which deviates from the current TF-A implementation in drivers/arm/gic/v3/gic600.c. For powering on a redistributor, the pseudo code suggests to loop over the whole sequence (check for transition, write request bit) instead of just looping over the ready bit read as TF-A does in gic600_pwr_on(). This patch fixes GIC-600 power up sequence according to the TRM. Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Merge "TF-A: Fix non-standard frequency issue in udelay" into integrationSoby Mathew2019-11-141-5/+15
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| * TF-A: Fix non-standard frequency issue in udelayMax Shvetsov2019-11-141-5/+15
| | | | | | | | | | | | | | | | | | Previous implementation of timers assumed that clk_div has pretty representation in MHz (10MHz, 100MHz, etc). Unusual frequencies (99.99MHz) were causing assertion error and made udelay unusable. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac
* | Merge changes from topic "gic600_multichip" into integrationPaul Beesley2019-11-122-0/+337
|\ \ | | | | | | | | | | | | | | | * changes: gic/gic600: add support for multichip configuration plat/arm/gicv3: add support for probing multiple GIC Redistributor frames
| * | gic/gic600: add support for multichip configurationVijayenthiran Subramaniam2019-11-112-0/+337
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
* / SMMUv3:Changed retry loop to delay timer(GENFW-3329)Deepika Bhavnani2019-11-011-4/+8
|/ | | | | | | Instead of retry polling, timer of 1ms is used to poll Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7e028dc68138d2888e3cf0cbed744f5e6bc6ff42
* Correct UART PL011 initialization calculationAvinash Mehta2019-10-081-1/+1
| | | | | | | | | | | | Currently for Armv7 plaforms the quotient calculated in pl011 uart init code is moved to register r1. This patch moves the quotient to register r2 as done for other platforms in the udiv instruction. Value of register r2 is then used to calculate the values for IBRD and FBRD register Change-Id: Ie6622f9f0e6d634378b471df5d02823b492c8a24 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
* gpio: stm32_gpio: do not mix error code typesNicolas Le Bayon2019-10-031-1/+1
| | | | | | Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
* mmc: increase delay between ACMD41 retriesYann Gautier2019-10-031-1/+1
| | | | | | | | | | In the SD Specification, Power Up Diagram of Card figure, the Timeout value for initialization process (ACMD41 command retries) is 1 second. Align to match MMC cards (in mmc_send_op_cond()) and Linux kernel code, and set the delay between ACMD41 command retries to 10ms. Change-Id: I2e07cb9944e7d7b72f2d4b13e0505e6751458091 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Merge changes from topic "ld/stm32-authentication" into integrationSoby Mathew2019-09-273-18/+338
|\ | | | | | | | | | | | | * changes: stm32mp1: add authentication support for stm32image bsec: move bsec_mode_is_closed_device() service to platform crypto: stm32_hash: Add HASH driver
| * stm32mp1: add authentication support for stm32imageLionel Debieve2019-09-231-1/+7
| | | | | | | | | | | | | | | | | | | | | | This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
| * bsec: move bsec_mode_is_closed_device() service to platformLionel Debieve2019-09-201-17/+1
| | | | | | | | | | | | | | | | This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
| * crypto: stm32_hash: Add HASH driverLionel Debieve2019-09-201-0/+330
| | | | | | | | | | | | | | The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
* | Merge changes from topic "amlogic-g12a" into integrationSoby Mathew2019-09-271-4/+1
|\ \ | | | | | | | | | | | | | | | | | | * changes: amlogic: g12a: Add support for the S905X2 (G12A) platform amlogic: makefile: Use PLAT variable when possible amlogic: sha_dma: Move register mappings to platform header
| * | amlogic: sha_dma: Move register mappings to platform headerCarlo Caione2019-09-181-4/+1
| |/ | | | | | | | | | | | | | | | | The registers location for the SHA DMA driver is not unique for the different platforms. Move the mapping out of the driver and into the platform-specific header. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129
* | Merge "GICv3 driver: Fix support for full SPI range" into integrationSoby Mathew2019-09-271-20/+24
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| * | GICv3 driver: Fix support for full SPI rangeAlexei Fedorov2019-09-131-20/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes GICv3 driver bug which causes assertion when full range of SPI INTIDs 32-1019 is supported in GICv3 implementation. Change-Id: Ib6da4b6eea868cff271cb32c7c7570bf5547ab47 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | Merge changes from topic "mp/giv3-discovery" into integrationSoby Mathew2019-09-271-34/+113
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: Migrate ARM platforms to use the new GICv3 API Adding new optional PSCI hook pwr_domain_on_finish_late GICv3: Enable multi socket GIC redistributor frame discovery
| * | | GICv3: Enable multi socket GIC redistributor frame discoveryMadhukar Pappireddy2019-09-251-34/+113
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | Merge changes I0283fc2e,Ib476d024,Iada05f7c into integrationPaul Beesley2019-09-262-9/+10
|\ \ \ | |/ / |/| | | | | | | | | | | | | | * changes: hikey: fix to load FIP by partition table. hikey960: fix to load FIP by partition table drivers: partition: support different block size
| * | drivers: partition: support different block sizeHaojian Zhuang2019-09-182-9/+10
| |/ | | | | | | | | | | | | | | | | The block size of some storage device is 4096-byte long, such as UFS. But PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3
* | rpi3: Move rng driver to driversAndre Przywara2019-09-131-0/+75
| | | | | | | | | | | | | | | | To allow sharing the driver between the RPi3 and RPi4, move the random number generator driver into the generic driver directory. Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | rpi3: Move VC mailbox driver into generic drivers directoryAndre Przywara2019-09-131-0/+82
|/ | | | | | | | To allow sharing the driver between the RPi3 and RPi4, move the mailbox driver into the generic driver directory. Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into ↵Soby Mathew2019-09-131-22/+6
|\ | | | | | | integration
| * stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driverYann Gautier2019-09-101-22/+6
| | | | | | | | | | | | | | | | | | | | The STM32 console driver was pre-pending '\r' before '\n'. It is now managed by the framework with the flag: CONSOLE_FLAG_TRANSLATE_CRLF. Remove the code in driver, and add the flag for STM32MP1. Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Remove RSA PKCS#1 v1.5 support from cert_toolJustin Chadwell2019-09-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed in SHA fe199e3, however, cert_tool is still able to generate certificates in that form. This patch fully removes the ability for cert_tool to generate these certificates. Additionally, this patch also fixes a bug where the issuing certificate was a RSA and the issued certificate was EcDSA. In this case, the issued certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now that PKCS#1 v1.5 support is removed, all certificates that are signed with RSA now use the more modern padding scheme. Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | Support larger RSA key sizes when using MBEDTLSJustin Chadwell2019-09-122-1/+28
| | | | | | | | | | | | | | | | | | | | | | Previously, TF-A could not support large RSA key sizes as the configuration options passed to MBEDTLS prevented storing and performing calculations with the larger, higher-precision numbers required. With these changes to the arguments passed to MBEDTLS, TF-A now supports using 3072 (3K) and 4096 (4K) keys in certificates. Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into ↵Soby Mathew2019-09-1219-5087/+4736
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: qos: update QoS setting rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers rcar_gen3: drivers: ddr_b: Fix line-over-80s rcar_gen3: drivers: ddr_b: Further checkpatch cleanups rcar_gen3: drivers: ddr_b: Clean up camel case rcar_get3: drivers: ddr_b: Basic checkpatch fixes rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B rcar_get3: drivers: ddr: Clean up common code
| * | rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3NChiaki Fujii2019-08-296-22/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | [IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.37. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295
| * | rcar_gen3: drivers: qos: update QoS settingYoshifumi Hosoya2019-08-293-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | [IPL/QoS] - Update M3 Ver.3.0 QoS setting rev.0.04. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I798401f417df6a352d94311ea07a1e96ba562f6a
| * | rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headersMarek Vasut2019-08-296-1896/+1903
| | | | | | | | | | | | | | | | | | | | | Clean up the DDR B header files and remove checkpatch errors. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I9648ef5511df299688fd5284513812d32a1f8064
| * | rcar_gen3: drivers: ddr_b: Fix line-over-80sMarek Vasut2019-08-292-99/+152
| | | | | | | | | | | | | | | | | | | | | | | | Fix as many line-over-80s as possible. There are still a few remaining, which would need further refactoring. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I7225d9fab658d05e3315d8c3fa3c9f3bbb1ab40d
| * | rcar_gen3: drivers: ddr_b: Further checkpatch cleanupsMarek Vasut2019-08-292-480/+291
| | | | | | | | | | | | | | | | | | | | | Address more checkpatch CHECKs and ERRORs, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ife682288cef3afa860571b2aca647c9ffe936125
| * | rcar_gen3: drivers: ddr_b: Clean up camel caseMarek Vasut2019-08-292-616/+616
| | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e
| * | rcar_get3: drivers: ddr_b: Basic checkpatch fixesMarek Vasut2019-08-293-309/+318
| | | | | | | | | | | | | | | | | | | | | Do basic automated checkpatch fixes on the ddr_b, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie401ec049a05d2c4c8044749994391adea171679
| * | rcar_get3: drivers: ddr: Partly unify register macros between DDR A and BMarek Vasut2019-08-296-1756/+1529
| | | | | | | | | | | | | | | | | | | | | | | | The ddr_a and ddr_b register macros are the same for the most part, unify them into a single header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75
| * | rcar_get3: drivers: ddr: Clean up common codeMarek Vasut2019-08-293-62/+53
| | | | | | | | | | | | | | | | | | | | | | | | Do minor coding style changes to the common DDR init code to make it checkpatch compliant and move macros out into rcar_def.h. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
* | | Merge changes from topic "amlogic-refactoring" into integrationSoby Mathew2019-09-122-4/+4
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: amlogic: Fix includes order amlogic: Fix header guards amlogic: Fix prefixes in the SoC specific files amlogic: Fix prefixes in the PM code amlogic: Fix prefixes in the SCPI related code amlogic: Fix prefixes in the MHU code amlogic: Fix prefixes in the SIP/SVC code amlogic: Fix prefixes in the thermal driver amlogic: Fix prefixes in the private header file amlogic: Fix prefixes in the efuse driver amlogic: Fix prefixes in the platform macros file amlogic: Fix prefixes in the helpers file amlogic: Rework Makefiles amlogic: Move the SIP SVC code to common directory amlogic: Move topology file to common directory amlogic: Move thermal code to common directory amlogic: Move MHU code to common directory amlogic: Move efuse code to common directory amlogic: Move platform macros assembly file to common directory amlogic: Introduce unified private header file amlogic: Move SCPI code to common directory amlogic: Move the SHA256 DMA driver to common directory amlogic: Move assembly helpers to common directory amlogic: Introduce directory parameters in the makefiles meson: Rename platform directory to amlogic
| * | amlogic: Move the SHA256 DMA driver to common directoryCarlo Caione2019-09-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The SHA256 DMA driver can be used by multiple SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
| * | meson: Rename platform directory to amlogicCarlo Caione2019-09-052-2/+2
| |/ | | | | | | | | | | | | | | | | Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
* | mmc: stm32_sdmmc2: correctly manage block sizeYann Gautier2019-09-021-16/+10
| | | | | | | | | | | | | | | | DBLOCKSIZE should be filled such as the data size is 2^DBLOCKSIZE. Hence it is calculated with __builtin_ctz. Change-Id: Id6b5ff9b594afc4fc523a388011beed307e6abd1 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | mmc: stm32_sdmmc2: manage max-frequency property from DTYann Gautier2019-09-021-4/+19
| | | | | | | | | | | | | | | | | | If the max-frequency property is provided in the device tree mmc node, it should be managed. The max allowed frequency will be the min between this property value and what the card can support. Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | stm32mp1: move check_header() to common codeYann Gautier2019-09-021-35/+1
| | | | | | | | | | | | | | | | This function can be used on several stm32mp devices, it is then moved in plat/st/common/stm32mp_common.c. Change-Id: I862debe39604410f71a9ddc28713026362e9ecda Signed-off-by: Yann Gautier <yann.gautier@st.com>
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