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* Add support for pointer authenticationAntonio Nino Diaz2019-02-273-1/+29
| | | | | | | | | | | | | | | The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Add ARMv8.3-PAuth registers to CPU contextAntonio Nino Diaz2019-02-272-2/+13
| | | | | | | | | | | | | | | | | | | | | | | ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1834 from thloh85-intel/s10_bl31Antonio Niño Díaz2019-02-271-0/+91
|\ | | | | plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
| * plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platformTien Hock, Loh2019-02-261-0/+91
| | | | | | | | | | | | | | | | | | This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
* | Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz2019-02-221-1/+6
|\ \ | | | | | | Update documentation for STM32MP1 and add Cortex-M4 support
| * | docs: stm32mp1: add links to documentationYann Gautier2019-02-201-1/+6
| |/ | | | | | | | | | | | | | | | | A link to st.com page describing STM32MP1 is added. Add the information about Cortex-M4 embedded in STM32MP1. Correct typo for u-boot command. Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge pull request #1828 from uarif1/masterAntonio Niño Díaz2019-02-211-0/+81
|\ \ | |/ |/| Introduce Versatile Express FVP platform to arm-trusted-firmware.
| * Documentation for Versatile Express Fixed Virtual PlatformsUsama Arif2019-02-191-0/+81
| | | | | | | | | | | | | | | | This documentation contains information about the boot sequence, code location and build procedure for fvp_ve platform. Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c Signed-off-by: Usama Arif <usama.arif@arm.com>
* | Merge pull request #1832 from jts-arm/docsAntonio Niño Díaz2019-02-206-0/+131
|\ \ | | | | | | docs: Document romlib design
| * | docs: Document romlib designSathees Balya2019-02-196-0/+131
| |/ | | | | | | | | | | Change-Id: I2b75be16f452a8ab7c2445ccd519fb057a135812 Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com> Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* / docs: Update documentation about ARMv8.2-TTCNPAntonio Nino Diaz2019-02-191-5/+3
|/ | | | | | | | | Commit 2559b2c8256f ("xlat v2: Dynamically detect need for CnP bit") modified the code to convert the compile-time check for ARMv8.2-TTCNP to a runtime check, but forgot to update the documentation associated to it. Change-Id: I6d33a4de389d976dbdcce65d8fdf138959530669 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* docs: Update note about plat/arm in Porting GuideAntonio Nino Diaz2019-02-131-10/+10
| | | | | | | | | Platforms are not allowed to use any file inside include/plat/arm or plat/arm to prevent dependencies between Arm platforms and non-Arm platforms. Change-Id: I6dc336ab71134c8d2758761fac0e4716e2d7e6ff Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1818 from pbeesley-arm/doc-linksAntonio Niño Díaz2019-02-129-13/+13
|\ | | | | doc: Fix broken external links
| * doc: Fix broken external linksPaul Beesley2019-02-089-14/+14
| | | | | | | | | | | | | | | | | | Using Sphinx linkcheck on the TF-A docs revealed some broken or permanently-redirected links. These have been updated where possible. Change-Id: Ie1fead47972ede3331973759b50ee466264bd2ee Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Doc: Remove useless escape charactersSandrine Bailleux2019-02-0812-180/+180
| | | | | | | | | | | | | | | | Just like has been done in the porting guide a couple of patches earlier, kill all escaped underscore characters in all documents. Change-Id: I7fb5b806412849761d9221a6ce3cbd95ec43d611 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Miscellaneous doc fixes/enhancementsSandrine Bailleux2019-02-084-15/+14
| | | | | | | | | | Change-Id: I915303cea787d9fb188428b98ac6cfc610cc4470 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Porting Guide: Fix some broken linksSandrine Bailleux2019-02-081-2/+2
| | | | | | | | | | | | | | | | Fix links to SCC and FreeBSD. Direct links do not need any special formatting. Change-Id: I00f7343d029a30ec02dfaa0ef393b3197260cab9 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Porting Guide: Remove useless escape charactersSandrine Bailleux2019-02-081-327/+327
|/ | | | | | | | | Replace all occurences of escaped underscore characters by plain ones. This makes the text version of the porting guide easier to read and grep into. Change-Id: I7bf3b292b686be4c6d847a467b6708ac16544c90 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19Antonio Niño Díaz2019-02-062-6/+38
|\ | | | | Tf2.0 tegra downstream rebase 1.25.19
| * docs: add Tegra186 information to nvidia-tegra.rstVarun Wadekar2019-02-051-6/+34
| | | | | | | | | | | | | | | | This patch adds information about the Tegra186 platforms to the docs. Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * Introduce build option to override libcVarun Wadekar2019-02-051-0/+4
| | | | | | | | | | | | | | | | | | This patch introduces a build option 'OVERRIDE_LIBC' that platforms can set to override libc from the BL image. The default value is '0' to keep the library. Change-Id: I10a0b247f6a782eeea4a0359e30a8d79b1e9e4e1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Merge pull request #1804 from antonio-nino-diaz-arm/an/cleanupAntonio Niño Díaz2019-02-051-9/+2
|\ \ | | | | | | Minor cleanup
| * | Remove unneeded include paths in PLAT_INCLUDESAntonio Nino Diaz2019-02-011-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1800 from sandrine-bailleux-arm/sb/load-img-v2Antonio Niño Díaz2019-02-011-3/+0
|\ \ \ | |/ / |/| | Remove dead code related to LOAD_IMAGE_V2=0
| * | Remove dead code related to LOAD_IMAGE_V2=0Sandrine Bailleux2019-01-311-3/+0
| |/ | | | | | | | | | | | | | | Commit ed51b51f7a9163a ("Remove build option LOAD_IMAGE_V2") intended to remove all code related to LOAD_IMAGE_V2=0 but missed a few things. Change-Id: I16aaf52779dd4af1e134e682731328c5f1e5d622 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* / User Guide: Move ARM_PLAT_MT doc to Arm build flagsSandrine Bailleux2019-01-311-6/+6
|/ | | | | | | | ARM_PLAT_MT build flag is specific to Arm platforms so should not be classified as a common build option. Change-Id: I79e411958846759a5b60d770e53f44bbec5febe6 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* doc: Fix broken code blocks in coding guidelinesPaul Beesley2019-01-311-0/+3
| | | | | | | | Sections 2.2, 2.3 and 2.4 contained example code blocks that were not being formatted properly due to missing newlines. Change-Id: I0dbce90c931cf69e4f47d2ccbcc8bc0e20f8fd66 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Merge pull request #1797 from antonio-nino-diaz-arm/an/remove-smccc-v2Antonio Niño Díaz2019-01-311-6/+1
|\ | | | | Remove support for the SMC Calling Convention 2.0
| * Remove support for the SMC Calling Convention 2.0Antonio Nino Diaz2019-01-301-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f370465241c ("Add support for the SMC Calling Convention 2.0"). SMCCC v2.0 is no longer required for SPM, and won't be needed in the future. Removing it makes the SMC handling code less complicated. The SPM implementation based on SPCI and SPRT was using it, but it has been adapted to SMCCC v1.0. Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | doc: Add details on #include orderingPaul Beesley2019-01-291-13/+61
| | | | | | | | | | | | | | | | This patch adds more details on #include directive use, including (pun not intended) the desired ordering, grouping and variants (<> or ""). Change-Id: Ib024ffc4d3577c63179e1bbc408f0d0462026312 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Reorder coding guidelines documentPaul Beesley2019-01-291-128/+137
| | | | | | | | | | | | | | | | This patch attempts to make the guidelines clearer by reordering the sections and grouping similar topics. Change-Id: I1418d6fc060d6403fe3e1978f32fd54b8793ad5b Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Link coding guidelines to user guidePaul Beesley2019-01-292-44/+44
| | | | | | | | | | | | | | | | | | Adds a link from user-guide.rst to coding-guidelines.rst and merges the information about using checkpatch from both files into the user guide document. Change-Id: Iffbb4225836a042d20024faf28b8bdd6b2c4043e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Clarify ssize_t use in coding guidelinesPaul Beesley2019-01-291-1/+3
| | | | | | | | | | Change-Id: I083f673f37495d2e53c704a43a0892231b6eb281 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Add AAPCS link to coding guidelinesPaul Beesley2019-01-291-1/+4
| | | | | | | | | | Change-Id: Id0e6d272b6d3d37eab785273f9c12c093191f3fc Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Add Coding Guidelines documentPaul Beesley2019-01-291-0/+505
|/ | | | | | | | | | | | | | | | This content has been imported and adapted from the TF GitHub wiki article 'ARM-Trusted-Firmware-Coding-Guidelines'. The aim is to increase the visibility of the coding guidelines by including them as part of the documentation that is within the TF repository. Additionally, the documentation can then be linked to by other documents in the docs/ directory without worrying about broken links to, for example, the external wiki. Change-Id: I9d8cd6b5117b707c1a113baeba7fc5e1b4bf33bc Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Merge pull request #1761 from satheesbalya-arm/sb1/sb1_2661_bl31_overlayAntonio Niño Díaz2019-01-251-3/+18
|\ | | | | plat/arm: Save BL2 descriptors to reserved memory.
| * plat/arm: Save BL2 descriptors to reserved memory.Sathees Balya2019-01-231-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory descriptors describing the list of executable images are created in BL2 R/W memory, which could be possibly corrupted later on by BL31/BL32 due to overlay. This patch creates a reserved location in SRAM for these descriptors and are copied over by BL2 before handing over to next BL image. Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR is enabled. Fixes ARM-Software/tf-issues#626 Change-Id: I755735706fa702024b4032f51ed4895b3687377f Signed-off-by: Sathees Balya <sathees.balya@arm.com>
* | Merge pull request #1768 from bryanodonoghue/integration+linaro_warp7-tbbAntonio Niño Díaz2019-01-231-11/+59
|\ \ | |/ |/| Integration+linaro warp7 tbb
| * docs: warp7: Update WaRP7 description for TBBBryan O'Donoghue2019-01-181-11/+59
| | | | | | | | | | | | | | | | | | This patch updates the WaRP7 build descriptions for booting WaRP7 in Trusted Board Boot mode. TBB is the only mode we really intend to support for this board so rather than maintain documentation for the old way of doing it, this patch updates the description for TBB mode only. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
* | Tegra: lib: library for profiling the cold boot pathVarun Wadekar2019-01-181-0/+2
|/ | | | | | | | | | | | | | | | The non secure world would like to profile the boot path for the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure DRAM region (4K) is allocated and the base address is passed to the EL3 firmware. This patch adds a library to allow the platform code to store the tag:timestamp pair to the shared memory. The tegra platform code then uses the `record` method to add timestamps. Original change by Akshay Sharan <asharan@nvidia.com> Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Tegra: support to set the L2 ECC and Parity enable bitHarvey Hsieh2019-01-161-0/+2
| | | | | | | | | | | | | | | | This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Correct typographical errorsPaul Beesley2019-01-159-46/+46
| | | | | | | | | | | Corrects typos in core code, documentation files, drivers, Arm platforms and services. None of the corrections affect code; changes are limited to comments and other documentation. Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* docs: marvell: Fix typo in file build.txtDing Tao2018-12-251-2/+2
| | | | | | Replace "SECURE=0" with "MARVELL_SECURE_BOOT=0". Signed-off-by: Ding Tao <miyatsu@qq.com>
* Merge pull request #1723 from soby-mathew/sm/reset_bl31_fixAntonio Niño Díaz2018-12-181-32/+35
|\ | | | | FVP: Fixes for RESET_TO_BL31
| * docs: User-guide corrections for RESET_TO_BL31Soby Mathew2018-12-171-32/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the user guide instructions for RESET_TO_SP_MIN and RESET_TO_BL31 cases. The load address for BL31 had to be updated because of increase in code size. Also, information about PIE support when RESET_TO_BL31=1 for FVP is added. In the case of RESET_TO_SP_MIN, the RVBAR address was wrong in the instruction. This is also corrected in the patch. Change-Id: I65fe6d28c5cf79bee0a11fbde320d49fcc1aacf5 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1716 from miyatsu/marvell-doc-fix-20181210Antonio Niño Díaz2018-12-171-1/+1
|\ \ | |/ |/| docs: marvell: Fix typo in file build.txt
| * docs: marvell: Fix typo in file build.txtDing Tao2018-12-101-1/+1
| | | | | | | | | | | | Replace "Uboot" with "Ubuntu". Signed-off-by: Ding Tao <miyatsu@qq.com>
* | Merge pull request #1700 from jwerner-chromium/JW_crashfixSoby Mathew2018-12-101-43/+9
|\ \ | |/ |/| MULTI_CONSOLE_API fixes and cleanups
| * plat/common/crash_console_helpers.S: Fix MULTI_CONSOLE_API supportJulius Werner2018-12-061-43/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Crash reporting via the default consoles registered by MULTI_CONSOLE_API has been broken since commit d35cc34 (Console: Use callee-saved registers), which was introduced to allow console drivers written in C. It's not really possible with the current crash reporting framework to support console drivers in C, however we should make sure that the existing assembly drivers that do support crash reporting continue to work through the MULTI_CONSOLE_API. This patch fixes the problem by creating custom console_putc() and console_flush() implementations for the crash reporting case that do not use the stack. Platforms that want to use this feature will have to link plat/common/aarch64/crash_console_helpers.S explicitly. Also update the documentation to better reflect the new reality (of this being an option rather than the expected default for most platforms). Change-Id: Id0c761e5e2fddaf25c277bc7b8ab603946ca73cb Signed-off-by: Julius Werner <jwerner@chromium.org>
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