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* Remove -Wpadded warningJustin Chadwell2019-12-161-4/+3
| | | | | | | | | | | | | | | -Wpadded warns whenever the C compiler automatically includes any padding in a structure. Because TF-A has a large number of structures, this occurs fairly frequently and is incredibly verbose, and as such is unlikely to ever be fixed. The utility of this warning is also extremely limited - knowing that a structure includes padding does not point to the existence of an error, and is probably quite unlikely to indicate actually buggy behaviour. Therefore, it's probably best to keep this warning off at all times. Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* docs: tegra: add support for Tegra194 class of SoCsVarun Wadekar2019-12-101-4/+16
| | | | | | | | This patch adds the Tegra194 SoC information to the nvidia-tegra.rst file. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454
* Merge "Enable Link Time Optimization in GCC" into integrationSoby Mathew2019-12-041-0/+4
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| * Enable Link Time Optimization in GCCzelalem-aweke2019-12-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables LTO for TF-A when compiled with GCC. LTO is disabled by default and is enabled by ENABLE_LTO=1 build option. LTO is enabled only for aarch64 as there seem to be a bug in the aarch32 compiler when LTO is enabled. The changes in the makefiles include: - Adding -flto and associated flags to enable LTO. - Using gcc as a wrapper at link time instead of ld. This is recommended when using LTO as gcc internally takes care of invoking the necessary plugins for LTO. - Adding switches to pass options to ld. - Adding a flag to disable fix for erratum cortex-a53-843419 unless explicitly enabled. This is needed because GCC seem to automatically add the erratum fix when used as a wrapper for LD. Additionally, this patch updates the TF-A user guide with the new build option. Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com> Change-Id: I1188c11974da98434b7dc9344e058cd1eacf5468
* | Merge "Remove unnecessary warning options" into integrationManish Pandey2019-12-031-2/+1
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| * Remove unnecessary warning optionsJustin Chadwell2019-11-191-2/+1
| | | | | | | | | | | | | | | | | | Both -Wmissing-field-initializers and -Wsign-compare are both covered by -Wextra which is enabled at W=1 anyway. Therefore, the explicit options are not required. Change-Id: I2e7d95b5fc14af7c70895859a7ebbeac5bc0d2a4 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | Merge "Changes to support updated register usage in SMCCC v1.2" into integrationAlexei Fedorov2019-11-292-6/+24
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| * | Changes to support updated register usage in SMCCC v1.2Madhukar Pappireddy2019-11-262-6/+24
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From AArch64 state, arguments are passed in registers W0-W7(X0-X7) and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls. From AArch32 state, arguments are passed in registers R0-R7 and results are returned in registers R0-R7 for SMC32 calls. Most of the functions and macros already existed to support using upto 8 registers for passing/returning parameters/results. Added few helper macros for SMC calls from AArch32 state. Link to the specification: https://developer.arm.com/docs/den0028/c Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* / doc: Split the User Guide into multiple filesPaul Beesley2019-11-2727-2325/+2337
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The User Guide document has grown organically over time and now covers a wide range of topics, making it difficult to skim read and extract information from. Currently, it covers these topics and maybe a couple more: - Requirements (hardware, tools, libs) - Checking out the repo - Basic build instructions - A comprehensive list of build flags - FIP packaging - Building specifically for Juno - Firmware update images - EL3 payloads - Preloaded BL33 boot flow - Running on FVPs - Running on Juno I have separated these out into a few groups that become new documents. Broadly speaking, build instructions for the tools, for TF-A generally, and for specific scenarios are separated. Content relating to specific platforms (Juno and the FVPs are Arm-specific platforms, essentially) has been moved into the documentation that is specific to those platforms, under docs/plat/arm. Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Merge changes from topic "lm/improve_memory_layout" into integrationSandrine Bailleux2019-11-181-0/+15
|\ | | | | | | | | | | * changes: DOC: Update ROMLIB page with memory impact info ROMLIB: Optimize memory layout when ROMLIB is used
| * DOC: Update ROMLIB page with memory impact infoLouis Mayencourt2019-11-181-0/+15
| | | | | | | | | | | | | | | | Complete the Library at ROM documentation with information regarding the memory impact of the feature. Change-Id: I5a10620a8e94f123021bb19523a36d558b330deb Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | doc: Add missing terms to the glossaryPaul Beesley2019-11-142-2/+30
| | | | | | | | | | Change-Id: Ibca94eae1a9a89c98b4d7cb5b4fd8943bf854030 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Merge "docs: Add Cortex-Hercules/HerculesAE CPU support" into integrationSandrine Bailleux2019-11-131-0/+4
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| * | docs: Add Cortex-Hercules/HerculesAE CPU supportlaurenw-arm2019-11-131-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ia1ff13be1308e63c2854d2b6e5f6651750186abe
* | | Merge "TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)" ↵Paul Beesley2019-11-121-5/+16
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| * | | TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)Alexei Fedorov2019-11-041-5/+16
| |/ / | | | | | | | | | | | | | | | | | | This patch updates description of Security Advisory TFV-5. Change-Id: Ieaee0b51a79843345b1aca5d0e20c4964beb3c95 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* / / doc: Fix syntax erros in I/O storage layer plantuml diagramsSandrine Bailleux2019-10-283-9/+9
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the plantuml diagrams in the I/O storage abstraction layer documentation are absent from the rendered version of the porting guide. The build log (see [1] for example) reports a syntax error in these files. This is due to the usage of the 'order' keyword on the participants list, which does not seem to be supported by the version of plantuml installed on the ReadTheDocs server. Fix these syntax errors by removing the 'order' keyword altogether. We simply rely on the participants being declared in the desired order, which will be the order of display, according to the plantuml documentation. [1] https://readthedocs.org/api/v2/build/9870345.txt Change-Id: Ife35c74cb2f1dac28bda07df395244639a8d6a2b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Merge "Update change log for v2.2 Release" into integrationPaul Beesley2019-10-221-0/+416
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| * | Update change log for v2.2 Releaselaurenw-arm2019-10-211-0/+416
| | | | | | | | | | | | | | | Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I53a7706016539e7de7fdbe87b786d99665bbe1d8
* | | Merge "Update release-information for v2.2 Release" into integrationPaul Beesley2019-10-221-25/+11
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| * | | Update release-information for v2.2 Releaselaurenw-arm2019-10-221-25/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed deprecated interfaces that have been removed from the TF-A project, updated the deprecated list with new deprecations for v2.2 Release, added upcoming release information, remove mentions of PR from github. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com> Change-Id: I2b59d351cde9860ad0dcb6520a8bd2827ad403cf
* | | | doc: Final, pre-release fixes and updatesPaul Beesley2019-10-225-10/+13
|/ / / | | | | | | | | | | | | | | | | | | | | | A small set of misc changes to ensure correctness before the v2.2 release tagging. Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | doc: Expand contact information in About sectionPaul Beesley2019-10-221-7/+37
| | | | | | | | | | | | | | | | | | | | | | | | Giving a bit more background information about the issue tracker and mailing lists. Change-Id: I68921d54e3113d348f1e16c685f74d32df2ca19f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | doc: Move platform list to the Platform Ports index pagePaul Beesley2019-10-212-84/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The list of upstream platforms on the index page is growing quite long, especially with all the FVP variants being listed individually. This patch leverages the "Platform Ports" chapter in the docs table of contents to condense this information. Almost all platform ports now have documentation, so the table of contents serves as the list of upstream platforms by itself. For those upstream platforms that do not have corresponding documentation, the top-level "Platform Ports" page mentions them individually. It also mentions each Arm FVP, just as the index page did before. Note that there is an in-progress patch that creates new platform port documentation for the Arm Juno and Arm FVP platforms, so this list of "other platforms" will soon be reduced further as those platforms become part of the table of contents as well. Change-Id: I6b1eab8cba71a599d85a6e22553a34b07f213268 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | doc: Move "About" content from index.rst to a new chapterPaul Beesley2019-10-218-154/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The index.rst page is now the primary landing page for the TF-A documentation. It contains quite a lot of content these days, including: - The project purpose and general intro - A list of functionality - A list of planned functionality - A list of supported platforms - "Getting started" links to other documents - Contact information for raising issues This patch creates an "About" chapter in the table of contents and moves some content there. In order, the above listed content: - Stayed where it is. This is the right place for it. - Moved to About->Features - Moved to About->Features (in subsection) - Stayed where it is. Moved in a later patch. - Was expanded in-place - Moved to About->Contact Change-Id: I254bb87560fd09140b9e485cf15246892aa45943 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | Merge "Fix documentation" into integrationPaul Beesley2019-10-182-5/+3
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| * | | Fix documentationArtsem Artsemenka2019-10-152-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | User guide: 1. Remove obsolete note saying only FVP is supported with AArch32 2. Switch compiler for Juno AArch32 to arm-eabi 3. Mention SOFTWARE folder in Juno Linaro release Index.rst: 1. Switch default FVP model to Version 11.6 Build 45 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: Ib47a2ea314e2b8394a20189bf91796de0e17de53
* | | | doc: Remove version and release variables from conf.pyPaul Beesley2019-10-171-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We would need to update this version for the release but, in fact, it is not required for our publishing workflow; the hosted version of the docs uses git commit/tag information in place of these variables anyway. Instead of updating the version, just remove these variables entirely. Change-Id: I424c4e45786e87604e91c7197b7983579afe4806 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | | Merge "doc: Update Linaro release mentioned on index page" into integrationPaul Beesley2019-10-151-2/+2
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| * | | doc: Update Linaro release mentioned on index pagePaul Beesley2019-10-151-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The version of the Linaro release that is used for testing was updated in 35010bb8 and the user guide was updated with the correct version, however the version is also mentioned on the index page and that was missed. Update the index page with the new version. We can come back and de-duplicate this content later, to ease future maintenance. Change-Id: I3fe83d7a1c59ab8d3ce2b18bcc23e16c93f7af97 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* / | doc: Misc syntax and spelling fixesPaul Beesley2019-10-1110-19/+21
|/ / | | | | | | | | | | | | | | | | | | Tidying up a few Sphinx warnings that had built-up over time. None of these are critical but it cleans up the Sphinx output. At the same time, fixing some spelling errors that were detected. Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Add guide for building the docs locallyPaul Beesley2019-10-092-0/+78
| | | | | | | | | | | | | | | | | | This new page contains instructions for doing a local build of the documentation, plus information on the environment setup that needs to be done beforehand. Change-Id: If563145ab40639cabbe25d0f62759981a33692c6 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: De-duplicate readme and license filesPaul Beesley2019-10-081-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The readme.rst and license.rst files in the project root overlap with the index.rst and license.rst files in the docs/ folder. We need to use the latter when building the documentation, as Sphinx requires all included files to be under a common root. However, the files in the root are currently used by the cgit and Github viewers. Using symlinks in Git presents some difficulties so the best course of action is likely to leave these files but in stub form. The license.rst file in the root will simply tell the reader to refer to docs/license.rst. The readme.rst file will contain a small amount of content that is derived from the docs/index.rst file, so that the Github main page will have something valid to show, but it will also contain a link to the full documentation on ReadTheDocs. Change-Id: I6dc46f08777e8d7ecb32ca7afc07a28486c9f77a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | doc: Convert internal links to RST formatPaul Beesley2019-10-0828-579/+352
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently links between documents are using the format: <path/to/><filename>.rst This was required for services like GitHub because they render each document in isolation - linking to another document is like linking to any other file, just provide the full path. However, with the new approach, the .rst files are only the raw source for the documents. Once the documents have been rendered the output is now in another format (HTML in our case) and so, when linking to another document, the link must point to the rendered version and not the .rst file. The RST spec provides a few methods for linking between content. The parent of this patch enabled the automatic creation of anchors for document titles - we will use these anchors as the targets for our links. Additional anchors can be added by hand if needed, on section and sub-section titles, for example. An example of this new format, for a document with the title "Firmware Design" is :ref:`Firmware Design`. One big advantage of this is that anchors are not dependent on paths. We can then move documents around, even between directories, without breaking any links between documents. Links will need to be updated only if the title of a document changes. Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* doc: Add more missing platformsPaul Beesley2019-10-072-2/+5
| | | | | | | | | Add meson-g12a, qemu-sbsa and rpi4 to the documentation index so that they will have their docs rendered and integrated into the table of contents. Change-Id: Id972bf2fee67312dd7bff29f92bea67842e62431 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Merge "Neoverse N1 Errata Workaround 1542419" into integrationSoby Mathew2019-10-071-0/+3
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| * Neoverse N1 Errata Workaround 1542419laurenw-arm2019-10-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
* | Merge "Fix the CAS spinlock implementation" into integrationSoby Mathew2019-10-072-2/+9
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| * | Fix the CAS spinlock implementationSoby Mathew2019-10-042-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the spinlock implementation use ARMv8.1-LSE CAS instruction based on a platform build option. The CAS-based implementation used to be unconditionally selected for all ARM8.1+ platforms. The previous CAS spinlock implementation had a bug wherein the spin_unlock() implementation had an `sev` after `stlr` which is not sufficient. A dsb is needed to ensure that the stlr completes prior to the sev. Having a dsb is heavyweight and a better solution would be to use load exclusive semantics to monitor the lock and wake up from wfe when a store happens to the lock. The patch implements the same. Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
* | | Merge changes from topic "qemu_sbsa" into integrationSoby Mathew2019-10-031-0/+48
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1 qemu/qemu_sbsa: Adding Qemu SBSA platform
| * | qemu/qemu_sbsa: Adding Qemu SBSA platformRadoslaw Biernacki2019-10-011-0/+48
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces Qemu SBSA platform. Both platform specific files where copied from qemu/qemu with changes for DRAM base above 32bit and removal of ARMv7 conditional defines/code. Documentation is aligned to rest of SBSA patches along the series and planed changes in edk2-platform repo. Fixes ARM-software/tf-issues#602 Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
* | doc: Fix GCC version to 8.3-2019.03Louis Mayencourt2019-10-021-3/+1
| | | | | | | | | | Change-Id: I3b866e927d93f4b690aa4891940fc8afabf4146e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Merge "doc: Migrate to Linaro release 19.06" into integrationSandrine Bailleux2019-10-011-20/+17
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| * doc: Migrate to Linaro release 19.06zelalem-aweke2019-09-301-20/+17
| | | | | | | | | | | | | | | | | | - Updated Linaro release version number to 19.06 - Updated links to Linaro instructions and releases - Removed the Linaro old releases link Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com> Change-Id: Ib786728106961e89182b42183e7b889f6fc74190
* | Merge "doc: Fix platform port inclusion" into integrationSoby Mathew2019-09-276-24/+30
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| * | doc: Fix platform port inclusionPaul Beesley2019-09-256-24/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch: - Adds any leftover platform ports that were not having their documentation built (not in the index.rst table of contents) - Corrects a handful of RST formatting errors that cause poor rendering - Reorders the list of platforms so that they are displayed in alphabetical order Change-Id: If8c135a822d581c3c5c4fca2936d501ccfd2e94c Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | Merge changes from topic "amlogic-g12a" into integrationSoby Mathew2019-09-272-0/+35
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: amlogic: g12a: Add support for the S905X2 (G12A) platform amlogic: makefile: Use PLAT variable when possible amlogic: sha_dma: Move register mappings to platform header
| * | | amlogic: g12a: Add support for the S905X2 (G12A) platformCarlo Caione2019-09-262-0/+35
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux. Tested on a SEI510 board. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ife958f10e815a4530292c45446adb71239f3367f
* | | Merge changes from topic "raspberry-pi-4-support" into integrationSoby Mathew2019-09-271-0/+85
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: rpi4: Add initial documentation file rpi4: Add stdout-path to device tree rpi4: Add GIC maintenance interrupt to GIC DT node rpi4: Cleanup memory regions, move pens to first page rpi4: Reserve resident BL31 region from non-secure world rpi4: Amend DTB to advertise PSCI rpi4: Determine BL33 entry point at runtime rpi4: Accommodate "armstub8.bin" header at the beginning of BL31 image Add basic support for Raspberry Pi 4 rpi3: Allow runtime determination of UART base clock rate FDT helper functions: Respect architecture in PSCI function IDs FDT helper functions: Add function documentation
| * | | rpi4: Add initial documentation fileAndre Przywara2019-09-251-0/+85
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the Raspberry Pi4 port is now in a usable state, add the build instructions together with some background information to the documentation directory. The port differs quite a bit from the Raspberry Pi 3, so we use a separate file for that. Change-Id: I7d9f5967fdf3ec3bfe97d78141f59cbcf03388d4 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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