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| author | Varun Wadekar <vwadekar@nvidia.com> | 2019-12-03 14:14:12 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-12-10 10:06:48 -0800 |
| commit | fbd9eb58e60f73a45a59b787eb405f19a3561530 (patch) | |
| tree | 78d4d7ee34d6110b892801a663b45677bef57fe5 /docs | |
| parent | fba54d5568fcfad5334319617c959416fe865e0c (diff) | |
| download | platform_external_arm-trusted-firmware-fbd9eb58e60f73a45a59b787eb405f19a3561530.tar.gz platform_external_arm-trusted-firmware-fbd9eb58e60f73a45a59b787eb405f19a3561530.tar.bz2 platform_external_arm-trusted-firmware-fbd9eb58e60f73a45a59b787eb405f19a3561530.zip | |
docs: tegra: add support for Tegra194 class of SoCs
This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/plat/nvidia-tegra.rst | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index bc9e35b4f..02ff38bef 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -1,6 +1,17 @@ NVIDIA Tegra ============ +- .. rubric:: T194 + :name: t194 + +T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor +configuration. The Carmel cores support the ARM Architecture version 8.2, +executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel +processors are organized as four dual-core clusters, where each cluster has +a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects +these processor complexes and allows heterogeneous multi-processing with all +eight cores if required. + - .. rubric:: T186 :name: t186 @@ -78,9 +89,10 @@ their dispatchers in the image without changing any makefiles. These are the supported Trusted OS' by Tegra platforms. -Tegra132: TLK -Tegra210: TLK and Trusty -Tegra186: Trusty +- Tegra132: TLK +- Tegra210: TLK and Trusty +- Tegra186: Trusty +- Tegra194: Trusty Scatter files ------------- @@ -98,7 +110,7 @@ Preparing the BL31 image to run on Tegra SoCs .. code:: shell CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ - TARGET_SOC=<target-soc e.g. t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> + TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> bl31 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` |