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* fconf: necessary modifications to support fconf in BL31 & SP_MINMadhukar Pappireddy2020-03-111-0/+10
| | | | | | | | | | | | | | | | | | | | Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN. Created few populator() functions which parse HW_CONFIG device tree and registered them with fconf framework. Many of the changes are only applicable for fvp platform. This patch: 1. Adds necessary symbols and sections in BL31, SP_MIN linker script 2. Adds necessary memory map entry for translation in BL31, SP_MIN 3. Creates an abstraction layer for hardware configuration based on fconf framework 4. Adds necessary changes to build flow (makefiles) 5. Minimal callback to read hw_config dtb for capturing properties related to GIC(interrupt-controller node) 6. updates the fconf documentation Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge changes from topic "spmd" into integrationOlivier Deprez2020-02-111-0/+1
|\ | | | | | | | | | | | | | | | | | | * changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0 spec SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP SPMD: add support for an example SPM core manifest SPMD: add SPCI Beta 0 specification header file
| * SPMD: enable SPM dispatcher supportAchin Gupta2020-02-101-0/+1
| | | | | | | | | | | | | | | | | | This patch adds support to the build system to include support for the SPM dispatcher when the SPD configuration option is spmd. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: Ic1ae50ecd7403fcbcf1d318abdbd6ebdc642f732
* | Make PAC demangling more genericAlexei Fedorov2020-02-071-1/+6
|/ | | | | | | | | | | At the moment, address demangling is only used by the backtrace functionality. However, at some point, other parts of the TF-A codebase may want to use it. The 'demangle_address' function is replaced with a single XPACI instruction which is also added in 'do_crash_reporting()'. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I4424dcd54d5bf0a5f9b2a0a84c4e565eec7329ec
* Merge "Coverity: remove unnecessary header file includes" into integrationMark Dykes2020-02-041-2/+1
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| * Coverity: remove unnecessary header file includesZelalem2020-02-041-2/+1
| | | | | | | | | | | | | | | | This patch removes unnecessary header file includes discovered by Coverity HFA option. Change-Id: I2827c37c1c24866c87db0e206e681900545925d4 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* | Merge changes from topic "mp/separate_nobits" into integrationSandrine Bailleux2020-02-043-8/+14
|\ \ | |/ |/| | | | | | | * changes: plat/arm: Add support for SEPARATE_NOBITS_REGION Changes necessary to support SEPARATE_NOBITS_REGION feature
| * Changes necessary to support SEPARATE_NOBITS_REGION featureMadhukar Pappireddy2020-01-273-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since BL31 PROGBITS and BL31 NOBITS sections are going to be in non-adjacent memory regions, potentially far from each other, some fixes are needed to support it completely. 1. adr instruction only allows computing the effective address of a location only within 1MB range of the PC. However, adrp instruction together with an add permits position independent address of any location with 4GB range of PC. 2. Since BL31 _RW_END_ marks the end of BL31 image, care must be taken that it is aligned to page size since we map this memory region in BL31 using xlat_v2 lib utils which mandate alignment of image size to page granularity. Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "Use correct type when reading SCR register" into integrationAlexei Fedorov2020-01-301-10/+10
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| * | Use correct type when reading SCR registerLouis Mayencourt2020-01-281-10/+10
| |/ | | | | | | | | | | | | | | The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* / BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE workMasahiro Yamada2020-01-241-0/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When I tried ENABLE_PIE for my PLAT=uniphier platform, BL31 crashed at its entry. When it is built with ENABLE_PIE=1, some sections are inserted before the executable code. $ make PLAT=uniphier CROSS_COMPILE=aarch64-linux-gnu- ENABLE_PIE=1 bl31 $ aarch64-linux-gnu-objdump -h build/uniphier/release/bl31/bl31.elf | head -n 13 build/uniphier/release/bl31/bl31.elf: file format elf64-littleaarch64 Sections: Idx Name Size VMA LMA File off Algn 0 .dynsym 000002a0 0000000081000000 0000000081000000 00010000 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .dynstr 000002a0 00000000810002a0 00000000810002a0 000102a0 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .hash 00000124 0000000081000540 0000000081000540 00010540 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 ro 0000699c 0000000081000664 0000000081000664 00010664 2**11 CONTENTS, ALLOC, LOAD, CODE The previous stage loader generally jumps over to the base address of BL31, where no valid instruction exists. I checked the linker script of Linux (arch/arm64/kernel/vmlinux.lds.S) and U-Boot (arch/arm/cpu/armv8/u-boot.lds), both of which support relocation. They simply discard those sections. Do similar in TF-A too. Change-Id: I6c33e9143856765d4ffa24f3924b0ab51a17cde9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Prevent speculative execution past ERETAnthony Steinhauser2020-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
* bl31: Split into two separate memory regionsSamuel Holland2019-12-291-4/+36
| | | | | | | | | | | | | | | | | Some platforms are extremely memory constrained and must split BL31 between multiple non-contiguous areas in SRAM. Allow the NOBITS sections (.bss, stacks, page tables, and coherent memory) to be placed in a separate region of RAM from the loaded firmware image. Because the NOBITS region may be at a lower address than the rest of BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this region, or el3_entrypoint_common would attempt to invalidate the dcache for the entire address space. New symbols __NOBITS_{START,END}__ are added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the NOBITS region is invalidated separately. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37
* Merge "debugfs: add 9p device interface" into integrationMark Dykes2019-12-201-0/+5
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| * debugfs: add 9p device interfaceOlivier Deprez2019-12-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The 9p interface provides abstraction layers allowing the software that uses devices to be independent from the hardware. This patch provides a file system abstraction to link drivers to their devices and propose a common interface to expose driver operations to higher layers. This file system can be used to access and configure a device by doing read/write operations. Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255
* | spm-mm: Rename component makefilePaul Beesley2019-12-201-1/+1
| | | | | | | | | | Change-Id: Idcd2a35cd2b30d77a7ca031f7e0172814bdb8cab Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | spm: Remove SPM Alpha 1 prototype and support filesPaul Beesley2019-12-202-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Secure Partition Manager (SPM) prototype implementation is being removed. This is preparatory work for putting in place a dispatcher component that, in turn, enables partition managers at S-EL2 / S-EL1. This patch removes: - The core service files (std_svc/spm) - The Resource Descriptor headers (include/services) - SPRT protocol support and service definitions - SPCI protocol support and service definitions Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426 Signed-off-by: Paul Beesley <paul.beesley@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
* | Remove dependency between SPM_MM and ENABLE_SPM build flagsPaul Beesley2019-12-202-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently. Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1. After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive. Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made. Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Merge changes from topic "bs/pmf32" into integrationGyörgy Szing2019-12-201-1/+1
|\ \ | | | | | | | | | | | | | | | * changes: pmf: Make the runtime instrumentation work on AArch32 SiP: Don't validate entrypoint if state switch is impossible
| * | pmf: Make the runtime instrumentation work on AArch32Bence Szépkúti2019-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ported the pmf asm macros and the asm code in the bl31 entrypoint necessary for the instrumentation to AArch32. Since smc dispatch is handled by the bl32 payload on AArch32, we provide this service only if AARCH32_SP=sp_min is set. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
* | | aarch64: Fix stack pointer maintenance on EA handling pathJan Dabros2019-12-181-4/+9
|/ / | | | | | | | | | | | | | | | | | | EA handlers for exceptions taken from lower ELs at the end invokes el3_exit function. However there was a bug with sp maintenance which resulted in el3_exit setting runtime stack to context. This in turn caused memory corruption on consecutive EL3 entries. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I0424245c27c369c864506f4baa719968890ce659
* | Merge "PIE: make call to GDT relocation fixup generalized" into integrationSoby Mathew2019-12-121-14/+6
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| * PIE: make call to GDT relocation fixup generalizedManish Pandey2019-12-121-14/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead806 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | Reduce space lost to object alignmentSamuel Holland2019-12-041-6/+6
|/ | | | | | | | | | | | | | | | | | | | | | Currently, sections within .text/.rodata/.data/.bss are emitted in the order they are seen by the linker. This leads to wasted space, when a section with a larger alignment follows one with a smaller alignment. We can avoid this wasted space by sorting the sections. To take full advantage of this, we must disable generation of common symbols, so "common" data can be sorted along with the rest of .bss. An example of the improvement, from `make DEBUG=1 PLAT=sun50i_a64 bl31`: .text => no change .rodata => 16 bytes saved .data => 11 bytes saved .bss => 576 bytes saved As a side effect, the addition of `-fno-common` in TF_CFLAGS makes it easier to spot bugs in header files. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I073630a9b0b84e7302a7a500d4bb4b547be01d51
* Neoverse N1 Errata Workaround 1542419laurenw-arm2019-10-041-6/+33
| | | | | | | | | | | | | | | Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
* Refactor ARMv8.3 Pointer Authentication support codeAlexei Fedorov2019-09-134-95/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Add UBSAN support and handlersJustin Chadwell2019-09-111-0/+57
| | | | | | | | | | | | | This patch adds support for the Undefined Behaviour sanitizer. There are two types of support offered - minimalistic trapping support which essentially immediately crashes on undefined behaviour and full support with full debug messages. The full support relies on ubsan.c which has been adapted from code used by OPTEE. Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* Move assembly newline function into common debug codeJustin Chadwell2019-08-291-10/+2
| | | | | | | | | Printing a newline is a relatively common functionality for code to want to do. Therefore, this patch now moves this function into a common part of the code that anyone can use. Change-Id: I2cad699fde00ef8d2aabf8bf35742ddd88d090ba Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* Merge "AArch64: Disable Secure Cycle Counter" into integrationPaul Beesley2019-08-232-0/+36
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| * AArch64: Disable Secure Cycle CounterAlexei Fedorov2019-08-212-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | AArch64: Align crash reporting outputAlexei Fedorov2019-08-151-7/+25
|/ | | | | | | | This patch modifies crash reporting for AArch64 to provide aligned output of register dump and GIC registers. Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Fix BL31 crash reporting on AArch64 only machinesImre Kis2019-07-221-20/+30
| | | | | | | | The AArch32 system registers are not listed if the platform supports AArch64 only. Change-Id: I087a10ae6e7cad1bb52775a344635dbac1f12679 Signed-off-by: Imre Kis <imre.kis@arm.com>
* Add support for Branch Target IdentificationAlexei Fedorov2019-05-242-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Rework smc_unknown return code path in smc_handlerMadhukar Pappireddy2019-05-211-29/+28
| | | | | | | | | | | | | | | The intention of this patch is to leverage the existing el3_exit() return routine for smc_unknown return path rather than a custom set of instructions. In order to leverage el3_exit(), the necessary counteraction (i.e., saving the system registers apart from GP registers) must be performed. Hence a series of instructions which save system registers( like SPSR_EL3, SCR_EL3 etc) to stack are moved to the top of group of instructions which essentially decode the OEN from the smc function identifier and obtain the specific service handler in rt_svc_descs_array. This ensures that the control flow for both known and unknown smc calls will be similar. Change-Id: I67f94cfcba176bf8aee1a446fb58a4e383905a87 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Fix restoration of PAuth contextAlexei Fedorov2019-04-051-1/+1
| | | | | | | | Replace call to pauth_context_save() with pauth_context_restore() in case of unknown SMC call. Change-Id: Ib863d979faa7831052b33e8ac73913e2f661f9a0 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* PIE: Fix reloc at the beginning of bl31 entrypointLouis Mayencourt2019-03-251-12/+13
| | | | | | | | | The relocation fixup code must be called at the beginning of bl31 entrypoint to ensure that CPU specific reset handlers are fixed up for relocations. Change-Id: Icb04eacb2d4c26c26b08b768d871d2c82777babb Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Restore PAuth context in case of unknown SMC callAlexei Fedorov2019-03-181-0/+3
| | | | | Change-Id: I8fb346743b7afddbb8bf5908db4f27ee5a26f99b Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* BL31: Enable pointer authentication support in warm boot pathAlexei Fedorov2019-03-071-0/+13
| | | | | | | | | | | | | | | In the current Pointer Authentication support added in commit b86048c40cb7d9ccd7aeac1681945676a6dc36ff PAuth gets enabled in BL31 cold boot entrypoint only, (see bl31_entrypoint() in bl31\aarch64\bl31_entrypoint.S) but not in bl31_warm_entrypoint(). This results in EnIA bit [31] in SCTLR_EL3 not being set and pointer authentication disabled after CPU wake-up event. Fixes ARM-software/tf-issues#684 Change-Id: I27a67804764dfba2a6d72ca119ca2bcff4f536d6 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Minor changes to documentation and commentsAntonio Nino Diaz2019-02-282-5/+5
| | | | | | | Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* BL31: Enable pointer authentication supportAntonio Nino Diaz2019-02-273-10/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +192 | +1536 | +0 | +0 | | | 0.3% | 3.1% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +1848 | +1536 | +16 | +0 | | | 3.3% | 3.1% | 3.1% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I43db7e509a4f39da6599ec2faa690d197573ec1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Add support for pointer authenticationAntonio Nino Diaz2019-02-272-0/+16
| | | | | | | | | | | | | | | The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Add ARMv8.3-PAuth registers to CPU contextAntonio Nino Diaz2019-02-272-3/+24
| | | | | | | | | | | | | | | | | | | | | | | ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1810 from antonio-nino-diaz-arm/an/setjmpAntonio Niño Díaz2019-02-111-1/+0
|\ | | | | Make setjmp/longjmp compliant with the C standard and move them to libc
| * libc: Move setjmp to libc folderAntonio Nino Diaz2019-02-081-1/+0
| | | | | | | | | | | | | | | | Now that setjmp() and longjmp() are compliant with the standard they can be moved with the other libc files. Change-Id: Iea3b91c34eb353ace5e171e72f331602d57774d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | locks: linker variables to calculate per-cpu bakery lock sizeVarun Wadekar2019-02-071-1/+3
|/ | | | | | | | | | | This patch introduces explicit linker variables to mark the start and end of the per-cpu bakery lock section to help bakery_lock_normal.c calculate the size of the section. This patch removes the previously used '__PERCPU_BAKERY_LOCK_SIZE__' linker variable to make the code uniform across GNU linker and ARM linker. Change-Id: Ie0c51702cbc0fe8a2076005344a1fcebb48e7cca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Remove support for the SMC Calling Convention 2.0Antonio Nino Diaz2019-01-301-73/+12
| | | | | | | | | | | | | | This reverts commit 2f370465241c ("Add support for the SMC Calling Convention 2.0"). SMCCC v2.0 is no longer required for SPM, and won't be needed in the future. Removing it makes the SMC handling code less complicated. The SPM implementation based on SPCI and SPRT was using it, but it has been adapted to SMCCC v1.0. Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Rename folder of SPM based on MMAntonio Nino Diaz2019-01-221-2/+2
| | | | | | | This implementation is no longer deprecated. Change-Id: I68552d0fd5ba9f08fad4345e4657e8e3c5362a36 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Rename SPM_DEPRECATED flag to SPM_MMAntonio Nino Diaz2019-01-221-2/+2
| | | | | | | | | The SPM implementation based on MM is going to be kept for the foreseeable future. Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
* Merge pull request #1738 from ardbiesheuvel/synquacer-spmSoby Mathew2019-01-161-1/+8
|\ | | | | synquacer: add SPM support
| * spm: permit platform to override the VMA placement of the vector tableArd Biesheuvel2019-01-151-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some systems, it may be preferred to place the secure EL1/0 vector table outside of the static placement of the BL31 image itself, for instance when the latter is located in non-shareable SRAM which does not tolerate inner shareable WBWA mappings (as is the case on SynQuacer) So permit the platform to #define SPM_SHIM_EXCEPTIONS_VMA in its supplementary linker script, in which case it will be used as the VMA region for the vector table. Note that the LMA does not change, and it is up to the platform to copy the contents to the right place at init time. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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