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| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2020-01-27 15:32:15 -0600 |
|---|---|---|
| committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2020-01-27 15:33:24 -0600 |
| commit | c367b75e8517f76182e196548ee098e27ef3a2c5 (patch) | |
| tree | 0cd1be78bd130bb6eb3636ba2475c92bc987871b /bl31 | |
| parent | 9054018bd5c12b16ef55ea41fcf8cdb15a24ae18 (diff) | |
| download | platform_external_arm-trusted-firmware-c367b75e8517f76182e196548ee098e27ef3a2c5.tar.gz platform_external_arm-trusted-firmware-c367b75e8517f76182e196548ee098e27ef3a2c5.tar.bz2 platform_external_arm-trusted-firmware-c367b75e8517f76182e196548ee098e27ef3a2c5.zip | |
Changes necessary to support SEPARATE_NOBITS_REGION feature
Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.
1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.
2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.
Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 14 | ||||
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 5 | ||||
| -rw-r--r-- | bl31/bl31.ld.S | 3 |
3 files changed, 14 insertions, 8 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 665a05e88..2d672dd12 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -110,13 +110,17 @@ func bl31_entrypoint * caches and participate in coherency. * -------------------------------------------------------------------- */ - adr x0, __DATA_START__ - adr x1, __DATA_END__ + adrp x0, __DATA_START__ + add x0, x0, :lo12:__DATA_START__ + adrp x1, __DATA_END__ + add x1, x1, :lo12:__DATA_END__ sub x1, x1, x0 bl clean_dcache_range - adr x0, __BSS_START__ - adr x1, __BSS_END__ + adrp x0, __BSS_START__ + add x0, x0, :lo12:__BSS_START__ + adrp x1, __BSS_END__ + add x1, x1, :lo12:__BSS_END__ sub x1, x1, x0 bl clean_dcache_range diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 7f739a9aa..5b3738868 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -414,7 +414,8 @@ smc_handler64: orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH /* Load descriptor index from array of indices */ - adr x14, rt_svc_descs_indices + adrp x14, rt_svc_descs_indices + add x14, x14, :lo12:rt_svc_descs_indices ldrb w15, [x14, x16] /* Any index greater than 127 is invalid. Check bit 7. */ diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 42227f0f3..86fe23608 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -208,6 +208,7 @@ SECTIONS * Define a linker symbol to mark end of the RW memory area for this * image. */ + . = ALIGN(PAGE_SIZE); __RW_END__ = .; __BL31_END__ = .; |