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path: root/bl31/aarch64/bl31_entrypoint.S
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* Sanitise includes across codebaseAntonio Nino Diaz2019-01-041-5/+6
* PIE: Position Independant Executable support for BL31Soby Mathew2018-10-291-0/+13
* Remove some MISRA defects in common codeAntonio Nino Diaz2018-10-041-2/+2
* DynamIQ: Enable MMU without using stackJeenu Viswambharan2018-06-271-7/+4
* Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatchdavidcunado-arm2018-02-281-1/+1
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| * Add comments about mismatched TCR_ELx and xlat tablesAntonio Nino Diaz2018-02-271-2/+2
* | Introduce the new BL handover interfaceSoby Mathew2018-02-261-15/+13
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* Fully initialise essential control registersDavid Cunado2017-06-211-6/+6
* Use SPDX license identifiersdp-arm2017-05-031-25/+1
* PSCI: Build option to enable D-Caches early in warmbootSoby Mathew2017-04-191-15/+16
* Merge pull request #860 from jeenu-arm/hw-asstd-cohdavidcunado-arm2017-03-171-16/+21
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| * Enable data caches early with hardware-assisted coherencyJeenu Viswambharan2017-03-021-17/+22
* | Simplify translation tables headers dependenciesAntonio Nino Diaz2017-03-081-2/+2
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* Add PMF instrumentation points in TFdp-arm2016-10-121-0/+32
* Introduce PSCI Library InterfaceSoby Mathew2016-07-191-2/+60
* Remove dashes from image names: 'BL3-x' --> 'BL3x'Juan Castillo2015-12-141-1/+1
* Introduce COLD_BOOT_SINGLE_CPU build optionSandrine Bailleux2015-11-261-1/+1
* Make generic code work in presence of system cachesAchin Gupta2015-09-141-0/+17
* Introduce PROGRAMMABLE_RESET_ADDRESS build optionSandrine Bailleux2015-06-041-1/+7
* Rationalize reset handling codeSandrine Bailleux2015-06-041-128/+36
* Add support to indicate size and end of assembly functionsKévin Petit2015-04-081-0/+1
* Initialise cpu ops after enabling data cacheVikram Kanigiri2015-03-131-6/+0
* Call reset handlers upon BL3-1 entry.Yatharth Kochar2015-01-261-6/+12
* Remove coherent memory from the BL memory mapsSoby Mathew2015-01-221-0/+2
* Miscellaneous documentation fixesSandrine Bailleux2014-08-271-4/+0
* Add CPU specific power management operationsSoby Mathew2014-08-201-0/+6
* Introduce framework for CPU specific operationsSoby Mathew2014-08-201-1/+1
* Unmask SError interrupt and clear SCR_EL3.EA bitAchin Gupta2014-08-151-0/+8
* Call platform_is_primary_cpu() only from reset handlerJuan Castillo2014-08-011-10/+0
* Merge pull request #172 from soby-mathew/sm/asm_assertdanh-arm2014-07-281-12/+12
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| * Rework the crash reporting in BL3-1 to use less stackSoby Mathew2014-07-281-12/+12
* | Simplify management of SCTLR_EL3 and SCTLR_EL1Achin Gupta2014-07-281-5/+15
* | Remove coherent stack usage from the cold boot pathAchin Gupta2014-07-191-11/+6
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* Merge pull request #151 from vikramkanigiri/vk/t133-code-readabilityAndrew Thoelke2014-06-271-0/+4
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| * Simplify entry point information generation code on FVPVikram Kanigiri2014-06-241-0/+4
* | Remove early_exceptions from BL3-1Andrew Thoelke2014-06-171-3/+5
* | Per-cpu data cache restructuringAndrew Thoelke2014-06-161-0/+9
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* Introduce interrupt handling framework in BL3-1Achin Gupta2014-05-221-2/+0
* Add support for BL3-1 as a reset vectorVikram Kanigiri2014-05-221-9/+31
* Populate BL31 input parameters as per new specVikram Kanigiri2014-05-221-5/+5
* Rework handover interface between BL stagesVikram Kanigiri2014-05-221-13/+4
* Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu...danh-arm2014-05-081-1/+0
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| * Preserve x19-x29 across world switch for exception handlingSoby Mathew2014-05-081-1/+0
* | Access system registers directly in assemblerAndrew Thoelke2014-05-071-4/+3
* | Correct usage of data and instruction barriersAndrew Thoelke2014-05-071-1/+0
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* Reduce deep nesting of header filesDan Handley2014-05-061-2/+1
* Make use of user/system includes more consistentDan Handley2014-05-061-1/+1
* Place assembler functions in separate sectionsAndrew Thoelke2014-03-261-3/+2
* Add support for BL3-2 in BL3-1Achin Gupta2014-02-201-12/+0
* Rework BL2 to BL3-1 hand over interfaceAchin Gupta2014-02-201-5/+4
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