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* Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C filesMasahiro Yamada2020-03-311-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | The build system defines the IMAGE_BL* macro when compiling each image. This is useful to distinguish which image the current file is being built for by using #if defined(IMAGE_BL2) or #if defined(IMAGE_BL31), or whatever. There are some cases where we are more interested in which exception level the current file is being built for. include/lib/cpus/{aarch32,aarch64}/cpu_macros.S defines IMAGE_AT_EL3, but we do not have it globally. Pass IMAGE_AT_EL1 or IMAGE_AT_EL3 to BL*_CFLAGS so that it is available from all C code. The library code (libc.a, libmbedtls.a, etc.) is exceptional cases, where the code can be shared between BL images. Other than that, we know the exception level at the build time, and this macro will be useful in the shared code. Change-Id: I7c8a1da10726906adfba981cfe8464dff111d6b0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge "fconf: notify if fw_config dt is not used" into integrationOlivier Deprez2020-03-271-1/+1
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| * fconf: notify if fw_config dt is not usedManish Pandey2020-03-271-1/+1
|/ | | | | | | Notify if fw_config dt is either not available or not loaded from fip. Change-Id: I4dfcbe5032503d97f532a3287c5312c581578b68 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* Merge "FVP: Add BL2 hash calculation in BL1" into integrationMark Dykes2020-03-268-8/+187
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| * FVP: Add BL2 hash calculation in BL1Alexei Fedorov2020-03-258-8/+187
| | | | | | | | | | | | | | | | This patch provides support for measured boot by adding calculation of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB. Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge "Fix warnings in porting-guide.rst" into integrationOlivier Deprez2020-03-261-2/+2
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| * | Fix warnings in porting-guide.rstManish V Badarkhe2020-03-261-2/+2
| |/ | | | | | | | | | | | | | | Fix below warnings appeared in porting-guide.rst WARNING: Title underline too short. Change-Id: Ibc0eba0da72a53a5f9b61c49a8bf7a10b17bc3b8 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | Merge "Tegra194: se: increase max. operation timeout to 1 second" into ↵Sandrine Bailleux2020-03-261-5/+4
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| * | Tegra194: se: increase max. operation timeout to 1 secondVarun Wadekar2020-03-231-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases the maximum timeout value for SE operation completion to 1 second. This takes care of some corner cases where an operation might take more time than the previous timeout value of 100ms. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I0012448ba372a8bb0e156df7dfe49d7de6d21a68
* | | Merge changes I250c3aa1,Icf816053 into integrationSandrine Bailleux2020-03-261-0/+16
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: changelog: introduce SPMD, add secure partition loading and tooling changelog: add debugfs functionality
| * | changelog: introduce SPMD, add secure partition loading and toolingOlivier Deprez2020-03-261-0/+15
| | | | | | | | | | | | | | | Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I250c3aa199d4e5efa68aa32bf5a1694835be56b7
| * | changelog: add debugfs functionalityOlivier Deprez2020-03-261-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Icf8160536c249c754b3dfac6f8f49ca7ad3bb0de
* | | Merge "Fix 'tautological-constant-compare' error" into integrationMark Dykes2020-03-251-2/+2
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| * | | Fix 'tautological-constant-compare' errorManish V Badarkhe2020-03-251-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed below 'tautological-constant-compare' error when building the source code with latest clang compiler <clang version 11.0.0>. plat/common/plat_psci_common.c:36:2: error: converting the result of '<<' to a boolean always evaluates to true [-Werror,-Wtautological-constant-compare] PMF_STORE_ENABLE) ^ include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE' PMF_STORE_ENABLE (1 << 0) This error is observed beacuse of CASSERT placed in "PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff: CASSERT(_flags, select_proper_config); where _flags = PMF_STORE_ENABLE (1 << 0) which always results true. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
* | | Merge "spm: Add spci manifest binding document" into integrationManish Pandey2020-03-241-0/+239
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| * | | spm: Add spci manifest binding documentLouis Mayencourt2020-03-231-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The manifest binding document defines the expected properties and their formats to represent a partition manifest in device tree. Change-Id: I5eb250c7b89e0d828e1fcfce32b121e4081879ec Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | Merge "fconf: Clean Arm IO" into integrationMark Dykes2020-03-2412-401/+150
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| * | | | fconf: Clean Arm IOLouis Mayencourt2020-03-1612-401/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This removes the duplicate io_policies and functions definition. This patch: - replace arm_io_storage.c with the content of arm_fconf_io_storage.c - rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB. - use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb. - propagate DEFINES when parsing dts. - use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb. - set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior of fvp stays the same as it was before the introduction of fconf. Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | | Merge "plat/sgi: Bump bl1 RW limit" into integrationMark Dykes2020-03-241-1/+1
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| * | | | plat/sgi: Bump bl1 RW limitLouis Mayencourt2020-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase bl1 RW limit to allow future development. Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | | Merge "corstone700: updating the kernel arguments to support initramfs" into ↵Mark Dykes2020-03-241-2/+0
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| * | | | | corstone700: updating the kernel arguments to support initramfsAbdellatif El Khlifi2020-03-241-2/+0
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the context of enabling initramfs this change makes the kernel arguments compatible with the initramfs requirements Change-Id: Ifa955a5790ae1398fd8ad9ca1c8272f019c121a6 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
* | | | | Merge "context: TPIDR_EL2 register not saved/restored" into integrationManish Pandey2020-03-242-8/+16
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| * | | | | context: TPIDR_EL2 register not saved/restoredOlivier Deprez2020-03-202-8/+16
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPIDR_EL2 is missing from the EL2 state register save/restore sequence. This patch adds it to the context save restore routines. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I35fc5ee82f97b72bcedac57c791312e7b3a45251
* | | | | Merge "spmd: skip loading of secure partitions on pre-v8.4 platforms" into ↵Alexei Fedorov2020-03-244-7/+14
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| * | | | spmd: skip loading of secure partitions on pre-v8.4 platformsOlivier Deprez2020-03-234-7/+14
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1 then there is no need for TF-A to load secure partitions individually. In this configuration, SPMC handles secure partition loading at S-EL1/EL0 levels. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df
* | | | Merge changes from topic "static_analysis" into integrationManish Pandey2020-03-235-12/+17
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: io: io_stm32image: correct possible NULL pointer dereference plat/st: correctly check pwr-regulators node nand: stm32_fmc2_nand: correct xor_ecc.val assigned value plat/st: correct static analysis tool warning raw_nand: correct static analysis tool warning spi: stm32_qspi: correct static analysis issues
| * | | | io: io_stm32image: correct possible NULL pointer dereferenceYann Gautier2020-03-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This issue was found with cppcheck in our downstream code: [drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]: (warning) Either the condition 'buffer!=0U' is redundant or there is possible null pointer dereference: local_buffer. Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | plat/st: correctly check pwr-regulators nodeYann Gautier2020-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This warning was issued by cppcheck in our downstream code: [plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]: (warning) Identical condition 'node<0', second condition is always false The second test has to check variable pwr_regulators_node. Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | nand: stm32_fmc2_nand: correct xor_ecc.val assigned valueYann Gautier2020-03-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variable is wrongly set to 0L, whereas it is an unsigned int, it should then be 0U. Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | plat/st: correct static analysis tool warningYann Gautier2020-03-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the following sparse warnings: plat/st/common/stm32mp_dt.c:103:5: warning: symbol 'fdt_get_node_parent_address_cells' was not declared. Should it be static? plat/st/common/stm32mp_dt.c:123:5: warning: symbol 'fdt_get_node_parent_size_cells' was not declared. Should it be static? As those 2 functions are only used by assert(), put them under ENABLE_ASSERTIONS flag. Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | raw_nand: correct static analysis tool warningYann Gautier2020-03-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the following warning given by sparse tool: include/drivers/raw_nand.h:158:3: warning: symbol '__packed' was not declared. Should it be static? Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | spi: stm32_qspi: correct static analysis issuesYann Gautier2020-03-231-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse issue: drivers/st/spi/stm32_qspi.c:445:5: warning: symbol 'stm32_qspi_init' was not declared. Should it be static? Cppcheck issue: [drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]: (style) Variable 'len' is reassigned a value before the old one has been used. [drivers/st/spi/stm32_qspi.c:178]: (style) The scope of the variable 'timeout' can be reduced. Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | | | Merge "allwinner: H6: Fix GPIO and CCU memory map addresses" into integrationManish Pandey2020-03-231-2/+2
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| * | | | allwinner: H6: Fix GPIO and CCU memory map addressesAndre Przywara2020-03-231-2/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The base address for both the GPIO and the clock unit of the H6 memory map have been typo-ed. Fix them to match the Linux DT and the manual. The H6 code use neither of them, so this doesn't change or fix anything in the real world, but should be corrected anyway. The issue was found and reported by Github user "armlabs". Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge changes from topic "tegra-downstream-03192020" into integrationManish Pandey2020-03-2323-349/+107
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: Tegra194: move cluster and CPU counter to header file. Tegra: gicv2: initialize target masks spd: tlkd: support new TLK SMCs for RPMB service Tegra210: trigger CPU0 hotplug power on using FC Tegra: memctrl: cleanup streamid override registers Tegra: memctrl_v2: remove support to secure TZSRAM Tegra: include platform headers from individual makefiles Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro Tegra194: SiP function ID to read SMMU_PER registers Tegra: memctrl: map video memory as uncached Tegra: remove support for USE_COHERENT_MEM Tegra: remove circular dependency with common_def.h Tegra: include missing stdbool.h Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
| * | | | Tegra194: move cluster and CPU counter to header file.Anthony Zhou2020-03-213-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA rules request that the cluster and CPU counter be unsigned values and have a suffix 'U'. If the define located in the makefile, this cannot be done. This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER macros to tegra_def.h as a result. Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
| * | | | Tegra: gicv2: initialize target masksVarun Wadekar2020-03-211-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch initializes the target masks in the GICv2 driver data, for all PEs. This will allow platforms to set the PE target for SPIs. Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | spd: tlkd: support new TLK SMCs for RPMB serviceMustafa Yigit Bilgen2020-03-212-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to handle following TLK SMCs: {TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE} These SMCs need to be supported in ATF in order to forward them to TLK. Otherwise, these functionalities won't work. Brief: TLK_SET_BL_VERSION: This SMC is issued by the bootloader to supply its version to TLK. TLK can use this to prevent rollback attacks. TLK_LOCK_BL_INTERFACE: This SMC is issued by bootloader before handing off execution to the OS. This allows preventing sensitive SMCs being used by the OS. TLK_BL_RPMB_SERVICE: bootloader issues this SMC to sign or verify RPMB frames. Tested by: Tests TLK can receive the new SMCs issued by bootloader Change-Id: I57c2d189a5f7a77cea26c3f8921866f2a6f0f944 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
| * | | | Tegra210: trigger CPU0 hotplug power on using FCsumitg2020-03-211-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hotplug poweron is not working for boot CPU as it's being triggerred using PMC and not with Flow Controller. This is happening because "cpu_powergate_mask" is only getting set for non-boot CPU's as the boot CPU's first bootup follows different code path. The patch is marking a CPU as ON within "cpu_powergate_mask" when turning its power domain on during power on. This will ensure only first bootup on all CPU's is using PMC and subsequent hotplug poweron will be using Flow Controller. Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2 Signed-off-by: sumitg <sumitg@nvidia.com>
| * | | | Tegra: memctrl: cleanup streamid override registersPritesh Raithatha2020-03-212-210/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Streamid override registers are passed to memctrl to program bypass streamid for all the registers. There is no reason to bypass SMMU for any of the client so need to remove register list and do not set streamid_override_cfg. Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC bypass as of now. Will revisit once these issues are fixed. Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
| * | | | Tegra: memctrl_v2: remove support to secure TZSRAMVarun Wadekar2020-03-214-92/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes support to secure the on-chip TZSRAM memory for Tegra186 and Tegra194 platforms as the previous bootloader does that for them. Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra: include platform headers from individual makefilesVarun Wadekar2020-03-215-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies PLAT_INCLUDES to include individual Tegra SoC headers from the platform's makefile. Change-Id: If5248667f4e58ac18727d37a18fbba8e53f2d7b5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macroVarun Wadekar2020-03-212-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to 'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this is a Tegra feature. Change-Id: I5c4431e662223ee80efbfd5ec2513f8b1cadfc50 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: SiP function ID to read SMMU_PER registersVarun Wadekar2020-03-211-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER error records from all supported SMMU blocks. The register values are passed over to the client via CPU registers X1 - X3, where X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0] X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2] X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4] Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra: memctrl: map video memory as uncachedKen Chang2020-03-212-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memmap video memory as uncached normal memory by adding flag 'MT_NON_CACHEABLE' in mmap_add_dynamic_region(). This improves the time taken for clearing the non-overlapping video memory: test conditions: 32MB memory size, EMC running at 1866MHz, t186 1) without MT_NON_CACHEABLE: 30ms ~ 40ms <3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000 <3>[ 133.860471] _tegra_set_vpr_params[120]: begin <3>[ 133.896481] _tegra_set_vpr_params[123]: end <3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000 <3>[ 133.916397] _tegra_set_vpr_params[120]: begin <3>[ 133.956369] _tegra_set_vpr_params[123]: end <3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000 <3>[ 133.977934] _tegra_set_vpr_params[120]: begin <3>[ 134.013874] _tegra_set_vpr_params[123]: end <3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000 <3>[ 134.033512] _tegra_set_vpr_params[120]: begin <3>[ 134.065996] _tegra_set_vpr_params[123]: end <3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000 <3>[ 134.082923] _tegra_set_vpr_params[120]: begin <3>[ 134.113119] _tegra_set_vpr_params[123]: end <3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000 <3>[ 134.130790] _tegra_set_vpr_params[120]: begin <3>[ 134.162523] _tegra_set_vpr_params[123]: end <3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000 <3>[ 134.179772] _tegra_set_vpr_params[120]: begin <3>[ 134.209142] _tegra_set_vpr_params[123]: end 2) with MT_NON_CACHEABLE: 10ms ~ 18ms <3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000 <3>[ 102.116296] _tegra_set_vpr_params[120]: begin <3>[ 102.134272] _tegra_set_vpr_params[123]: end <3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000 <3>[ 102.153226] _tegra_set_vpr_params[120]: begin <3>[ 102.164201] _tegra_set_vpr_params[123]: end <3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000 <3>[ 102.179638] _tegra_set_vpr_params[120]: begin <3>[ 102.190342] _tegra_set_vpr_params[123]: end <3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000 <3>[ 102.205085] _tegra_set_vpr_params[120]: begin <3>[ 102.216112] _tegra_set_vpr_params[123]: end <3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000 <3>[ 102.231387] _tegra_set_vpr_params[120]: begin <3>[ 102.241775] _tegra_set_vpr_params[123]: end <3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000 <3>[ 102.256069] _tegra_set_vpr_params[120]: begin <3>[ 102.266368] _tegra_set_vpr_params[123]: end <3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000 <3>[ 102.280672] _tegra_set_vpr_params[120]: begin <3>[ 102.290929] _tegra_set_vpr_params[123]: end Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a Signed-off-by: Ken Chang <kenc@nvidia.com>
| * | | | Tegra: remove support for USE_COHERENT_MEMKalyani Chidambaram2020-03-211-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the support for 'USE_COHERENT_MEM' as Tegra platforms no longer support the feature. Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4ec Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
| * | | | Tegra: remove circular dependency with common_def.hVarun Wadekar2020-03-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch stops including common_def.h from platform_def.h to fix a circular depoendency between them. This means platform_def.h now has to define the linker macros: * PLATFORM_LINKER_FORMAT * PLATFORM_LINKER_ARCH Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra: include missing stdbool.hVarun Wadekar2020-03-212-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the missing stdbool.h header from flowctrl.h and bpmp_ivc.c files. Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra: remove support for SEPARATE_CODE_AND_RODATA=0Kalyani Chidambaram2020-03-212-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0. This patch uses the common macros provided by bl_common.h as a result and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set to '1'. Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 17:15:15 +0000