aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* sp_min: make sp_min_warm_entrypoint publicHeiko Stuebner2019-04-252-1/+1
| | | | | | | | | | Similar to bl31_warm_entrypoint, sp_min-based platforms may need that for special resume handling. Therefore move it from the private header to the sp_min platform header. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I40d9eb3ff77cff88d47c1ff51d53d9b2512cbd3e
* drivers: ti: uart: add a aarch32 variantHeiko Stuebner2019-04-251-0/+267
| | | | | | | | | | Rockchip re-uses the ti uart console driver and for aarch32 needs a specific variant, so add it. There are also aarch32 ti socs, so it may be useful for them as well at some point. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I31ede7cc7b10347b3691cff051db2b985fd59e17
* Merge changes from topic "av/console-register" into integrationAntonio Niño Díaz2019-04-242-7/+7
|\ | | | | | | | | | | * changes: Console: Remove Arm console unregister on suspend Console: Allow to register multiple times
| * Console: Remove Arm console unregister on suspendAmbroise Vincent2019-04-241-5/+3
| | | | | | | | | | Change-Id: Ie649b3c367a93db057eeaee7e83fa3e43f8c2607 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * Console: Allow to register multiple timesAmbroise Vincent2019-04-241-2/+4
| | | | | | | | | | | | | | It removes the need to unregister the console on system suspend. Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge changes from topic "k3-sequence-fix" into integrationAntonio Niño Díaz2019-04-242-42/+48
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID ti: k3: drivers: ti_sci: Cleanup sequence ID usage ti: k3: drivers: sec_proxy: Use direction definitions ti: k3: drivers: sec_proxy: Fix printf format specifiers
| * | ti: k3: drivers: ti_sci: Retry message receive on bad sequence IDAndrew F. Davis2019-04-231-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we get a sequence ID that does not match what we expect then the we are looking at is not the one we are expecting and so we error out. We can also assume this message is a stale message left in the queue, in this case we can read in the next message and check again for our message. Switch to doing that here. We only retry a set number of times so we don't lock the system if our message is actually lost and will never show up. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c
| * | ti: k3: drivers: ti_sci: Cleanup sequence ID usageAndrew F. Davis2019-04-231-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence ID can be set with a message to identify it when it is responded to in the response queue. We assign each message a number and check for this same number to detect response mismatches. Start this at 0 and increase it by one for each message sent, even ones that do not request or wait for a response as one may still be delivered in some cases and we want to detect this. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea
| * | ti: k3: drivers: sec_proxy: Use direction definitionsAndrew F. Davis2019-04-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | The direction of a thread should be explicitly compared to avoid confusion. Also fixup message wording based on this direction. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11
| * | ti: k3: drivers: sec_proxy: Fix printf format specifiersAndrew F. Davis2019-04-231-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ID of a thread is not used outside for printing it out when something goes wrong. The specifier used is also not consistent. Instead of storing the thread ID, store its name and print that. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b
* | | Merge changes from topic "k3-cleanups" into integrationAntonio Niño Díaz2019-04-244-24/+17
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | * changes: ti: k3: common: Align elements of map region table ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default ti: k3: common: Remove shared RAM space ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines
| * | ti: k3: common: Align elements of map region tableAndrew F. Davis2019-04-191-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is only a formatting change but makes it instantly clear how each region is set. This is over 80 chars and the MT_RO are not strictly needed but this section very important to get right so make readability the priority here. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I2432deda05d4502b3478170296b5da43f26ad8e6
| * | ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by defaultAndrew F. Davis2019-04-193-2/+4
| | | | | | | | | | | | | | | | | | | | | This should be more secure and looks a bit cleaner. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ie5eaf0234b211ba02631cf5eab5faa1402a34461
| * | ti: k3: common: Remove shared RAM spaceAndrew F. Davis2019-04-192-9/+3
| | | | | | | | | | | | | | | | | | | | | We don't use this for anything right now, remove it. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I11505d01834f7ff1fdba46fda0acbb3b56fc9b66
| * | ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other definesAndrew F. Davis2019-04-193-5/+5
| |/ | | | | | | | | | | | | This makes definitions more consistent, plus helps alignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I38fcdd76207586613d9934c9dc83d7a347e9e0fc
* | Merge "Cortex A9: Fix typo in errata 794073 workaround" into integrationAntonio Niño Díaz2019-04-231-1/+1
|\ \
| * | Cortex A9: Fix typo in errata 794073 workaroundLouis Mayencourt2019-04-181-1/+1
| |/ | | | | | | | | Change-Id: I22568caf83b9846cd7b59241fcec34a395825399 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Merge "Neoverse N1: Forces cacheable atomic to near" into integrationAntonio Niño Díaz2019-04-232-2/+19
|\ \
| * | Neoverse N1: Forces cacheable atomic to nearLouis Mayencourt2019-04-182-2/+19
| |/ | | | | | | | | | | | | | | This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Merge changes from topic "yg/optee" into integrationAntonio Niño Díaz2019-04-239-111/+377
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: stm32mp1: add OP-TEE support stm32mp1: fix TZC400 configuration against non-secure DDR stm32mp1: remove useless define stm32mp: split stm32mp_io_setup function
| * | stm32mp1: add OP-TEE supportYann Gautier2019-04-239-3/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support booting OP-TEE as BL32 boot stage and secure runtime service. OP-TEE executes in internal RAM and uses a secure DDR area to store the pager pagestore. Memory mapping and TZC are configured accordingly prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where a header file describes the effective boot images. This change post processes header file content to get OP-TEE load addresses and set OP-TEE boot arguments. Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
| * | stm32mp1: fix TZC400 configuration against non-secure DDRYann Gautier2019-04-231-21/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change disables secure accesses to non-secure DDR which are useless. TF-A already maps non-secure memory with non-secure permissions thanks to the MMU. This change also corrects some inline comments. Change-Id: Id4c20c9ee5c95a666dae6b7446ed80baf2d53fb0 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
| * | stm32mp1: remove useless defineYann Gautier2019-04-231-1/+0
| | | | | | | | | | | | | | | | | | | | | Remove STM32MP_DDR_SPEED_DFLT that is not used in STM32MP1 TF-A code. Change-Id: I780cdc4e93a8a9d997d50f67cfc582acd4a353d6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | stm32mp: split stm32mp_io_setup functionYann Gautier2019-04-231-86/+89
| |/ | | | | | | | | | | | | | | A new static function boot_mmc is created to simplify code maintenance of stm32mp_io_setup. Change-Id: I5c416e567e7e174fb1c2b435925a983c9c55fc40 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge changes from topic "aa-sbsa-watchdog" into integrationAntonio Niño Díaz2019-04-2318-10/+157
|\ \ | |/ |/| | | | | | | * changes: plat/arm: introduce wrapper functions to setup secure watchdog drivers/sbsa: add sbsa watchdog driver
| * plat/arm: introduce wrapper functions to setup secure watchdogAditya Angadi2019-04-1716-10/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BL1 stage setup code for ARM platforms sets up the SP805 watchdog controller as the secure watchdog. But not all ARM platforms use SP805 as the secure watchdog controller. So introduce two new ARM platform code specific wrapper functions to start and stop the secure watchdog. These functions then replace the calls to SP805 driver in common BL1 setup code. All the ARM platforms implement these wrapper functions by either calling into SP805 driver or the SBSA watchdog driver. Change-Id: I1a9a11b124cf3fac2a84f22ca40acd440a441257 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
| * drivers/sbsa: add sbsa watchdog driverAditya Angadi2019-04-172-0/+66
| | | | | | | | | | | | | | | | Add a driver for configuring the SBSA Generic Watchdog which aids in the detection of errant system behaviour. Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* | DSU: Implement workaround for errata 798953Louis Mayencourt2019-04-177-1/+85
| | | | | | | | | | | | | | | | | | Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | DSU: Small fix and reformat on errata frameworkLouis Mayencourt2019-04-172-28/+34
| | | | | | | | | | Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Cortex-A35: Implement workaround for errata 855472Louis Mayencourt2019-04-174-2/+69
|/ | | | | | | | | Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Temporarily disable shared Mbed TLS heap for SGMJohn Tsichritzis2019-04-161-5/+3
| | | | | | | | There is a bug in the shared heap implementation for SGM. Until the bug is solved, the default implementation is used. Change-Id: I010911a3f00ed860f742b14daad1d99b9e7ce711 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge "Cortex A9:errata 794073 workaround" into integrationAntonio Niño Díaz2019-04-124-2/+28
|\
| * Cortex A9:errata 794073 workaroundJoel Hutton2019-04-124-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
* | Merge changes from topic "av/tls-heap" into integrationAntonio Niño Díaz2019-04-1211-41/+83
|\ \ | | | | | | | | | | | | | | | * changes: Mbed TLS: Remove weak heap implementation sgm: Fix bl2 sources
| * | Mbed TLS: Remove weak heap implementationAmbroise Vincent2019-04-1210-36/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | sgm: Fix bl2 sourcesAmbroise Vincent2019-04-111-5/+6
| |/ | | | | | | | | | | | | The weak version of plat_get_mbedtls_heap() was being used. Change-Id: I6da331a098dd1af5bb64729d5b914cfb74b8869e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge changes from topic "pb/tbbr-oid" into integrationAntonio Niño Díaz2019-04-122-14/+4
|\ \ | | | | | | | | | | | | | | | * changes: doc: Clarify cert_create build when USE_TBBR_DEFS=0 plat/sgm: Remove redundant platform_oid.h
| * | doc: Clarify cert_create build when USE_TBBR_DEFS=0Paul Beesley2019-04-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The user guide documentation for the cert_create tool needs to mention that a platform must have a platform_oid.h header file in order to successfully build the cert_create tool when USE_TBBR_DEFS is 0. Change-Id: I77f86a022d207e88a79c97741be3eafbfa0c86f1 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
| * | plat/sgm: Remove redundant platform_oid.hPaul Beesley2019-04-111-12/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file is used when building the cert_create tool without using the 'standard' set of Arm OID values as defined in the TBBR specification (see tbbr_oid.h). This configuration is enabled by setting USE_TBBR_DEFS to 0 during build. At the moment this will fail because the header file included by this file was removed in commit bb41eb7a9dc3 ("cert: move platform_oid.h to include/tools_share for all platforms"). For the SGM platform this means that there is no current use for this file. Change-Id: I3c82983ada62330f1ab6be6d6c0cf489adabae7b Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Merge changes from topic "renesas-bsp203" into integrationAntonio Niño Díaz2019-04-1222-138/+210
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3 rcar_gen3: drivers: Change to restore timer counter value at resume rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2 rcar_gen3: drivers: ddr: Update DDR setting rev.0.35 rcar_gen3: drivers: qos: change subslot cycle rcar_gen3: drivers: board: Add new board revision for H3ULCB rcar_gen3: plat: Change periodic write DQ training option.
| * | rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3Toshiyuki Ogasahara2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759
| * | rcar_gen3: drivers: Change to restore timer counter value at resumeToshiyuki Ogasahara2019-04-116-66/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
| * | rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh modeYoshifumi Hosoya2019-04-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Very rarely, LPDDR4 power consumption may not decrease In self-refresh mode. This patch fixes the DBSC4 self-refresh mode sequence. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com> Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
| * | rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2Toshiyuki Ogasahara2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
| * | rcar_gen3: drivers: ddr: Update DDR setting rev.0.35Chiaki Fujii2019-04-116-48/+129
| | | | | | | | | | | | | | | | | | | | | | | | [IPL/DDR] - Update DDR setting rev.0.35. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
| * | rcar_gen3: drivers: qos: change subslot cycleYoshifumi Hosoya2019-04-117-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Subslot cycle from 132 to 126 as default setting. Subslot cycle from 264 to 252. [IPL/QoS] - Update H3 Ver.2.0 QoS setting rev.0.21. - Update H3 Ver.3.0 QoS setting rev.0.11. - Update M3 Ver.1.1 QoS setting rev.0.19. - Update M3 Ver.3.0 QoS setting rev.0.02. - Update M3N Ver.1.1 QoS setting rev.0.09. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
| * | rcar_gen3: drivers: board: Add new board revision for H3ULCBYusuke Goda2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board Revision[2:0] 3'b000 Rev1.0 OB 3'b001 Rev1.0 CE 3'b010 Rev2.0 [New] Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
| * | rcar_gen3: plat: Change periodic write DQ training option.Toshiyuki Ogasahara2019-04-111-1/+1
| |/ | | | | | | | | | | | | | | Periodic write DQ training available as default. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
* | Merge "Improvements in Readme" into integrationAntonio Niño Díaz2019-04-121-7/+12
|\ \
| * | Improvements in ReadmeJohn Tsichritzis2019-04-121-7/+12
| |/ | | | | | | | | | | | | | | | | | | - Fix broken link to the issue tracker. - Add contents section to make navigation easier throughout the page. - Move the link to documentation contents near the top. Where it was before could be missed and documentation might seem inaccessible. Change-Id: I502e4fc0fd312459cda351d30a8781c221625724 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 08:07:47 +0000