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* Standardise header guards across codebaseAntonio Nino Diaz2018-11-08508-1558/+1611
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1672 from sandrine-bailleux-arm/sb/fix-dram-constantsSoby Mathew2018-11-071-2/+2
|\ | | | | Arm platforms: Fix DRAM address macros
| * Arm platforms: Fix DRAM address macrosSandrine Bailleux2018-11-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently 32-bit values (because they are suffixed with UL and the value 0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When summing them up, the result overflows the maximum value that can be encoded in a 32-bit value so it wraps around and does not result in the expected value. This patch changes the suffix of these constants into ULL so that they always are 64-bit values. Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Merge pull request #1668 from ldts/rcar_gen3/e3_buildSoby Mathew2018-11-075-7/+18
|\ \ | | | | | | rcar_gen3: E3 target: fix compilation issues
| * | rcar_gen3: E3 target: fix compilation issuesldts2018-11-064-7/+8
| | | | | | | | | | | | | | | | | | Target builds but has not been tested. Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
| * | plat: rcar: support plat_crash_console_flushldts2018-11-061-0/+10
| | | | | | | | | | | | Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
* | | Merge pull request #1670 from antonio-nino-diaz-arm/an/misra-armSoby Mathew2018-11-075-28/+25
|\ \ \ | | | | | | | | plat/arm: Fix MISRA defects in common code
| * | | plat/arm: Fix MISRA defects in common codeAntonio Nino Diaz2018-11-065-28/+25
| | |/ | |/| | | | | | | | | | Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1669 from sandrine-bailleux-arm/sb/rm-tzc-top-fnSoby Mathew2018-11-076-45/+57
|\ \ \ | | | | | | | | Remove unneeded _tzc_get_max_top_addr() function
| * | | Remove _tzc_get_max_top_addr() functionSandrine Bailleux2018-11-063-38/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function was needed at the time where we didn't have the compiler_rt lib. An AArch32-specific variant was provided to handle the 64-bit shift operation in 32-bit. This is no longer needed. Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
| * | | compiler_rt: Import lshrdi3.c fileSandrine Bailleux2018-11-062-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __aeabi_llsr() builtin, which is required by a subsequent patch that uses a logical right shift operator in AArch32. Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
| * | | compiler_rt: Import latest changes on int_lib.hSandrine Bailleux2018-11-061-6/+7
| |/ / | | | | | | | | | | | | | | | | | | | | | Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | Merge pull request #1666 from pmanish87/mp2/manish_localSoby Mathew2018-11-074-10/+29
|\ \ \ | |/ / |/| | plat/arm: Support direct Linux kernel boot in AArch32
| * | plat/arm: Support direct Linux kernel boot in AArch32Manish Pandey2018-11-054-10/+29
| |/ | | | | | | | | | | | | | | | | | | | | | | This option allows the Trusted Firmware to directly jump to Linux kernel for aarch32 without the need of an intermediate loader such as U-Boot. Similar to AArch64 ARM_LINUX_KERNEL_AS_BL33 only available with RESET_TO_SP_MIN=1 as well as BL33 and DTB are preloaded in memory. Change-Id: I908bc1633696be1caad0ce2f099c34215c8e0633 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | Merge pull request #1665 from antonio-nino-diaz-arm/an/fdt-helpersAntonio Niño Díaz2018-11-065-1/+131
|\ \ | | | | | | Introduce new fdt helpers
| * | Introduce fdtw_read_array() helperAntonio Nino Diaz2018-11-022-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | fdtw_read_cells() can only read one or two cells, sometimes it may be needed to read more cells from one property. Change-Id: Ie70dc76d1540cd6a04787cde7cccb4d1bafc7282 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | Introduce new fdt helper to read string propertiesAntonio Nino Diaz2018-11-022-0/+36
| | | | | | | | | | | | | | | | | | | | | Introduced fdtw_read_string() to read string properties. Change-Id: I854eef0390632cf2eaddd2dce60cdb98c117de43 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | libc: Adapt strlcpy to this codebaseAntonio Nino Diaz2018-11-023-5/+6
| | | | | | | | | | | | | | | Change-Id: I2f5f64aaf90caae936510e1179392a8835f493e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | libc: Import strlcpy from FreeBSDAntonio Nino Diaz2018-11-021-0/+53
| |/ | | | | | | | | | | | | | | | | From commit aafd1cf4235d78ce85b76d7da63e9589039344b3: - lib/libc/strlcpy.c Change-Id: Iaa7028fcc26706bdd6ee3f1e4bd55dd5873a30c6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1661 from hzhuang1/emmc_delaySoby Mathew2018-11-061-0/+2
|\ \ | |/ |/| hikey: add delay after eMMC initialized
| * hikey: add delay after eMMC initializedHaojian Zhuang2018-10-311-0/+2
| | | | | | | | | | | | | | It boots failure on CircuitCo HiKey board. The delay could fix the hang issue. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | Merge pull request #1663 from sudeep-holla/scpi_build_fixAntonio Niño Díaz2018-11-021-0/+2
|\ \ | | | | | | plat: juno: fix build for !CSS_USE_SCMI_DRIVER
| * | plat: juno: fix build for !CSS_USE_SCMI_DRIVERSudeep Holla2018-11-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CSS_USE_SCMI_DRIVER is not defined or set to 0, we get the following build error. plat/arm/board/juno/juno_topology.c:16:19: error: ‘CSS_SCMI_PAYLOAD_BASE’ undeclared here (not in a function) .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, ^~~~~~~~~~~~~~~~~~~~~ plat/arm/board/juno/juno_topology.c:17:38: error: ‘CSS_SCMI_MHU_DB_REG_OFF’ undeclared here (not in a function) .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, ^~~~~~~~~~~~~~~~~~~~~~~ CSS_CPU_PWR_STATE_OFF Fix the error in order to get function legacy SCPI support functional. Change-Id: I00cb80db9968aa0be546e33a3a682a2db87719be Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | | Merge pull request #1660 from antonio-nino-diaz-arm/an/misraAntonio Niño Díaz2018-11-0231-322/+362
|\ \ \ | |/ / |/| | Several MISRA defect fixes
| * | bakery: Fix MISRA defectsAntonio Nino Diaz2018-11-014-53/+82
| | | | | | | | | | | | | | | Change-Id: I600bc13522ae977db355b6dc5a1695bce39ec130 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | plat/arm: Fix MISRA defects in dyn configAntonio Nino Diaz2018-11-012-11/+10
| | | | | | | | | | | | | | | Change-Id: Iae6758ca6395560131d1e1a69a1ecfe50ca8bf83 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | plat/arm: Fix types of constants in headersAntonio Nino Diaz2018-11-017-173/+173
| | | | | | | | | | | | | | | Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | context_mgmt: Fix MISRA defectsAntonio Nino Diaz2018-11-0118-85/+97
|/ / | | | | | | | | | | | | | | The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1658 from glneo/plat-arm-removeAntonio Niño Díaz2018-11-012-8/+4
|\ \ | | | | | | ti: k3: common: Remove use of ARM platform code
| * | ti: k3: common: Remove use of ARM platform codeAndrew F. Davis2018-10-302-8/+4
| |/ | | | | | | | | | | | | | | | | | | A recent patch[0] has made setting up page tables into generic code, complete the conversion for TI platforms by removing the use of plat_arm_get_mmap() and using the mmap table directly. [0] 0916c38deca4 ("Convert arm_setup_page_tables into a generic helper") Signed-off-by: Andrew F. Davis <afd@ti.com>
* | Merge pull request #1657 from antonio-nino-diaz-arm/an/libfdtAntonio Niño Díaz2018-11-019-441/+99
|\ \ | | | | | | libfdt: Downgrade to version 1.4.6-9
| * | libfdt: Downgrade to version 1.4.6-9Antonio Nino Diaz2018-10-309-441/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Version 1.4.7 introduces a big performance hit to functions that access the FDT. Downgrade the library to version 1.4.6-9, before the changes that introduce the problem. Version 1.4.6 isn't used because one of the libfdt files (fdt_overlay.c) is missing the license header. This problem is also fixed in 1.4.6-9. This version corresponds to commit <aadd0b65c987> checks: centralize printing of property names in failure messages. Fixes ARM-software/tf-issues#643 Change-Id: I73c05f2b1f994bcdcc4366131ce0647553cdcfb8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1656 from masahir0y/uniphierAntonio Niño Díaz2018-11-014-29/+6
|\ \ \ | | | | | | | | uniphier: clean-up and improve SCP handling code
| * | | uniphier: revise SCP protocol handshakeDai Okamura2018-10-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the SoC issues a command IRQ to SCP, SCP sets STMTOBEIRQ as ACK. The SoC must wait for it before issuing the next command. This commit makes sure to meet the requirement. Signed-off-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | uniphier: terminate boot if SCP_BL2 image is missing in SCP boot modeMasahiro Yamada2018-10-303-29/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Skipping SCP_BL2 image is just a temporary workaround. If on-chip SCP needs to work, BL2 should load the SCP_BL2 image. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge pull request #1623 from MISL-EBU-System-SW/a3700-supportAntonio Niño Díaz2018-11-0158-296/+5399
|\ \ \ \ | | | | | | | | | | Add support for Armada 3700 and COMPHY porting layer
| * | | | plat: marvell: Add support for Armada-37xx SoC platformKonstantin Porotchkin2018-10-3127-4/+2917
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | | drivers: marvell Add support for Armada-37xx UARTKonstantin Porotchkin2018-10-222-0/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce driver for Marvell Armada-37xx UART console Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | | drivers: marvell Add Armada-37xx COMPHY driverKonstantin Porotchkin2018-10-222-0/+1233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Marvell Armada-3700 COMPHY driver Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | | tools: Move doimage to marvell folder for future add-onsKonstantin Porotchkin2018-10-2213-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move doimage utility from toos/doimage to tools/marvell/doimage. This is done for supporting mode Marvell tools in the future. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | | mvebu: cp110: introduce COMPHY porting layerGrzegorz Jaszczyk2018-10-1813-287/+1014
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | | plat: marvell: Fix the wrong include protectorKonstantin Porotchkin2018-10-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the include protector to be in sync with file name Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | | lib/mmio: Add mmio_clrsetbits_16 inline functionKonstantin Porotchkin2018-10-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 16-bit variant of mmio_clrsetbits function Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | | | | Merge pull request #1650 from chandnich/sgiclark-ares-supportAntonio Niño Díaz2018-10-319-4/+200
|\ \ \ \ \ | | | | | | | | | | | | Sgiclark ares support
| * | | | | plat/arm/sgi: add support for SGI-Clark.Ares platformChandni Cherukuri2018-10-264-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SGI-Clark.Ares platform is a variant of the SGI-Clark platform. It has two clusters of four Ares CPUs each. Though very similar to the SGI575 platform, there are subtle differences. HW_CONFIG and TB_FW_CONFIG dts files have been added. Change-Id: I740a33cbd1c3b1f1984cb56243b46ad379bab3e6 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | | plat/arm/sgi: add support for SGI-Clark platformChandni Cherukuri2018-10-263-4/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SGI-Clark platform is the next version in the Arm's SGI platform series. One of the primary difference between the SGI-575 platform and the SGI-Clark platform is the MHU version (MHUv2 in case of SGI-Clark). Add the required base support for SGI-Clark platform. Change-Id: If396e5279fdf801d586662dad0b55195e81371e4 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | | plat/arm/css: Add SID registers for SGx platformsChandni Cherukuri2018-10-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the SGx platforms use System Identification (SID) registers for platform identification. Add support for these registers in css. Change-Id: If00b18744a31ff2cf14338f18c8c680eb69c9027 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | | plat/arm/sgi: disable Ares cpu power down bit in reset handlerChandni Cherukuri2018-10-261-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SGI platforms that include Ares CPUs, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it to enable hotplug and idle to function correctly. The reset value of the CORE_PWRDN_EN bit is zero but it still requires this explicit clear to zero. This indicates that this could be a model related issue but for now this issue can be fixed be clearing the CORE_PWRDN_EN bit in the platform specific reset handler function. Change-Id: I8b9884ae27a2986d789bfec2e9ae792ef930944e Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | | | Merge pull request #1655 from deepan02/deepak-arm/introduce-n1sdpAntonio Niño Díaz2018-10-319-0/+382
|\ \ \ \ \ \ | | | | | | | | | | | | | | plat/arm: Introduce the N1SDP.
| * | | | | | plat/arm: Introduce the N1SDP.Deepak Pandey2018-10-299-0/+382
| | |_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the N1SDP (NeoVerse N1 System Development Platform). It is an initial port and additional features are expected to be added later. The port includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary boatloader Change-Id: Ife17d8215a7bfcc1420204a72205e7ef920d0c10 Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
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