aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Remove references to old project name from common filesJohn Tsichritzis2019-07-109-21/+24
| | | | | | | | | | | | | The project has been renamed from "Arm Trusted Firmware (ATF)" to "Trusted Firmware-A (TF-A)" long ago. A few references to the old project name that still remained in various places have now been removed. This change doesn't affect any platform files. Any "ATF" references inside platform files, still remain. Change-Id: Id97895faa5b1845e851d4d50f5750de7a55bf99e Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge "plat: imx8m: Add caam module init on imx8m" into integrationSandrine Bailleux2019-07-098-11/+86
|\
| * plat: imx8m: Add caam module init on imx8mJacky Bai2019-07-048-11/+86
| | | | | | | | | | | | | | | | CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
* | Merge changes from topic "jts/reword" into integrationSandrine Bailleux2019-07-095-27/+23
|\ \ | | | | | | | | | | | | | | | * changes: docs: removing references to GitHub Change checkpatch.conf after migration to tf.org
| * | docs: removing references to GitHubJohn Tsichritzis2019-07-084-23/+23
| | | | | | | | | | | | | | | Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | Change checkpatch.conf after migration to tf.orgJohn Tsichritzis2019-07-081-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | A specific checkpatch setting was used because of GitHub. This necessity doesn't exist anymore. Change-Id: Ie2225a5cb88654f3b7407e43e0a48fafa9a9165c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | Merge "rpi3: Fix compilation error when stack protector is enabled" into ↵Sandrine Bailleux2019-07-081-1/+2
|\ \ \ | |/ / |/| | | | | integration
| * | rpi3: Fix compilation error when stack protector is enabledMadhukar Pappireddy2019-07-081-1/+2
|/ / | | | | | | | | | | | | Include necessary header file to use ARRAY_SIZE() macro Change-Id: I5b7caccd02c14c598b7944cf4f347606c1e7a8e7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "tools/fiptool: Add Makefile.msvc to build on Windows." into integrationSandrine Bailleux2019-07-051-0/+30
|\ \
| * | tools/fiptool: Add Makefile.msvc to build on Windows.Girish Pathak2019-07-021-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | This change adds nmake compatible Makefile.msvc file for building (nmake /FMakefile.msvc) fiptool on the Windows. Change-Id: Iccd1fe8da072edd09eb04b8622f27b3c4693b281 Signed-off-by: Girish Pathak <girish.pathak@arm.com>
* | | Merge "uniphier: support console based on multi-console" into integrationSandrine Bailleux2019-07-055-179/+144
|\ \ \
| * | | uniphier: support console based on multi-consoleMasahiro Yamada2019-07-055-179/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The legacy console is gone. Re-add the console support based on the multi-console framework. I am still keeping the putc, getc, and flush callbacks in uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S The console registration code already relies on that C environment has been set up. So, I just filled the struct console fields with the callback pointers, then called console_register() directly. I also re-implemented the init function in C to improve the readability. Removing the custom crash console implementation has one disadvantage; we cannot use the crash console on very early crashes because crash_console_helpers.S works only after the console is registered. I can live with this limitation. Tested on my boards, and confirmed this worked like before. Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge "ti: k3: common: Trap all asynchronous bus errors to EL3" into integrationSandrine Bailleux2019-07-051-0/+3
|\ \ \ \ | |/ / / |/| | |
| * | | ti: k3: common: Trap all asynchronous bus errors to EL3Andrew F. Davis2019-07-041-0/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | These errors are asynchronous and cannot be directly correlated with the exact current running software, so handling them in the same EL is not critical. Handling them in TF-A allows for more platform specific decoding of the implementation defined exception registers Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda
* | | Merge changes from topic "lw/n1_errata_fixes" into integrationSandrine Bailleux2019-07-044-6/+407
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: Removing redundant ISB instructions Workaround for Neoverse N1 erratum 1275112 Workaround for Neoverse N1 erratum 1262888 Workaround for Neoverse N1 erratum 1262606 Workaround for Neoverse N1 erratum 1257314 Workaround for Neoverse N1 erratum 1220197 Workaround for Neoverse N1 erratum 1207823 Workaround for Neoverse N1 erratum 1165347 Workaround for Neoverse N1 erratum 1130799 Workaround for Neoverse N1 erratum 1073348
| * | Removing redundant ISB instructionslauwal012019-07-021-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1275112lauwal012019-07-023-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1262888lauwal012019-07-024-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1262606lauwal012019-07-024-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1257314lauwal012019-07-024-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1220197lauwal012019-07-024-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1207823lauwal012019-07-024-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1165347lauwal012019-07-024-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1130799lauwal012019-07-024-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
| * | Workaround for Neoverse N1 erratum 1073348lauwal012019-07-024-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* | | Merge "zynqmp: add support for multi console interface" into integrationSandrine Bailleux2019-07-025-15/+25
|\ \ \
| * | | zynqmp: add support for multi console interfaceAmbroise Vincent2019-07-015-15/+25
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This patch addds multi console interface for ZynqMP platform Change-Id: I508a61412df2b71d04bca6a1139c8f32cbd7dccd Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* | | Merge changes from topic "banned_api_list" into integrationSoby Mathew2019-07-012-2/+37
|\ \ \ | |/ / |/| | | | | | | | | | | * changes: Fix the License header template in imx_aipstz.c docs: Add the list of banned/use with caution APIs
| * | Fix the License header template in imx_aipstz.cSoby Mathew2019-07-011-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af
| * | docs: Add the list of banned/use with caution APIsSoby Mathew2019-07-011-0/+35
| |/ | | | | | | | | | | | | Credit to sam.ellis@arm.com for the input to create the list. Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge changes from topic "av/console-port" into integrationPaul Beesley2019-06-2850-527/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: qemu: use new console interface in aarch32 warp7: remove old console from makefile Remove MULTI_CONSOLE_API flag and references to it Console: removed legacy console API
| * | qemu: use new console interface in aarch32Ambroise Vincent2019-06-282-6/+5
| | | | | | | | | | | | | | | Change-Id: Iab788e3e7cb2f83144255c4eb830712fd5cb6240 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | warp7: remove old console from makefileAmbroise Vincent2019-06-281-2/+1
| | | | | | | | | | | | | | | Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Remove MULTI_CONSOLE_API flag and references to itAmbroise Vincent2019-06-2844-252/+0
| | | | | | | | | | | | | | | | | | | | | The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Console: removed legacy console APIAmbroise Vincent2019-06-267-268/+3
| | | | | | | | | | | | | | | | | | | | | This interface has been deprecated in favour of MULTI_CONSOLE_API. Change-Id: I6170c1c8c74a890e5bd6d05396743fe62024a08a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | | Merge "Tegra: Fix typo in comment" into integrationPaul Beesley2019-06-271-1/+1
|\ \ \
| * | | Tegra: Fix typo in commentAndreas Färber2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | initilise -> initialise Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: Ib129e6bd48623b6565b669bc674208893a2f7668
* | | | Merge "Tegra: Extend NS address check error output" into integrationPaul Beesley2019-06-271-2/+2
|\| | |
| * | | Tegra: Extend NS address check error outputAndreas Färber2019-06-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Let bl31_check_ns_address() print the address it doesn't like. Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: I29a4fb33c24e9f7464ccd2ea44a4608f5cfe5be6
* | | | Merge "n1sdp: add code for DDR ECC enablement and BL33 copy to DDR" into ↵Paul Beesley2019-06-2713-19/+266
|\ \ \ \ | | | | | | | | | | | | | | | integration
| * | | | n1sdp: add code for DDR ECC enablement and BL33 copy to DDRManoj Kumar2019-06-2613-19/+266
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* | | | Merge changes from topic "pull-out-drivers" into integrationPaul Beesley2019-06-269-29/+265
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: intel: Add ncore ccu driver intel: Fix watchdog driver structure intel: Fix qspi driver write config intel: Pull out common drivers into platform common
| * | | | intel: Add ncore ccu driverHadi Asyrafi2019-06-262-0/+234
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
| * | | | intel: Fix watchdog driver structureHadi Asyrafi2019-06-262-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01
| * | | | intel: Fix qspi driver write configHadi Asyrafi2019-06-262-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a
| * | | | intel: Pull out common drivers into platform commonHadi Asyrafi2019-06-267-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa
* | | | | Merge "rcar_gen3: drivers: pfc: E3: Replace REVERCED with REVERSED" into ↵Paul Beesley2019-06-261-4/+4
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | integration
| * | | | | rcar_gen3: drivers: pfc: E3: Replace REVERCED with REVERSEDMarek Vasut2019-06-251-4/+4
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id6abb4c192729f55b3500505860c7f7718944c62
* | | | | Merge changes Ie594b535,Ifa444dd5,Ie93e7fcc,I302cff20,I0f6c1cad, ... into ↵Paul Beesley2019-06-2526-8738/+7480
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: rcar_gen3: drivers: pfc: Move PFC drivers out of staging rcar_gen3: drivers: pfc: Checkpatch cleanup rcar_gen3: drivers: pfc: V3M: Fix camel case rcar_gen3: drivers: pfc: V3M: Drop forward declarations rcar_gen3: drivers: pfc: V3M: Switch to BIT() macro rcar_gen3: drivers: pfc: V3M: Checkpatch cleanup rcar_gen3: drivers: pfc: V3M: Switch to common register header file rcar_gen3: drivers: pfc: E3: Drop pfc_reg_write() forward declaration rcar_gen3: drivers: pfc: E3: Switch to BIT() macro rcar_gen3: drivers: pfc: E3: Checkpatch cleanup rcar_gen3: drivers: pfc: E3: Switch to common register header file rcar_gen3: drivers: pfc: D3: Switch to BIT() macro rcar_gen3: drivers: pfc: D3: Drop unused macros rcar_gen3: drivers: pfc: D3: Checkpatch cleanup rcar_gen3: drivers: pfc: D3: Switch to common register header file rcar_gen3: drivers: pfc: M3N: Drop forward declarations rcar_gen3: drivers: pfc: M3N: Switch to BIT() macro rcar_gen3: drivers: pfc: M3N: Checkpatch cleanup rcar_gen3: drivers: pfc: M3N: Switch to common register header file rcar_gen3: drivers: pfc: M3W: Fix camel case rcar_gen3: drivers: pfc: M3W: Drop forward declarations rcar_gen3: drivers: pfc: M3W: Switch to BIT() macro rcar_gen3: drivers: pfc: M3W: Checkpatch cleanup rcar_gen3: drivers: pfc: M3W: Switch to common register header file rcar_gen3: drivers: pfc: H3: Drop pfc_reg_write() forward declaration rcar_gen3: drivers: pfc: H3: Switch to BIT() macro rcar_gen3: drivers: pfc: H3: Drop unused macros rcar_gen3: drivers: pfc: H3: Checkpatch cleanup rcar_gen3: drivers: pfc: H3: Switch to common register header file rcar_gen3: drivers: pfc: Introduce common register header file rcar_gen3: drivers: pfc: D3: Drop unused M3W check
| * | | | | rcar_gen3: drivers: pfc: Move PFC drivers out of stagingMarek Vasut2019-06-2219-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that PFC drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie594b53558c2bfb8e5d88e5b0354752c17a2487e
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 08:19:44 +0000