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* TSP: Enable cache along with MMUJeenu Viswambharan2018-06-271-31/+3
| | | | | | | | | Previously, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. Change-Id: I73f3b8bae5178610e17e9ad06f81f8f6f97734a6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* DynamIQ: Enable MMU without using stackJeenu Viswambharan2018-06-277-26/+57
| | | | | | | | | | | | | | | | | | | Having an active stack while enabling MMU has shown coherency problems. This patch builds on top of translation library changes that introduces MMU-enabling without using stacks. Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. NOTE: Since this feature depends on using translation table library v2, disallow using translation table library v1 with HW_ASSISTED_COHERENCY. Fixes ARM-software/tf-issues#566 Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* xlat v1: Provide direct MMU-enabling stubsJeenu Viswambharan2018-06-272-1/+11
| | | | | | | | | | An earlier patch split MMU-enabling function for translation library v2. Although we don't intend to introduce the exact same functionality for xlat v1, this patch introduces stubs for directly enabling MMU to maintain API-compatibility. Change-Id: Id7d56e124c80af71de999fcda10f1734b50bca97 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* xlat v2: Split MMU setup and enableJeenu Viswambharan2018-06-2714-121/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, the function provided by the translation library to enable MMU constructs appropriate values for translation library, and programs them to the right registers. The construction of initial values, however, is only required once as both the primary and secondaries program the same values. Additionally, the MMU-enabling function is written in C, which means there's an active stack at the time of enabling MMU. On some systems, like Arm DynamIQ, having active stack while enabling MMU during warm boot might lead to coherency problems. This patch addresses both the above problems by: - Splitting the MMU-enabling function into two: one that sets up values to be programmed into the registers, and another one that takes the pre-computed values and writes to the appropriate registers. With this, the primary effectively calls both functions to have the MMU enabled, but secondaries only need to call the latter. - Rewriting the function that enables MMU in assembly so that it doesn't use stack. This patch fixes a bunch of MISRA issues on the way. Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Merge pull request #1445 from danielboulby-arm/db/DynamicAuthenticationDimitris Papastamos2018-06-251-1/+1
|\ | | | | Set FVP DYN_DISABLE_AUTH authentication default to 0
| * Set FVP DYN_DISABLE_AUTH authentication default to 0Daniel Boulby2018-06-251-1/+1
| | | | | | | | | | | | | | | | Set the ability to dynamically disable Trusted Boot Board authentication to be off by default Change-Id: Ibd2aa179179f7d9b0e7731c6e450f200a8c67529 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge pull request #1448 from npoushin/npoushin/sgi575-coverity-fixesDimitris Papastamos2018-06-254-9/+27
|\ \ | |/ |/| npoushin/sgi575 coverity fixes
| * plat/arm: css: Sanitize the input to css_validate_power_stateNariman Poushin2018-06-231-1/+13
| | | | | | | | | | | | | | | | | | | | In the case of the platform max power level being less than the system power level, make sure to not overrun the array of power states. This fixes Coverity Scan OVERRUN defect CID 267021. Change-Id: I52646ab9be2fceeb5c331b5dad7a6267991f4197 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
| * plat/arm: css: Convert CSS_SYSTEM_PWR_STATE from macro to inline functionNariman Poushin2018-06-234-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | This is to fix a number of Coverity Scan DEADCODE defects, CID numbers listed below, as reported from https://scan.coverity.com/projects/arm-software-arm-trusted-firmware CID 267023 CID 267022 CID 267020 Change-Id: I2963a799b210149e84ccab5c5b9082267ddfe337 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
* | Merge pull request #1446 from masahir0y/uniphierDimitris Papastamos2018-06-251-1/+1
|\ \ | | | | | | maintainers.rst: separate maintainership of uniphier and synquacer
| * | maintainers.rst: separate maintainership of uniphier and synquacerMasahiro Yamada2018-06-231-1/+1
| |/ | | | | | | | | | | | | Socionext has multiple product lines. The UniPhier is not the only platform any more. Correct the maintainership. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge pull request #1441 from robertovargas-arm/mem_protect_boardDimitris Papastamos2018-06-224-8/+34
|\ \ | | | | | | Move mem-protect definitions to board specific files
| * | Move mem-protect definitions to board specific filesRoberto Vargas2018-06-184-8/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having these definitions in board_arm_def.h forces to all the arm platforms to use the same definition for PLAT_ARM_MEM_PROT_ADDR. This macro also enables the mem-protect mechanism, which means that all the arm platform has enabled mem-protect and they cannot get rid of it. Change-Id: Id29d2c51cbe6edc15f010a9f5a20c42266c48a08 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1444 from jts-arm/docsDimitris Papastamos2018-06-222-12/+16
|\ \ \ | | | | | | | | Fix typos in documentation
| * | | Fix typos in documentationJohn Tsichritzis2018-06-222-12/+16
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the porting guide, there are blue boxes that describe the argument types and the return type of each function. A small typo caused some of these boxes not being properly rendered. In the user guide, small typos were fixed that caused random text being unintentionally rendered as bold. Also, a slight rewording was done in the section describing the DYN_DISABLE_AUTH flag. Change-Id: I57303ca609436a82162fa9b42c06b0d5a63da6df Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | Merge pull request #1406 from robertovargas-arm/uuidDimitris Papastamos2018-06-2216-80/+107
|\ \ \ | |/ / |/| | Make TF UUID RFC 4122 compliant
| * | Make TF UUID RFC 4122 compliantRoberto Vargas2018-06-1416-80/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC4122 defines that fields are stored in network order (big endian), but TF-A stores them in machine order (little endian by default in TF-A). We cannot change the future UUIDs that are already generated, but we can store all the bytes using arrays and modify fiptool to generate the UUIDs with the correct byte order. Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1443 from jeenu-arm/sdei-fixesDimitris Papastamos2018-06-222-3/+3
|\ \ \ | | | | | | | | SDEI client EL determination fix
| * | | SDEI: Fix name of internal functionJeenu Viswambharan2018-06-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function end_sdei_explicit_dispatch() was intended to be end_sdei_synchronous_dispatch() which does the opposite of begin_sdei_synchronous_dispatch(). This patch fixes that. No functional changes. Change-Id: I141bd91eb342ecf4ddfd05b49513eee4549e7a56 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | SDEI: Fix determining client ELJeenu Viswambharan2018-06-221-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | commit 2ccfcb2ea555eb86122e7780010cc50fcee08f54 ("SDEI: Determine client EL from NS context's SCR_EL3") intended to read from SCR_EL3, but wrongly read from SPSR_EL3 instead. This patch fixes that. Change-Id: I8ffea39cc98ef59cb8e7a4c6ef4cb12011c58536 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | Merge pull request #1442 from jeenu-arm/sdei-dispatch-fixDimitris Papastamos2018-06-221-1/+1
|\ \ \ | | | | | | | | SDEI: Fix dispatch bug
| * | | SDEI: Fix dispatch bugJeenu Viswambharan2018-06-221-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | The Commit cdb6ac94ecb3c4caa784cd4d7580cf6252146196 introduced a bug because of which the SDEI dispatcher wrongly panic when an SDEI event dispatched earlier as a result of interrupt. This patch fixes the check for a bound interrupt. Change-Id: If55c8f0422ff781731248bbbc9c1b59fa0d3c4b0 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | Merge pull request #1437 from jeenu-arm/ras-remainingDimitris Papastamos2018-06-2215-162/+373
|\ \ \ | | | | | | | | SDEI dispatch changes to enable RAS use cases
| * | | Arm platforms: Remove common RAS configuration sourceJeenu Viswambharan2018-06-214-18/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file arm_ras.c intended to provide common platform-specific RAS configuration for Arm platforms. Because this file has symbol definitions, it's proving difficult to provide a common definition. This patch therefore renames and makes the file specific to FVP. Other platforms shall provide their own configuration in similar fashion. Change-Id: I766fd238946e3e49cdb659680e1b45f41b237901 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | SDEI: Make dispatches synchronousJeenu Viswambharan2018-06-218-122/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDEI event dispatches currently only sets up the Non-secure context before returning to the caller. The actual dispatch only happens upon exiting EL3 next time. However, for various error handling scenarios, it's beneficial to have the dispatch happen synchronously. I.e. when receiving SDEI interrupt, or for a successful sdei_dispatch_event() call, the event handler is executed; and upon the event completion, dispatcher execution resumes after the point of dispatch. The jump primitives introduced in the earlier patch facilitates this feature. With this patch: - SDEI interrupts and calls to sdei_dispatch_event prepares the NS context for event dispatch, then sets a jump point, and immediately exits EL3. This results in the client handler executing in Non-secure. - When the SDEI client completes the dispatched event, the SDEI dispatcher does a longjmp to the jump pointer created earlier. For the caller of the sdei_dispatch_event() in particular, this would appear as if call returned successfully. The dynamic workaround for CVE_2018_3639 is slightly shifted around as part of related minor refactoring. It doesn't affect the workaround functionality. Documentation updated. NOTE: This breaks the semantics of the explicit dispatch API, and any exiting usages should be carefully reviewed. Change-Id: Ib9c876d27ea2af7fb22de49832e55a0da83da3f9 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | BL31: Introduce jump primitivesJeenu Viswambharan2018-06-213-2/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces setjmp() and ongjmp() primitives to enable standard setjmp/longjmp style execution. Both APIs parameters take a pointer to struct jmpbuf type, which hosts CPU registers saved/restored during jump. As per the standard usage: - setjmp() return 0 when a jump is setup; and a non-zero value when returning from jump. - The caller of setjmp() must not return, or otherwise update stack pointer since. Change-Id: I4af1d32e490cfa547979631b762b4cba188d0551 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | SDEI: Determine client EL from NS context's SCR_EL3Jeenu Viswambharan2018-06-213-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the dispatcher reads from SCR_EL3 register directly to determine the EL of SDEI client. This is with the assumption that SCR_EL3 is not modified throughout. However, with RAS work flows, it's possible that SCR_EL3 register contains values corresponding to Secure world, and therefore EL determination can go wrong. To mitigate this, always read the register from the saved Non-secure context. Change-Id: Ic85e4021deb18eb58757f676f9a001174998543a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | SDEI: Allow platforms to define explicit eventsJeenu Viswambharan2018-06-215-17/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current macros only allow to define dynamic and statically-bound SDEI events. However, there ought be a mechanism to define SDEI events that are explicitly dispatched; i.e., events that are dispatched as a result of a previous secure interrupt or other exception This patch introduces SDEI_EXPLICIT_EVENT() macro to define an explicit event. They must be placed under private mappings. Only the priority flags are allowed to be additionally specified. Documentation updated. Change-Id: I2e12f5571381195d6234c9dfbd5904608ad41db3 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | | Merge pull request #1440 from antonio-nino-diaz-arm/an/xlat-enumsDimitris Papastamos2018-06-227-110/+110
|\ \ \ \ | | | | | | | | | | xlat: Remove mmap_attr_t enum type
| * | | | xlat: Remove mmap_attr_t enum typeAntonio Nino Diaz2018-06-227-110/+110
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The values defined in this type are used in logical operations, which goes against MISRA Rule 10.1: "Operands shall not be of an inappropriate essential type". Now, `unsigned int` is used instead. This also allows us to move the dynamic mapping bit from 30 to 31. It was an undefined behaviour in the past because an enum is signed by default, and bit 31 corresponds to the sign bit. It is undefined behaviour to modify the sign bit. Now, bit 31 is free to use as it was originally meant to be. mmap_attr_t is now defined as an `unsigned int` for backwards compatibility. Change-Id: I6b31218c14b9c7fdabebe432de7fae6e90a97f34 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1427 from b49020/integrationDimitris Papastamos2018-06-2218-1/+1416
|\ \ \ \ | | | | | | | | | | Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform.
| * | | | synquacer: Add platform makefile and documentationSumit Garg2018-06-214-1/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * | | | synquacer: Enable PSCI frameworkSumit Garg2018-06-212-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Retrieve DRAM info from SCP firmwareArd Biesheuvel2018-06-214-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Add SCPI driverSumit Garg2018-06-213-0/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Add MHU driverSumit Garg2018-06-215-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Enable MMU using xlat_tables_v2 librarySumit Garg2018-06-214-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Enable System level Generic timerSumit Garg2018-06-212-0/+41
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Enable GICv3 supportSumit Garg2018-06-214-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Enable CCN driver supportSumit Garg2018-06-214-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Implement topology functionsSumit Garg2018-06-213-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Populate BL32 and BL33 entrypointsSumit Garg2018-06-211-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Enable PL011 UART ConsoleSumit Garg2018-06-213-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Add platform core management helpersSumit Garg2018-06-213-0/+90
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | | synquacer: Introduce basic platform supportSumit Garg2018-06-212-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synquacer supports direct entry to BL31 without BL1 and BL2 as SCP firmware does similar work. So this patch adds BL31 stub APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* | | | | Merge pull request #1436 from antonio-nino-diaz-arm/an/spm-syncDimitris Papastamos2018-06-212-18/+34
|\ \ \ \ \ | |_|/ / / |/| | | | SPM: Allow entering the SP without needing a SMC
| * | | | SPM: Allow entering the SP without needing a SMCAntonio Nino Diaz2018-06-202-18/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It may be needed to enter the Secure Partition through other means than an MM_COMMUNICATE SMC. This patch enables this behaviour by extracting the necessary code from mm_communicate() and allowing other parts of the code to use it. Change-Id: I59f6638d22d9c9d0baff0984f39d056298a8dc8e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | | Merge pull request #1439 from dp-arm/dp/bl2_sizeDimitris Papastamos2018-06-211-1/+1
|\ \ \ \ \ | | | | | | | | | | | | fvp: Increase BL2 size for TBBR builds
| * | | | | fvp: Increase BL2 size for TBBR buildsDimitris Papastamos2018-06-211-1/+1
|/ / / / / | | | | | | | | | | | | | | | | | | | | Change-Id: I67e64bb79cc984ea3263f069e22738a42321c46d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | | | | Merge pull request #1428 from jeenu-arm/mbedtlsDimitris Papastamos2018-06-212-2/+4
|\ \ \ \ \ | | | | | | | | | | | | Move to mbedtls-2.10.0 tag
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