aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Fix MISRA rule 8.4Roberto Vargas2018-07-102-1/+2
| | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32 Change-Id: I3ac25096b55774689112ae37bdf1222f9a9ecffb Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Fix MISRA rule 8.3Roberto Vargas2018-07-105-7/+7
| | | | | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Fixed for: make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32 Change-Id: Ia34f5155e1cdb67161191f69e8d1248cbaa39e1a Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Merge pull request #1463 from grandpaul/paulliu-rpi3-tbb0Dimitris Papastamos2018-07-066-41/+142
|\ | | | | rpi3: Add support for Trusted Board Boot
| * docs: rpi3: add description for Trusted Board BootYing-Chun Liu (PaulLiu)2018-07-051-0/+10
| | | | | | | | | | | | | | Add paragraph for how to enable Trusted Board Boot for rpi3 Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
| * docs: rpi3: fix the size of BL1Ying-Chun Liu (PaulLiu)2018-07-051-2/+2
| | | | | | | | | | | | | | For Trusted Board Boot we enlarge the BL1 size from 64k to 128k. Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
| * rpi3: Add support for Trusted Board BootYing-Chun Liu (PaulLiu)2018-07-055-39/+130
| | | | | | | | | | | | | | | | | | This patch adds support for TBB to rpi3. The ROTPK is generated at build time and is included into BL1/BL2. The key and content certificates are read over semihosting. Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
* | Merge pull request #1465 from Andre-ARM/allwinner/h6-supportDimitris Papastamos2018-07-056-1/+158
|\ \ | | | | | | allwinner: Add H6 SoC support
| * | maintainers: allwinner: add missing link to github pageAndre Przywara2018-07-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | A proper link to Samuel's github page was missing. Add this to make the link actually work. Change-Id: I68b116935bf045df60b2e9309b5fd58a1c694d47 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | allwinner: Add Allwinner H6 SoC supportAndre Przywara2018-07-035-1/+157
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The H6 is Allwinner's most recent SoC. It shares most peripherals with the other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory map. Introduce a separate platform target, which includes a different header file to cater for the address differences. Also add the new build target to the documentation. The new ATF platform name is "sun50i_h6". Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge pull request #1461 from antonio-nino-diaz-arm/an/xlat-docsDimitris Papastamos2018-07-041-31/+42
|\ \ | | | | | | xlat v2: Update documentation
| * | xlat v2: Update documentationAntonio Nino Diaz2018-07-031-31/+42
| | | | | | | | | | | | | | | | | | | | | Update documentation to reflect the current state of the library. Change-Id: Ic72f90ee322d2ebd6ea7f4296315700d6bc434e6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1396 from ruchi393/multiple_fipDimitris Papastamos2018-07-041-10/+114
|\ \ \ | | | | | | | | Extend FIP io driver to support multiple FIP devices
| * | | Extend FIP io driver to support multiple FIP devicesRuchika Gupta2018-07-021-10/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platform can define MAX_NUM_FIP_DEVICES in platform_def.h to define the number of FIP io devices. The FIP driver doesn't support muliple open file. So only one single file can be open at a time across multiple FIP devices. For any FIP device, an image should be loaded fully before moving on to the next image. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
* | | | Merge pull request #1462 from ↵Dimitris Papastamos2018-07-044-14/+28
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | sandrine-bailleux-arm/topics/sb/no-unaligned-access Fixes related to unaligned accesses
| * | | Fix incorrect pointer conversion in SMC_UUID_RET()Sandrine Bailleux2018-07-033-14/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Casting a pointer to a struct uuid into a pointer to uint32_t may result in a pointer that is not correctly aligned, which constitutes an undefined behaviour. In the case of TF, this also generates a data abort because alignment fault checking is enabled (through the SCTLR.A bit). This patch modifies the SMC_UUID_RET() macro to read the uuid structure without any pointer aliasing. A helper function then combines every set of 4 bytes into a 32-bit value suitable to be returned through the x0-x3 registers. This fixes a violation of MISRA rule 11.3. Change-Id: I53ee73bb4cb332f4d8286055ceceb6f347caa080 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
| * | | AArch32: Force compiler to align memory accessesSandrine Bailleux2018-07-031-0/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alignment fault checking is always enabled in TF (by setting the SCTLR.A bit). Thus, all instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. The compiler needs to be aware that it must not emit load and store instructions resulting in unaligned accesses. It already is for AArch64 builds (see commit fa1d37122c "Add -mstrict-align to the gcc options"), this patch does the same for AArch32 builds. Change-Id: Ic885796bc6ed0ff392aae2d49f3a13f517e0169f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | Merge pull request #1459 from antonio-nino-diaz-arm/an/xlat-refactorDimitris Papastamos2018-07-0311-709/+720
|\ \ \ | | |/ | |/| Refactor of the xlat tables v2 library
| * | xlat v2: Make get/set attrs functions less verboseAntonio Nino Diaz2018-07-031-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to have LOG_LEVEL_VERBOSE because it prints the memory map of each image, but that also means that the change_mem_attributes and get_mem_attributes functions have verbose prints, and generate a too long text output that hides other useful information. As they were mostly there for debug purposes, this patch removes them. Change-Id: I2986537377d1f78be2b79cc8a6cf230c380bdb55 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | xlat v2: Clean debug xlat tables descriptor printAntonio Nino Diaz2018-07-031-36/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous debug output for EL1&0 translation regimes was too verbose, which makes it hard to read and hides the intent behind the parameters assigned to each region. This patch simplifies this output and makes the outputs for EL3 and EL1&0 mostly the same. The difference is that in EL1&0 it is specified whether the region is exclusively accessible from EL1 (PRIV) or both EL0 and EL1 (USER). For example: MEM-RW(PRIV)-NOACCESS(USER)-XN(PRIV)-XN(USER)-S MEM-RO(PRIV)-NOACCESS(USER)-EXEC(PRIV)-EXEC(USER)-S After the change, it becomes this: MEM-RW-XN-PRIV-S MEM-RO-EXEC-PRIV-S Change-Id: I15f4b99058429d42107fbf89e15f4838a9b559a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | xlat v2: Split code into separate filesAntonio Nino Diaz2018-07-0311-709/+750
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of having one big file with all the code, it's better to have a few smaller files that are more manageable: - xlat_tables_core.c: Code related to the core functionality of the library (map and unmap regions, initialize xlat context). - xlat_tables_context.c: Instantiation of the active image context as well as APIs to manipulate it. - xlat_tables_utils.c: Helper code that isn't part of the core functionality (change attributes, debug print messages). Change-Id: I3ea956fc1afd7473c0bb5e7c6aab3b2e5d88c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1458 from Andre-ARM/allwinner/fixesDimitris Papastamos2018-07-0310-11/+47
|\ \ \ | | | | | | | | allwinner: various smaller fixes
| * | | allwinner: Add Samuel as second maintainerAndre Przywara2018-06-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As Samuel contributed most of the original code and he has an interest in that, add him as a second maintainer for the Allwinner port. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: Detect and output current SoCAndre Przywara2018-06-283-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we already support booting on two different SoCs, and we will shortly add a third, so add some code to determine the current SoC type. This can be later used to runtime detect certain properties. Also print the SoC name to the console, to give valuable debug information. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: Don't map boot ROMAndre Przywara2018-06-282-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is nothing we need from the BootROM area, so we also don't need to map it in EL3. Remove the mapping and reduce the number of MMAP regions by one. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: Relax PSCI entry point checkAndre Przywara2018-06-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM controller supports up to 4GB of DRAM, and there are actually boards out there where we can use at least 3GB of this. Relax the PSCI entry point check, to be not restricted to 2GB of DRAM. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: security: Fix SPC guardAndre Przywara2018-06-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "#ifdef SUNXI_SPC_BASE" guard was meant to allow the build on SoCs without a Secure Peripherals Controller, so that we skip that part of the security setup. But in the current position this will trigger a warning about an unused variable. Simply move the guard one line up to cover the variable as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: cpu-ops: avoid PSCI on/off outputAndre Przywara2018-06-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more obvious by changing the log level to "VERBOSE" and so avoiding it to be printed in a normal (even debug) build. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: sun50i_a64: remove unneeded VER_REG offsetAndre Przywara2018-06-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The relative VER_REG *offset* is the same across all known SoCs, so we can define this offset near it's user. Remove it from the memory map. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: doc: add missing paragraphsAndre Przywara2018-06-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two empty lines to denote the paragraphs properly and improve readability. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: common: add missing headerAndre Przywara2018-06-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some code in sunxi_common.c requires symbols defined in sunxi_private.h, so add the header to that file. It was included via another header before, but let's make this explicit. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | allwinner: Add BL32 (corresponds to Trusted OS) supportAmit Singh Tomar2018-06-283-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along side BL31 image. ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS) as an input using the 'SPD=<dispatcher name>' option during bl31 build. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* | | | Merge pull request #1447 from Amit-Radur/bl32_v1Dimitris Papastamos2018-07-033-2/+31
|\ \ \ \ | |_|/ / |/| | | allwinner: Add BL32 (corresponds to Trusted OS) support
| * | | allwinner: Add BL32 (corresponds to Trusted OS) supportAmit Singh Tomar2018-06-233-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along side BL31 image. ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS) as an input using the 'SPD=<dispatcher name>' option during bl31 build. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* | | | Merge pull request #1456 from robertovargas-arm/make_certDimitris Papastamos2018-07-021-3/+1
|\ \ \ \ | | | | | | | | | | make_cert: return error when invalid options are used
| * | | | make_cert: return error when invalid options are usedRoberto Vargas2018-06-271-3/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print_help was used in different contexts and returning no error in that function was hiding the error when incorrect options were used. Change-Id: Ic3f71748be7ff8440c9d54810b986e9f177f4439 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | | Merge pull request #1452 from glneo/fixups-for-k3Dimitris Papastamos2018-07-023-6/+14
|\ \ \ \ | |_|_|/ |/| | | Couple of fixups for K3 platform
| * | | ti: k3: common: Enable interrupts before entering standby stateAndrew F. Davis2018-06-291-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To wake a core from wfi interrupts must be enabled, in some cases they may not be and so we can lock up here. Unconditionally enable interrupts before wfi and then restore interrupt state. Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | ti: k3: common: Add root domain node to platform topologyAndrew F. Davis2018-06-292-2/+4
|/ / / | | | | | | | | | | | | | | | | | | | | | Actions may need to be taken by the last core when all clusters have been shutdown. Add a top level root domain node to coordinate this between clusters. Signed-off-by: Andrew F. Davis <afd@ti.com>
* | | Merge pull request #1457 from antonio-nino-diaz-arm/an/maintainersDimitris Papastamos2018-06-281-178/+156
|\ \ \ | | | | | | | | maintainers: Modify format of file
| * | | maintainers: Modify format of fileAntonio Nino Diaz2018-06-281-178/+156
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous format was not very practical and hard to parse by scripts. The current format is easier as it uses more tokens that can be identified by scripts, while maintaining a reasonably good result when it is rendered. Some maintainers maintain more than one subsystem but they were all part of the same entry. In cases like this the entry has been split into two to clarify what file belongs to which subsystem. The list of maintainers of the Trusted Firmware has been updated. Change-Id: I4be2d527c5171e8d2d86fb49e45e1d9dbcbd2d80 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1429 from jeenu-arm/mmu-directDimitris Papastamos2018-06-2724-179/+327
|\ \ \ | | | | | | | | Enable MMU without stack for xlat v2/DynamIQ
| * | | TSP: Enable cache along with MMUJeenu Viswambharan2018-06-271-31/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. Change-Id: I73f3b8bae5178610e17e9ad06f81f8f6f97734a6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | DynamIQ: Enable MMU without using stackJeenu Viswambharan2018-06-277-26/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having an active stack while enabling MMU has shown coherency problems. This patch builds on top of translation library changes that introduces MMU-enabling without using stacks. Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. NOTE: Since this feature depends on using translation table library v2, disallow using translation table library v1 with HW_ASSISTED_COHERENCY. Fixes ARM-software/tf-issues#566 Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | xlat v1: Provide direct MMU-enabling stubsJeenu Viswambharan2018-06-272-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An earlier patch split MMU-enabling function for translation library v2. Although we don't intend to introduce the exact same functionality for xlat v1, this patch introduces stubs for directly enabling MMU to maintain API-compatibility. Change-Id: Id7d56e124c80af71de999fcda10f1734b50bca97 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | xlat v2: Split MMU setup and enableJeenu Viswambharan2018-06-2714-121/+256
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, the function provided by the translation library to enable MMU constructs appropriate values for translation library, and programs them to the right registers. The construction of initial values, however, is only required once as both the primary and secondaries program the same values. Additionally, the MMU-enabling function is written in C, which means there's an active stack at the time of enabling MMU. On some systems, like Arm DynamIQ, having active stack while enabling MMU during warm boot might lead to coherency problems. This patch addresses both the above problems by: - Splitting the MMU-enabling function into two: one that sets up values to be programmed into the registers, and another one that takes the pre-computed values and writes to the appropriate registers. With this, the primary effectively calls both functions to have the MMU enabled, but secondaries only need to call the latter. - Rewriting the function that enables MMU in assembly so that it doesn't use stack. This patch fixes a bunch of MISRA issues on the way. Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | Merge pull request #1453 from soby-mathew/sm/set_cntfrq_bl1Dimitris Papastamos2018-06-272-0/+8
|\ \ \ | | | | | | | | ARM platforms: Initialize cntfrq for BL1 Firmware update
| * | | ARM platforms: Initialize cntfrq for BL1 Firmware updateSoby Mathew2018-06-262-0/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Currenly the CNTFRQ register and system timer is initialized in BL31 for use by the normal world. During firmware update, the NS-BL1 or NS-BL2U may need to access the system timer. Hence this patch duplicates the CNTFRQ and system timer initialization in BL1 as well. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I1ede78b4ae64080fb418cb93f3e48b26d7b724dc
* | | Merge pull request #1455 from antonio-nino-diaz-arm/an/ep-docDimitris Papastamos2018-06-271-21/+26
|\ \ \ | |/ / |/| | Document ep_info attribute flags
| * | Document ep_info attribute flagsAntonio Nino Diaz2018-06-261-21/+26
|/ / | | | | | | | | | | | | | | | | | | The meaning of them wasn't clear in the header file, it was needed to search the code for the places where they are used. Add parentheses to macros in the same header. Change-Id: I700bc0fd75ccfc0a34f439cb3b2692861bb73b9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1445 from danielboulby-arm/db/DynamicAuthenticationDimitris Papastamos2018-06-251-1/+1
|\ \ | | | | | | Set FVP DYN_DISABLE_AUTH authentication default to 0
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 17:34:19 +0000