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* TSP: Enable pointer authentication supportAntonio Nino Diaz2019-02-274-7/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.4% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +352 | +0 | +16 | +0 | | | 3.1% | | 15.8% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I6cc1fe0b2345c547dcef66f98758c4eb55fe5ee4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* BL31: Enable pointer authentication supportAntonio Nino Diaz2019-02-274-11/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +192 | +1536 | +0 | +0 | | | 0.3% | 3.1% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +1848 | +1536 | +16 | +0 | | | 3.3% | 3.1% | 3.1% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I43db7e509a4f39da6599ec2faa690d197573ec1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* BL2_AT_EL3: Enable pointer authentication supportAntonio Nino Diaz2019-02-274-15/+74
| | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +44 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +712 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ The results are valid for the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ BL2_AT_EL3=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* BL2: Enable pointer authentication supportAntonio Nino Diaz2019-02-275-15/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +664 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 The changes for BL2_AT_EL3 aren't done in this commit. Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* BL1: Enable pointer authentication supportAntonio Nino Diaz2019-02-275-20/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +108 | +192 | +0 | +0 | | | 0.5% | 0.8% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +748 | +192 | +16 | +0 | | | 3.7% | 0.8% | 7.0% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm: Implement ARMv8.3-PAuth interfacesAntonio Nino Diaz2019-02-272-0/+37
| | | | | | | This feature is only supported on FVP. Change-Id: I4e265610211d92a84bd2773c34acfbe02a1a1826 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Add support for pointer authenticationAntonio Nino Diaz2019-02-2713-5/+166
| | | | | | | | | | | | | | | The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Add ARMv8.3-PAuth registers to CPU contextAntonio Nino Diaz2019-02-2711-20/+201
| | | | | | | | | | | | | | | | | | | | | | | ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Cleanup context handling libraryAntonio Nino Diaz2019-02-272-34/+34
| | | | | | | Minor style cleanup. Change-Id: Ief19dece41a989e2e8157859a265701549f6c585 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1834 from thloh85-intel/s10_bl31Antonio Niño Díaz2019-02-2711-19/+1305
|\ | | | | plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
| * plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platformTien Hock, Loh2019-02-2611-19/+1305
| | | | | | | | | | | | | | | | | | This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
* | Merge pull request #1831 from antonio-nino-diaz-arm/an/sccdAntonio Niño Díaz2019-02-274-15/+29
|\ \ | | | | | | Disable processor Cycle Counting in Secure state
| * | Disable processor Cycle Counting in Secure stateAntonio Nino Diaz2019-02-184-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a system with ARMv8.5-PMU implemented: - If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting in Secure state in PMCCNTR. - If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in Secure state in PMCCNTR_EL0. So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64) or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure as any EL can change that value. Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1826 from smaeul/allwinnerAntonio Niño Díaz2019-02-277-25/+34
|\ \ \ | | | | | | | | allwinner: A few minor improvements
| * | | allwinner: Clean up CPU ops functionsSamuel Holland2019-02-174-21/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert them to take an mpidr instead of a (cluster, core) pair. This simplifies all of the call sites, and actually makes the functions a bit smaller. Signed-off-by: Samuel Holland <samuel@sholland.org>
| * | | allwinner: Constify data structuresSamuel Holland2019-02-173-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | This maximizes the amount of data protected by the MMU. Signed-off-by: Samuel Holland <samuel@sholland.org>
* | | | Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz2019-02-229-1/+98
|\ \ \ \ | | | | | | | | | | Update documentation for STM32MP1 and add Cortex-M4 support
| * | | | stm32mp1: add minimal support for co-processor Cortex-M4Yann Gautier2019-02-208-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | docs: stm32mp1: add links to documentationYann Gautier2019-02-201-1/+6
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A link to st.com page describing STM32MP1 is added. Add the information about Cortex-M4 embedded in STM32MP1. Correct typo for u-boot command. Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | | Merge pull request #1835 from jts-arm/renameAntonio Niño Díaz2019-02-2216-176/+176
|\ \ \ \ | | | | | | | | | | Apply official names to new Arm Neoverse cores
| * | | | Rename Cortex-Helios to Neoverse E1John Tsichritzis2019-02-193-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | | Rename Cortex-Helios filenames to Neoverse E1John Tsichritzis2019-02-192-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | | Rename Cortex-Ares to Neoverse N1John Tsichritzis2019-02-1910-82/+82
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | | Rename Cortex-Ares filenames to Neoverse N1John Tsichritzis2019-02-193-0/+0
| | |_|/ | |/| | | | | | | | | | | | | | Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | | Merge pull request #1828 from uarif1/masterAntonio Niño Díaz2019-02-2130-24/+1802
|\ \ \ \ | | | | | | | | | | Introduce Versatile Express FVP platform to arm-trusted-firmware.
| * | | | Documentation for Versatile Express Fixed Virtual PlatformsUsama Arif2019-02-191-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This documentation contains information about the boot sequence, code location and build procedure for fvp_ve platform. Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | | plat/arm: Support for Cortex A5 in FVP Versatile Express platformUsama Arif2019-02-195-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex A5 doesnt support VFP, Large Page addressing and generic timer which are addressed in this patch. The device tree for Cortex a5 is also included. Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678 Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | | Division functionality for cores that dont have divide hardware.Usama Arif2019-02-192-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex a5 doesnt support hardware division such as sdiv and udiv commands. This commit adds a software division function in assembly as well as include appropriate files for software divison. The software division algorithm is a modified version obtained from: http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652 Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | | ARMv7: support non-LPAE mapping (not xlat_v2)Etienne Carriere2019-02-192-1/+555
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support 32bit descriptor MMU table. This is required by ARMv7 architectures that do not support the Large Page Address Extensions. nonlpae_tables.c source file is dumped from the OP-TEE project: core_mmu_armv7.c and related header files. Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | | plat/arm: Introduce FVP Versatile Express platform.Usama Arif2019-02-1919-6/+958
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Versatile express FVP (Fast models). Versatile express is a family of platforms that are based on ARM v7. Currently this port has only been tested on Cortex A7, although it should work with other ARM V7 cores that support LPAE, generic timers, VFP and hardware divide. Future patches will support other cores like Cortex A5 that dont support features like LPAE and hardware divide. This platform is tested on and only expected to work on single core models. Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | | Rename PLAT_ARM_BL31_RUN_UART* variableUsama Arif2019-02-184-16/+16
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variable is renamed to PLAT_ARM_RUN_UART as the UART is used outside BL31 as well. Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a Signed-off-by: Usama Arif <usama.arif@arm.com>
* | | | Merge pull request #1833 from marex/arm/master/pci-v2.0.0Antonio Niño Díaz2019-02-212-2/+74
|\ \ \ \ | |_|/ / |/| | | rcar_gen3: plat: Prevent PCIe hang during L1X config access
| * | | rcar_gen3: plat: Prevent PCIe hang during L1X config accessMarek Vasut2019-02-202-2/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the PCIe controller receives a L1_Enter_PM DLLP, it will disable the internal PLLs. The system software cannot predict it and can attempt to perform device config space access across the PCIe link while the controller is in this transitional state. If such condition happens, the PCIe controller register access will trigger ARM64 SError exception. This patch adds checks for which PCIe controller is enabled, checks whether the PCIe controller is in such a transitional state and if so, first completes the transition and then restarts the instruction which caused the SError. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | | Merge pull request #1832 from jts-arm/docsAntonio Niño Díaz2019-02-206-0/+131
|\ \ \ \ | | | | | | | | | | docs: Document romlib design
| * | | | docs: Document romlib designSathees Balya2019-02-196-0/+131
| | |/ / | |/| | | | | | | | | | | | | | | | | | Change-Id: I2b75be16f452a8ab7c2445ccd519fb057a135812 Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com> Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | | Merge pull request #1830 from antonio-nino-diaz-arm/an/fix-fw-designAntonio Niño Díaz2019-02-201-5/+3
|\ \ \ \ | |_|/ / |/| | | docs: Update documentation about ARMv8.2-TTCNP
| * | | docs: Update documentation about ARMv8.2-TTCNPAntonio Nino Diaz2019-02-191-5/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Commit 2559b2c8256f ("xlat v2: Dynamically detect need for CnP bit") modified the code to convert the compile-time check for ARMv8.2-TTCNP to a runtime check, but forgot to update the documentation associated to it. Change-Id: I6d33a4de389d976dbdcce65d8fdf138959530669 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1825 from antonio-nino-diaz-arm/an/csv2Antonio Niño Díaz2019-02-191-5/+17
|\ \ \ | |/ / |/| | Update macro to check need for CVE-2017-5715 mitigation
| * | Update macro to check need for CVE-2017-5715 mitigationAntonio Nino Diaz2019-02-141-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armv8.5 introduces the field CSV2 to register ID_AA64PFR0_EL1. It can have the following 3 values: - 0: Branch targets trained in one hardware described context may affect speculative execution in a different hardware described context. In some CPUs it may be needed to apply mitigations. - 1: Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. No mitigation required. - 2: Same as 1, but the device is also aware of SCXTNUM_ELx register contexts. The TF doesn't use the registers, so there is no difference with 1. The field CSV2 was originally introduced in the TRM of the Cortex-A76 before the release of the Armv8.5 architecture. That TRM only mentions the meaning of values 0 and 1. Because of this, the code only checks if the field has value 1 to know whether to enable or disable the mitigations. This patch makes it aware of value 2 as well. Both values 1 and 2 disable the mitigation, and 0 enables it. Change-Id: I5af33de25a0197c98173f52c6c8c77b51a51429f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1824 from antonio-nino-diaz-arm/an/move-dyn-xlatAntonio Niño Díaz2019-02-182-3/+4
|\ \ \ | | | | | | | | fvp: trusty: Move dynamic xlat enable to platform
| * | | fvp: trusty: Move dynamic xlat enable to platformAntonio Nino Diaz2019-02-122-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than letting the Trusty makefile set the option to enable dynamic translation tables, make platforms do it themselves. This also allows platforms to replace the implementation of the translation tables library as long as they use the same function prototypes. Change-Id: Ia60904f61709ac323addcb57f7a83391d9e21cd0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1823 from antonio-nino-diaz-arm/an/spm-regsAntonio Niño Díaz2019-02-181-8/+0
|\ \ \ \ | | | | | | | | | | SPM: Remove unnecessary register save
| * | | | SPM: Remove unnecessary register saveAntonio Nino Diaz2019-02-141-8/+0
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 01fc1c24b9a0 ("BL31: Use helper function to save registers in SMC handler") all the general-purpose registers are saved when entering EL3. It isn't needed to save them here. Change-Id: Ic540a5441b89b70888da587ab8fc3b2508cef8cc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14Antonio Niño Díaz2019-02-1846-1980/+3148
|\ \ \ \ | |_|_|/ |/| | | Series of new patches for STM32MP1
| * | | stm32mp1: introduce STM32MP1 discovery boardsYann Gautier2019-02-144-0/+503
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree files to support the 2 discovery boards: DK1 & DK2. Change-Id: I90b4797dc69bd0aab1b643a72c932ead48a03c1f Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | stm32mp1: update clock driverYann Gautier2019-02-1414-567/+843
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks. Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
| * | | stm32mp1: add timeout detection in reset driverYann Gautier2019-02-142-12/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes the platform to panic in case of peripheral reset resource malfunction. Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
| * | | stm32mp1: use functions to retrieve some peripheral addressesYann Gautier2019-02-1410-17/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC addresses. Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
| * | | stm32mp1: split clkfunc codeYann Gautier2019-02-148-242/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a new file stm32mp_clkfunc.c to put functions that could be common between several platforms. Change-Id: Ica915c796b162b2345056b33328acc05035a242c Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | stm32mp1: update I2C and PMIC driversYann Gautier2019-02-148-730/+931
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regulator configuration at boot takes more information from DT. I2C configuration from DT is done in I2C driver. I2C driver manages more transfer modes. The min voltage of buck1 should also be increased to 1.2V, else the platform does not boot. Heavily modifies stm32_i2c.c since many functions move inside the source file to remove redundant declarations. Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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