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* docs: marvell: Fix typo in file build.txtDing Tao2018-12-101-1/+1
| | | | | | Replace "Uboot" with "Ubuntu". Signed-off-by: Ding Tao <miyatsu@qq.com>
* Merge pull request #1711 from antonio-nino-diaz-arm/an/fix-imxAntonio Niño Díaz2018-12-051-3/+3
|\ | | | | tzc380: Fix some asserts
| * tzc380: Fix some assertsAntonio Nino Diaz2018-12-051-3/+3
|/ | | | | | | | | This driver can be compiled in release builds, but GCC generates warnings for some comparisons and that prevents the firmware from being built in debug builds. Change-Id: Ic52e1b4a11896ecf086864fbe2b5bfc143ec9b1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1653 from JackyBai/masterAntonio Niño Díaz2018-12-0513-21/+1289
|\ | | | | Add NXP i.MX8MQ basic support
| * plat: imx: Add i.MX8MQ basic supportBai Ping2018-12-059-0/+1018
| | | | | | | | | | | | | | | | | | | | | | | | | | i.MX8MQ is new SOC of NXP's i.MX8M family based on A53. It can provide industry-leading audio, voice and video processing for applications that scale from consumer home audio to industrial building automation and mobile computers this patchset add the basic supoort to boot up the 4 X A53. more feature will be added later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
| * drivers: add tzc380 supportPeng Fan2018-12-044-21/+271
| | | | | | | | | | | | | | Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
* | Merge pull request #1703 from oscardagrach/hikey960-dmac-fixAntonio Niño Díaz2018-12-042-0/+23
|\ \ | | | | | | hikey960: initialize EDMAC and channels
| * | hikey960: initialize EDMAC and channelsRyan Grachek2018-11-292-0/+23
| |/ | | | | | | | | | | This is needed to utilize the DMA controller on the hikey960 Signed-off-by: Ryan Grachek <ryan@edited.us>
* | Merge pull request #1705 from chandnich/platform-idAntonio Nino Diaz2018-12-047-67/+53
|\ \ | | | | | | | | | plat/arm/sgi: Use platform specific functions to get platform ids
| * | plat/arm/sgi: Use platform specific functions to get platform idsChandni Cherukuri2018-12-037-67/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two new functions 'plat_arm_sgi_get_platform_id' and 'plat_arm_sgi_get_config_id' which will be implemented by all the SGI platforms. These functions can be used to determine the part number and configuration id of the SGI platforms. In BL2, these functions are used to populate the 'system-id' node. In BL31, these functions are used to populate the 'sgi_plat_info_t' structure with the part number and configuration id of the platform. Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | Merge pull request #1702 from MISL-EBU-System-SW/patches-18.12Antonio Niño Díaz2018-12-0414-104/+404
|\ \ \ | | | | | | | | Update code with latest changes from Marvell LSP 18.12
| * | | plat/marvell: update platform LSP version to 18.12.0Konstantin Porotchkin2018-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Sync the platform code version with current Marvell LSP. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | a8k: pm: extend MSS_TRIGGER_TIMEOUTIgal Liberman2018-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Very rarely, during cpuidle operations the following error is seen: "PM MSG Trigger Timeout". This is caused by slow handling of message interrutps in the PM FW running on CM3 (under heavy PM operation load). This is not a real issue, so we extend the timeout to avoid the error prints. Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59670 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
| * | | plat/marvell: comphy: Add support for SFI on Lane 4Konstantin Porotchkin2018-12-041-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add static configuration for SFI+ 10Gbps interface on SERDES Lane 4. This is just a copy of Lane 2 static values, not optimized. Board-to-board iperf test shows up to 6Gbps transfer speed. Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
| * | | doc: marvell: Update build manual with new memory layoutsKonstantin Porotchkin2018-12-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add description for memory layouts used by EspressoBin v7 (DDR4) Change-Id: I199d8b52580b26e560f14b503a6e99d32de4f284 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61279 Reviewed-by: Stefan Chulski <stefanc@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
| * | | fix: a3900: pm: fix number of CPU power switches.Christine Gharzuzi2018-12-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Number of open power switches for CPUs should be three and now two. - This patch updates the value of open power switches from 0xfd (two power-switches) to 0xfc (three power-switches). Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| * | | svc: Update the EEPROM AVS values processingKonstantin Porotchkin2018-12-042-1/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SVC test builds for tuning AVS values. Update the SVC procedure and add EEPROM access. Add support for AP807 AVS values (10 bits wide). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | ble: ap807: Switch to PLL mode and update CPU frequencyChristine Gharzuzi2018-12-044-75/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | mvebu: cp110: avoid pcie power on/off sequence when called from LinuxIgal Liberman2018-12-044-10/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Armada 8K DB boards, PCIe initialization can be executed only once because PCIe reset performed during chip power on and it cannot be executed via GPIO later. This means that power on can be executed only once, when it's called from the bootloader. Power on: Read bit 21 of the mode, it marks if the caller is the bootloader or the Linux Kernel. Power off: Check if the comphy was already configured to PCIe, if yes, check if the caller is bootloader, if both conditions are true (PCIe mode and called by Linux) - skip the power-off. In addition, fix incorrect documentation describing mode fields - PCIe width is 3 bits, not 2. NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work with it). Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| * | | plat: marvell: a3700: do not power off cpu due to errata ref #13Grzegorz Jaszczyk2018-12-041-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not power off the CPU1 since there is no way to wake it up (wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata Ref #13 [In power saving mode, both cores must be powered off]: "When Core 0 is on and Core 1 is in power-off state, a Core 1 wake-up resets Core 0 as well and puts Core 0 back to ROM". To overcome described HW bug instead of powering the CPU off, let it reach WFI instruction, which is invoked by generic psci_do_cpu_off function after platform handler finishes. This will put the core in low power state and give a chance to wake it up. Before this change, after running secondary kernel via kexec, only one core was up, now both cores are up. Change-Id: I87f144867550728055d9b8a2edb84a14539acab7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| * | | mvebu: cp110: fix phy selector configuration for XFI1Grzegorz Jaszczyk2018-12-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extended phy selector configuration about XFI1 mode. Change-Id: I1309770bbb5fdbfb0127b6f12ee78974d1d6b19f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
* | | | Merge pull request #1699 from chandnich/sgi-mt-supportSoby Mathew2018-12-039-5/+28
|\ \ \ \ | |_|/ / |/| | | Add support to implement multi-threaded platforms for SGI
| * | | plat/arm/sgi: allow value of PLAT_MAX_PWR_LVL to be platform specificChandni Cherukuri2018-11-273-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms with multi-threaded CPUs, the number of power domains supported would be more than the value currently defined by PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform specific code and let the platform define the number of power domain levels. Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | plat/arm/sgi: override weak implementation of plat_arm_get_cpu_pe_countChandni Cherukuri2018-11-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support platforms which are based on multi-threaded CPUs, override the weak implementation of plat_arm_get_cpu_pe_count function to return the number of threads supported by the CPU used in the platform. Change-Id: Ia680773f1277b17e2d3d2414d87943dcece33e89 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | plat/arm/common: add an additional platform power levelChandni Cherukuri2018-11-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | plat/css: allow platforms to define the system power domain levelChandni Cherukuri2018-11-276-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | Merge pull request #1701 from chandnich/psci-opsSoby Mathew2018-11-3010-10/+42
|\ \ \ \ | |_|_|/ |/| | | remove weak implemention of 'plat_arm_psci_override_pm_ops'
| * | | plat/arm: remove weak implemention of 'plat_arm_psci_override_pm_ops' functionChandni Cherukuri2018-11-2910-10/+42
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to allow Arm platforms to override the default list of PSCI callbacks, remove the existing weak implementation of 'plat_arm_psci_override_pm_ops' function and let all the Arm platforms implement their own 'plat_arm_psci_override_pm_ops' function. For platforms that support SCMI protocol, the function 'css_scmi_override_pm_ops' can be additionally used as well to override the default PSCI callbacks. Change-Id: If7c27468bd51a00ea9c2a3716b5894163f5a9f3c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | Merge pull request #1688 from JoelHutton/jh/variant_1_mitigationsAntonio Niño Díaz2018-11-292-2/+9
|\ \ \ | | | | | | | | Initial Spectre V1 mitigations (CVE-2017-5753).
| * | | Initial Spectre V1 mitigations (CVE-2017-5753).Joel Hutton2018-11-262-2/+9
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial Spectre Variant 1 mitigations (CVE-2017-5753). A potential speculative data leak was found in PSCI code, this depends on a non-robust implementation of the `plat_get_core_pos_by_mpidr()` function. This is considered very low-risk. This patch adds a macro to mitigate this. Note not all code paths could be analyzed with current tools. Add a macro which makes a variable 'speculation safe', using the __builtin_speculation_safe_value function of GCC and llvm. This will be available in GCC 9, and is planned for llvm, but is not currently in mainline GCC or llvm. In order to implement this mitigation the compiler must support this builtin. Support is indicated by the __HAVE_SPECULATION_SAFE_VALUE flag. The -mtrack-speculation option maintains a 'tracker' register, which determines if the processor is in false speculation at any point. This adds instructions and increases code size, but avoids the performance impact of a hard barrier. Without the -mtrack-speculation option, __builtin_speculation_safe_value expands to a ISB DSB SY sequence after a conditional branch, before the speculation safe variable is used. With -mtrack-speculation a CSEL tracker, tracker, XZR, [cond]; AND safeval,tracker; CSDB sequence is added instead, clearing the vulnerable variable by AND'ing it with the tracker register, which is zero during speculative execution. [cond] are the status flags which will only be true during speculative execution. For more information on __builtin_speculation_safe_value and the -mtrack-speculation option see https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/compiler-support-for-mitigations The -mtracking option was not added, as the performance impact of the mitigation is low, and there is only one occurence. Change-Id: Ic9e66d1f4a5155e42e3e4055594974c230bfba3c Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* | | Merge pull request #1698 from hzhuang1/rm_emmc_delayAntonio Niño Díaz2018-11-292-1/+7
|\ \ \ | | | | | | | | Rm emmc delay
| * | | hikey: remove delay after eMMC initializedHaojian Zhuang2018-11-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 386b14bf64124ebf0368eab33ef07603e0c3138a Author: Haojian Zhuang <haojian.zhuang@linaro.org> Date: Wed Nov 21 09:19:49 2018 +0800 mmc: poll eMMC status after EXT_CSD command EXT_CSD command needs to access data from eMMC device. Add the operation of polling eMMC device status. Make sure the command is finished. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> A hacked delay time can't fit each eMMC device. Since the above commit enables the polling operation, remove the hacked delay time now. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * | | mmc: poll eMMC status after EXT_CSD commandHaojian Zhuang2018-11-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EXT_CSD command needs to access data from eMMC device. Add the operation of polling eMMC device status. Make sure the command is finished. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | | | Merge pull request #1679 from pangupta/masterAntonio Niño Díaz2018-11-292-0/+138
|\ \ \ \ | |_|_|/ |/| | | ccn: Introduce API to set and read value of node register
| * | | ccn: Introduce API to set and read value of node registerPankaj Gupta2018-11-232-0/+138
| | | | | | | | | | | | | | | | Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
* | | | Merge pull request #1693 from jeenu-arm/ehf-docAntonio Niño Díaz2018-11-2810-6/+914
|\ \ \ \ | | | | | | | | | | EHF and RAS documentation
| * | | | docs: Add RAS framework documentationJeenu Viswambharan2018-11-264-2/+263
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Ibf2b21b12ebc0af5815fc6643532a3be9100bf02 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | | docs: Add Exception Handling Framework documentationJeenu Viswambharan2018-11-265-1/+649
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I77d38758d18ba6dda1652b1b1e644fbfb14386cc Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
| * | | | SDEI: Unconditionally resume Secure if it was interruptedJeenu Viswambharan2018-11-261-3/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure world execution nearly always expect a controlled exit to Non-secure world. SDEI interrupts, although targets EL3, occur on behalf of Non-secure world, and may have higher priority than Secure world interrupts. Therefore they might preempt Secure execution, and yield execution to Non-secure SDEI handler. Upon completion of SDEI event handling (regardless of whether it's COPLETE or COMPLETE_AND_RESUME), we must resume Secure execution if it was preempted. Change-Id: I6edd991032588588427ba2fe6c3d7668f7080e3d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | | Merge pull request #1696 from satheesbalya-arm/sb1/sb1_2406_romlib_junoAntonio Niño Díaz2018-11-273-11/+75
|\ \ \ \ | | | | | | | | | | romlib: Add juno support for romlib
| * | | | juno: Add romlib supportSathees Balya2018-11-233-11/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to build a combined BL1 and ROMLIB binary file with the right page alignment in Juno. When USE_ROMLIB=1 is set for Juno, it generates the combined file bl1_romlib.bin which needs to be used instead of bl1.bin Change-Id: I407efbe48d3e522fa6ef855538a9587193cb1919 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
* | | | | Merge pull request #1695 from satheesbalya-arm/sb1/sb1_2641_romlib_phase2Antonio Niño Díaz2018-11-274-10/+16
|\ \ \ \ \ | |_|_|_|/ |/| | | | romlib: Allow patching of romlib functions
| * | | | romlib: Add map file generationSathees Balya2018-11-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I1f377d2d94c0fe8d2d9e62614f4a8e2dfcd9e745 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
| * | | | romlib: Add calloc_free register functionSathees Balya2018-11-221-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register functions have to be added to the jump table to allow patching in the future Change-Id: I57a885f7fc6290ea74a6096aea5b1867b2098eb7 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
| * | | | romlib: Allow patching of romlib functionsSathees Balya2018-11-223-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change allows patching of functions in the romlib. This can be done by adding "patch" at the end of the jump table entry for the function that needs to be patched in the file jmptbl.i. Functions patched in the jump table list will be built as part of the BL image and the romlib version will not be used Change-Id: Iefb200cb86e2a4b61ad3ee6180d3ecc39bad537f Signed-off-by: Sathees Balya <sathees.balya@arm.com>
* | | | | Merge pull request #1697 from antonio-nino-diaz-arm/an/archAntonio Niño Díaz2018-11-266-86/+196
|\ \ \ \ \ | |_|_|/ / |/| | | | Synchronise arch.h and arch_helpers.h with TF-A-Tests
| * | | | Synchronise arch.h and arch_helpers.h with TF-A-TestsAntonio Nino Diaz2018-11-266-61/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The headers forked at some point in the past and have diverged a lot. In order to make it easier to share code between TF-A-Tests and TF-A, this patch synchronises most of the definitions in the mentioned headers. This is not a complete sync, it has to be followed by more cleanup. This patch also removes the read helpers for the AArch32 instructions ats1cpr and ats1hr (they are write-only). Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | | Revert "aarch32: Apply workaround for errata 813419 of Cortex-A57"Antonio Nino Diaz2018-11-221-25/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6f512a3dfd61662dbdae4912fb6a320ae4d754d5. According to the 'Cortex-A57 MPCore Software Developers Errata Notice': This bug will only affect secure AArch64 EL3. If the above conditions occur, the CPU will not invalidate the targeted EL3 TLB entries and incorrect translations might occur. For this reason it is not needed in AArch32. Change-Id: I6f7b333817515499723e8f306145790ad6af9975 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1681 from Andre-ARM/allwinner/fixesAntonio Niño Díaz2018-11-232-6/+33
|\ \ \ \ | | | | | | | | | | allwinner: clock / power fixes
| * | | | allwinner: power: Add DCDC6 power railAndre Przywara2018-11-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is on by default and uses the default voltage. As there seems to be at least on board using a different voltage, add the rail to the list of known voltage lines, so we can setup the right voltage as early as possible. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-06 01:51:12 +0000