aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Apply stricter speculative load restrictionJohn Tsichritzis2019-03-125-11/+19
| | | | | | | | | | | The SCTLR.DSSBS bit is zero by default thus disabling speculative loads. However, we also explicitly set it to zero for BL2 and TSP images when each image initialises its context. This is done to ensure that the image environment is initialised in a safe state, regardless of the reset value of the bit. Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* allwinner: regulators: pick correct DT subnodeAndre Przywara2019-03-081-4/+8
| | | | | | | | | | | | | | So far the DT node describing the AXP803 PMIC used in many Allwinner A64 boards had only one subnode, so our code just entering the first subnode to find all regulators worked fine. However recent DT updates in the Linux kernel add more subnodes *before* that, so we need to make sure to explicitly enter the "regulators" subnode to find the information we are after. Improve some DT node parsing error handling on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Fixup register handling in aarch32 reset_handlerHeiko Stuebner2019-03-081-3/+3
| | | | | | | | | | | | | | | | The BL handover interface stores the bootloader arguments in registers r9-r12, so when the reset_handler stores the lr pointer in r10 it clobers one of the arguments. Adapt to use r8 and adapt the comment about registers allowed to clober. I've checked aarch32 reset_handlers and none seem to use higher registers as far as I can tell. Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* zynqmp: pm: Add support for setting PMU configuration objectLuca Ceresoli2019-03-081-1/+4
| | | | | | | | | Allow EL2 (e.g. U-Boot) to load the configuration object at runtime into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot and U-Boot SPL with PMU FW without hard-coding the configuration object. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
* Merge pull request #1867 from AlexeiFedorov/af/enable_ptrauth_warm_bootDimitris Papastamos2019-03-081-0/+13
|\ | | | | BL31: Enable pointer authentication support in warm boot path
| * BL31: Enable pointer authentication support in warm boot pathAlexei Fedorov2019-03-071-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current Pointer Authentication support added in commit b86048c40cb7d9ccd7aeac1681945676a6dc36ff PAuth gets enabled in BL31 cold boot entrypoint only, (see bl31_entrypoint() in bl31\aarch64\bl31_entrypoint.S) but not in bl31_warm_entrypoint(). This results in EnIA bit [31] in SCTLR_EL3 not being set and pointer authentication disabled after CPU wake-up event. Fixes ARM-software/tf-issues#684 Change-Id: I27a67804764dfba2a6d72ca119ca2bcff4f536d6 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge pull request #1870 from thloh85-intel/s10_mmcDimitris Papastamos2019-03-080-0/+0
|\ \ | | | | | | plat: intel: Add MMC OCR voltage information for initialization
| * | plat: intel: Add MMC OCR voltage information for initializationTien Hock, Loh2019-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | | Merge pull request #1863 from thloh85-intel/mmc_fixesDimitris Papastamos2019-03-083-4/+8
|\ \ \ | | | | | | | | drivers: mmc: Fix some issues with MMC stack
| * | | plat: intel: Add MMC OCR voltage information for initializationTien Hock, Loh2019-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
| * | | drivers: mmc: Fix some issues with MMC stackTien Hock, Loh2019-03-072-4/+7
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed - ACMD41 needs to send voltage information in initialization, otherwise the command is a query, thus will not initialize the controller - when checking device state, retry until the retries counter goes to zero before failing Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | | Merge pull request #1864 from hadi-asyrafi/mailbox_fixDimitris Papastamos2019-03-071-5/+10
|\ \ \ | | | | | | | | intel: Mailbox service un-accessible
| * | | intel: Mailbox service un-accessibleMuhammad Hadi Asyrafi Abdul Halim2019-03-071-5/+10
| | |/ | |/| | | | | | | | | | | | | Change map region for device 2 from non-secure to secure Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
* | | Merge pull request #1862 from thloh85-intel/s10_bl2Dimitris Papastamos2019-03-071-1/+2
|\ \ \ | | | | | | | | plat: intel: Improve ECC scrubbing performance
| * | | plat: intel: Improve ECC scrubbing performanceTien Hock, Loh2019-03-071-1/+2
| | |/ | |/| | | | | | | | | | | | | | | | We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | | Merge pull request #1868 from Yann-lms/zeromem_device_infoDimitris Papastamos2019-03-071-1/+2
|\ \ \ | | | | | | | | stm32mp1: zeromem device_info struct
| * | | stm32mp1: zeromem device_info structYann Gautier2019-03-071-1/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | The change of the structure highlighted the fact that all fields are not correctly initialized with zeroes. Replace the other memset in the function with zeromem, as it is faster. Change-Id: I27f45a64e34637f79fa519f486bf5936721ef396 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | Merge pull request #1869 from pbeesley-arm/pb/wiki-importSoby Mathew2019-03-0715-1/+1631
|\ \ \ | | | | | | | | Pb/wiki import
| * | | doc: Add and correct headings for imported filesPaul Beesley2019-03-074-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some files imported from the wiki are missing RST section headers and other files are using inconsistent characters for the same header level. Change-Id: I318c843f9bc8fb40074ef90827b9acac06463662 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
| * | | doc: Add missing CVE links to advisoriesPaul Beesley2019-03-076-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some security advisories did not contain a direct link to the CVE page on mitre.org. Change-Id: I80f8f27a25da3a76b564a3e49cafe5e253379f37 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
| * | | doc: Update links within imported wiki contentJoel Hutton2019-03-075-17/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch covers two changes: - Links that refer to GitHub are updated to point to the relevant content on trustedfirmware.org - Internal links between documents have been updated, with the required .rst suffix being added or due to a change in the relative locations of the files. Change-Id: Ibf87da7d2ece726d1c94a9b33a2bbc3129de7779 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com>
| * | | doc: Migrate a subset of the GitHub wiki contentJoel Hutton2019-03-0714-0/+1585
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the TF wiki being migrated from GitHub to trustedfirmware.org, some documents will be moved into the docs/ directory within the repository rather than remaining as external content. The appropriate action has been decided on a per-document basis. Change-Id: Id0f615f3418369256f30d2e34e354a115389d105 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | | Merge pull request #1860 from pbeesley-arm/pb/todo-cleanupDimitris Papastamos2019-03-071-1/+0
|\ \ \ | |/ / |/| | doc: Remove todo from example code
| * | Remove todo from example codePaul Beesley2019-03-061-1/+0
|/ / | | | | | | | | | | | | Keeping that in the docs is a bit untidy Change-Id: Ia95246208cee48df1536b4317a8c896ab2c84fc2 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Merge pull request #1847 from jts-arm/mbedtlsAntonio Niño Díaz2019-03-052-24/+20
|\ \ | | | | | | Remove Mbed TLS dependency from plat_bl_common.c
| * | Remove Mbed TLS dependency from plat_bl_common.cJohn Tsichritzis2019-02-282-24/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the shared Mbed TLS heap optimisation introduced in 6d01a463, common code files were depending on Mbed TLS specific headers. This dependency is now removed by moving the default, unoptimised heap implementation inside the Mbed TLS specific files. Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | Merge pull request #1855 from dp-arm/dp/ssbsAntonio Niño Díaz2019-03-052-2/+3
|\ \ \ | | | | | | | | Ensure proper ID register is checked for feature detection
| * | | Ensure proper ID register is checked for feature detectionDimitris Papastamos2019-03-042-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSBS support is determined by checking ID_AA64PFR1_EL1 and not ID_AA64PFR0_EL1. Fixes ARM-Software/tf-issues#679 Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | | | Merge pull request #1853 from vwadekar/dummy_io_storageAntonio Niño Díaz2019-03-054-3/+30
|\ \ \ \ | | | | | | | | | | Tegra: dummy support for the io_storage backend
| * | | | Tegra: dummy support for the io_storage backendVarun Wadekar2019-03-014-3/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides dummy macros and platform files to compile the io_storage driver backend. This patch is necessary to remove the "--unresolved=el3_panic" linker flag from Tegra's makefiles and allow us to revert this workaround, previously suggested by the ARM toolchain team. The "--unresolved=el3_panic" flag actually was a big hammer that allowed Tegra platforms to work with armlink previously but it masks legit errors with the code as well. Change-Id: I0421d35657823215229f84231896b84167f90548 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Merge pull request #1854 from marex/arm/master/atf-v2.0.1Antonio Niño Díaz2019-03-0518-23/+407
|\ \ \ \ \ | | | | | | | | | | | | Arm/master/atf v2.0.1
| * | | | | rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCBMarek Vasut2019-03-044-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the GPIO5 09 pin as input on the ULCB board by default, since the pin is routed on the expansion connector and not connected to anything by default. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | | | | rcar_gen3: Add M3-W 3.0 supportMarek Vasut2019-03-0413-23/+388
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | | | | rcar_gen3: Add myself as a maintainerMarek Vasut2019-03-041-0/+3
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | Add myself into the maintainers file to make Jorge's life easier. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | | | Merge pull request #1852 from sandrine-bailleux-arm/sb/fix-intmgt-docAntonio Niño Díaz2019-03-041-53/+68
|\ \ \ \ \ | |/ / / / |/| | | | Minor fixes in the interrupt framework design guide
| * | | | Doc: Fix internal links in interrupt framework design guideSandrine Bailleux2019-03-011-49/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the sections numbers have been incorrect since the document structure has changed. Using references to sections rather than hard-coded section numbers fixes the issue while making it more future-proof to updates. Change-Id: I80f5ab6a55a0073b1562a02ce2c9ec7d67cddfff Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
| * | | | Doc: Fix a formatting glitchSandrine Bailleux2019-03-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While converting the interrupt framework design document from Markdown to reStructuredText format, see commit 6f6257476754 ("Convert documentation to reStructuredText"), the structure of the document was changed and one of the titles got lost. Fix that. Change-Id: Ib3e6c1f9f01f16108fde3b89ceb624bd54049d2f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | | | Merge pull request #1844 from chandnich/rename_sgiclarkAntonio Niño Díaz2019-03-043-17/+17
|\ \ \ \ \ | | | | | | | | | | | | css/sgi: replace all uses of Clark with new product names
| * | | | | css/sgi: replace all uses of Clark with new product namesChandni Cherukuri2019-02-283-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and 'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product names Change-Id: Ib8136e421b1a46da1e5df58c6b1432d5c78d279b Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | | | Merge pull request #1851 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz2019-03-042-4/+6
|\ \ \ \ \ \ | | | | | | | | | | | | | | Correctly check for support of Address Authentication
| * | | | | | Correctly check for support of Address AuthenticationAntonio Nino Diaz2019-03-012-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for both IMPLEMENTATION_DEFINED and Architected algorithms of Address Authentication. Change-Id: I209dcc6087172cfef7baf8d09e0454628f02cbd0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | | | | Merge pull request #1837 from spencercw/masterAntonio Niño Díaz2019-03-042-0/+10
|\ \ \ \ \ \ \ | |_|_|_|/ / / |/| | | | | | imx: Configure CAAM job rings master ID for i.MX8MQ
| * | | | | | imx: Configure CAAM job rings master ID for i.MX8MQChris Spencer2019-02-222-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For i.MX8MQ B0 revision the default configuration of JRaMID is not valid to allow the kernel to use the CAAM job rings. This patch sets the master ID of the Cortex A in the JRaMID registers. Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
* | | | | | | Merge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metricAntonio Niño Díaz2019-03-011-75/+99
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Reduce cyclomatic complexity metric
| * | | | | | | xlat_tables_v2: find VA/idx with helper functions.David Pu2019-02-281-26/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces 2 helper functions 'xlat_tables_find_start_va' and 'xlat_tables_va_to_index' to find the first VA and table index affected by the specified mmap region. it reduces code duplication and cyclomatic code complexity in xlat_tables_map/unmap_region functions. Cyclomatic complexity calculated using 'Coverity' fixes arm-software/tf-issues#673 Signed-off-by: David Pu <dpu@nvidia.com>
| * | | | | | | xlat_tables_v2: get unmap action type with helper function.David Pu2019-02-281-49/+64
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces helper function 'xlat_tables_unmap_region_action' to get the required action type from given arguments when unmapping the specified region. it reduces cyclomatic code complexity in xlat_tables_unmap_region function. Cyclomatic complexity calculated using 'Coverity' fixes arm-software/tf-issues#673 Signed-off-by: David Pu <dpu@nvidia.com>
* | | | | | | Merge pull request #1815 from Anson-Huang/gicAntonio Niño Díaz2019-03-011-0/+21
|\ \ \ \ \ \ \ | |_|_|_|/ / / |/| | | | | | gic: make sure ProcessorSleep bit clear successfully
| * | | | | | imx: make sure GIC redistributor is awake before initializationAnson Huang2019-03-011-0/+21
| | |_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* | | | | | Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz2019-03-0110-7/+411
|\ \ \ \ \ \ | | | | | | | | | | | | | | Tegra scatter file support
| * | | | | | Tegra: Support for scatterfile for the BL31 imageVarun Wadekar2019-02-2710-7/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 08:10:52 +0000