diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/nvidia/tegra/include/t194/tegra_def.h | 3 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_memctrl.c | 33 |
2 files changed, 35 insertions, 1 deletions
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a41c0cd7e..ca2a6ed4f 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -73,6 +73,9 @@ #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) +#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) +#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) + /* Video Memory carveout configuration registers */ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_LO U(0x648) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 044a4512f..75705cff1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -638,4 +638,35 @@ static tegra_mc_settings_t tegra194_mc_settings = { tegra_mc_settings_t *tegra_get_mc_settings(void) { return &tegra194_mc_settings; -}
\ No newline at end of file +} + +/******************************************************************************* + * Handler to program the scratch registers with TZDRAM settings for the + * resume firmware + ******************************************************************************/ +void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) +{ + /* + * Check if the carveout register is already locked, if locked + * no TZDRAM setup + */ + if ((tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0) & + SECURITY_CFG_WRITE_ACCESS_BIT) == SECURITY_CFG_WRITE_ACCESS_BIT) { + + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring TrustZone DRAM Memory Carveout\n"); + + tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); + tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); + tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); + + /* + * MCE propagates the security configuration values across the + * CCPLEX. + */ + (void)mce_update_gsc_tzdram(); + } +} |