101 files changed, 1878 insertions, 455 deletions

diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk
deleted file mode 100644
index 1e2756734..000000000
--- a/plat/marvell/a3700/common/a3700_common.mk
+++ /dev/null
@@ -1,171 +0,0 @@
-#
-# Copyright (C) 2018 Marvell International Ltd.
-#
-# SPDX-License-Identifier:	BSD-3-Clause
-# https://spdx.org/licenses
-#
-
-MARVELL_PLAT_BASE		:= plat/marvell
-MARVELL_PLAT_INCLUDE_BASE	:= include/plat/marvell
-PLAT_FAMILY			:= a3700
-PLAT_FAMILY_BASE		:= $(MARVELL_PLAT_BASE)/$(PLAT_FAMILY)
-PLAT_INCLUDE_BASE		:= $(MARVELL_PLAT_INCLUDE_BASE)/$(PLAT_FAMILY)
-PLAT_COMMON_BASE		:= $(PLAT_FAMILY_BASE)/common
-MARVELL_DRV_BASE		:= drivers/marvell
-MARVELL_COMMON_BASE		:= $(MARVELL_PLAT_BASE)/common
-HANDLE_EA_EL3_FIRST		:= 1
-
-include $(MARVELL_PLAT_BASE)/marvell.mk
-
-#*********** A3700 *************
-DOIMAGEPATH	:= $(WTP)
-DOIMAGETOOL	:= $(DOIMAGEPATH)/wtptp/linux/tbb_linux
-
-ifeq ($(MARVELL_SECURE_BOOT),1)
-DOIMAGE_CFG	:= $(DOIMAGEPATH)/atf-tim.txt
-IMAGESPATH	:= $(DOIMAGEPATH)/tim/trusted
-
-TIMNCFG		:= $(DOIMAGEPATH)/atf-timN.txt
-TIMNSIG		:= $(IMAGESPATH)/timnsign.txt
-TIM2IMGARGS	:= -i $(DOIMAGE_CFG) -n $(TIMNCFG)
-TIMN_IMAGE	:= $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
-else #MARVELL_SECURE_BOOT
-DOIMAGE_CFG	:= $(DOIMAGEPATH)/atf-ntim.txt
-IMAGESPATH	:= $(DOIMAGEPATH)/tim/untrusted
-TIM2IMGARGS	:= -i $(DOIMAGE_CFG)
-endif #MARVELL_SECURE_BOOT
-
-TIMBUILD	:= $(DOIMAGEPATH)/script/buildtim.sh
-TIM2IMG		:= $(DOIMAGEPATH)/script/tim2img.pl
-
-# WTMI_IMG is used to specify the customized RTOS image running over
-# Service CPU (CM3 processor). By the default, it points to a
-# baremetal binary of fuse programming in A3700_utils.
-WTMI_IMG	:= $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
-
-# WTMI_SYSINIT_IMG is used for the system early initialization,
-# such as AVS settings, clock-tree setup and dynamic DDR PHY training.
-# After the initialization is done, this image will be wiped out
-# from the memory and CM3 will continue with RTOS image or other application.
-WTMI_SYSINIT_IMG	:= $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin
-
-# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
-# and sys-init image (WTMI_SYSINIT_IMG).
-WTMI_MULTI_IMG		:= $(DOIMAGEPATH)/wtmi/build/wtmi.bin
-
-WTMI_ENC_IMG		:= $(DOIMAGEPATH)/wtmi/build/wtmi-enc.bin
-BUILD_UART		:= uart-images
-
-SRCPATH			:= $(dir $(BL33))
-
-CLOCKSPRESET		?= CPU_800_DDR_800
-
-DDR_TOPOLOGY		?= 0
-
-BOOTDEV			?= SPINOR
-PARTNUM			?= 0
-
-TIM_IMAGE		:= $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
-TIMBLDARGS		:= $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
-				$(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
-TIMBLDUARTARGS		:= $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
-				$(DDR_TOPOLOGY) 0 0 $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 0
-DOIMAGE_FLAGS		:= -r $(DOIMAGE_CFG) -v -D
-
-# GICV3
-$(eval $(call add_define,CONFIG_GICV3))
-
-# CCI-400
-$(eval $(call add_define,USE_CCI))
-
-MARVELL_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
-				drivers/arm/gic/v3/gicv3_main.c		\
-				drivers/arm/gic/v3/gicv3_helpers.c	\
-				drivers/arm/gic/v3/arm_gicv3_common.c	\
-				plat/common/plat_gicv3.c		\
-				drivers/arm/gic/v3/gic500.c
-
-PLAT_INCLUDES		:=	-I$(PLAT_FAMILY_BASE)/$(PLAT)		\
-				-I$(PLAT_COMMON_BASE)/include		\
-				-I$(PLAT_INCLUDE_BASE)/common		\
-				-I$(MARVELL_DRV_BASE)			\
-				-I$/drivers/arm/gic/common/
-
-PLAT_BL_COMMON_SOURCES	:=	$(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
-				$(MARVELL_COMMON_BASE)/marvell_cci.c	   \
-				$(MARVELL_DRV_BASE)/uart/a3700_console.S
-
-BL1_SOURCES		+=	$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
-				lib/cpus/aarch64/cortex_a53.S
-
-BL31_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
-
-MARVELL_DRV		:=	$(MARVELL_DRV_BASE)/comphy/phy-comphy-3700.c
-
-BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
-				$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
-				$(PLAT_COMMON_BASE)/plat_pm.c		\
-				$(PLAT_COMMON_BASE)/dram_win.c		\
-				$(PLAT_COMMON_BASE)/io_addr_dec.c	\
-				$(PLAT_COMMON_BASE)/marvell_plat_config.c     \
-				$(PLAT_COMMON_BASE)/a3700_ea.c		\
-				$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
-				$(MARVELL_COMMON_BASE)/marvell_ddr_info.c	\
-				$(MARVELL_COMMON_BASE)/marvell_gicv3.c	\
-				$(MARVELL_GIC_SOURCES)			\
-				drivers/arm/cci/cci.c			\
-				$(BL31_PORTING_SOURCES)			\
-				$(PLAT_COMMON_BASE)/a3700_sip_svc.c	\
-				$(MARVELL_DRV)
-
-mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL}
-	$(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
-	$(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
-	$(shell truncate -s %4 ${BUILD_PLAT}/${BOOT_IMAGE})
-	$(shell truncate -s %4 $(WTMI_IMG))
-	@echo
-	@echo "Building uart images"
-	$(TIMBUILD) $(TIMBLDUARTARGS)
-	@sed -i 's|WTMI_IMG|$(WTMI_MULTI_IMG)|1' $(DOIMAGE_CFG)
-	@sed -i 's|BOOT_IMAGE|$(BUILD_PLAT)/$(BOOT_IMAGE)|1' $(DOIMAGE_CFG)
-ifeq ($(MARVELL_SECURE_BOOT),1)
-	@sed -i 's|WTMI_IMG|$(WTMI_MULTI_IMG)|1' $(TIMNCFG)
-	@sed -i 's|BOOT_IMAGE|$(BUILD_PLAT)/$(BOOT_IMAGE)|1' $(TIMNCFG)
-endif
-	$(DOIMAGETOOL) $(DOIMAGE_FLAGS)
-	@if [ -e "$(TIMNCFG)" ]; then $(DOIMAGETOOL) -r $(TIMNCFG); fi
-	@rm -rf $(BUILD_PLAT)/$(BUILD_UART)*
-	@mkdir $(BUILD_PLAT)/$(BUILD_UART)
-	@mv -t $(BUILD_PLAT)/$(BUILD_UART) $(TIM_IMAGE) $(DOIMAGE_CFG) $(TIMN_IMAGE) $(TIMNCFG)
-	@find . -name "*_h.*" |xargs cp -ut $(BUILD_PLAT)/$(BUILD_UART)
-	@mv $(subst .bin,_h.bin,$(WTMI_MULTI_IMG)) $(BUILD_PLAT)/$(BUILD_UART)/wtmi_h.bin
-	@tar czf $(BUILD_PLAT)/$(BUILD_UART).tgz -C $(BUILD_PLAT) ./$(BUILD_UART)
-	@echo
-	@echo "Building flash image"
-	$(TIMBUILD) $(TIMBLDARGS)
-	sed -i 's|WTMI_IMG|$(WTMI_MULTI_IMG)|1' $(DOIMAGE_CFG)
-	sed -i 's|BOOT_IMAGE|$(BUILD_PLAT)/$(BOOT_IMAGE)|1' $(DOIMAGE_CFG)
-ifeq ($(MARVELL_SECURE_BOOT),1)
-	@sed -i 's|WTMI_IMG|$(WTMI_MULTI_IMG)|1' $(TIMNCFG)
-	@sed -i 's|BOOT_IMAGE|$(BUILD_PLAT)/$(BOOT_IMAGE)|1' $(TIMNCFG)
-	@echo -e "\n\t=======================================================\n";
-	@echo -e "\t  Secure boot. Encrypting wtmi and boot-image \n";
-	@echo -e "\t=======================================================\n";
-	@truncate -s %16 $(WTMI_MULTI_IMG)
-	@openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) \
-	-out $(WTMI_ENC_IMG) \
-	-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-	-iv `cat $(IMAGESPATH)/iv.txt` -p
-	@truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE);
-	@openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \
-	-out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \
-	-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-	-iv `cat $(IMAGESPATH)/iv.txt` -p
-endif
-	$(DOIMAGETOOL) $(DOIMAGE_FLAGS)
-	@if [ -e "$(TIMNCFG)" ]; then $(DOIMAGETOOL) -r $(TIMNCFG); fi
-	@if [ "$(MARVELL_SECURE_BOOT)" = "1" ]; then sed -i 's|$(WTMI_MULTI_IMG)|$(WTMI_ENC_IMG)|1;s|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1;' $(TIMNCFG); fi
-	$(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
-	@mv -t $(BUILD_PLAT) $(TIM_IMAGE) $(DOIMAGE_CFG) $(TIMN_IMAGE) $(TIMNCFG) $(WTMI_IMG) $(WTMI_SYSINIT_IMG) $(WTMI_MULTI_IMG)
-	@if [ "$(MARVELL_SECURE_BOOT)" = "1" ]; then mv -t $(BUILD_PLAT) $(WTMI_ENC_IMG) OtpHash.txt; fi
-	@find . -name "*.txt" | grep -E "CSK[[:alnum:]]_KeyHash.txt|Tim_msg.txt|TIMHash.txt" | xargs rm -f
diff --git a/plat/marvell/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/a8k/common/aarch64/plat_arch_config.c
deleted file mode 100644
index 06dc84115..000000000
--- a/plat/marvell/a8k/common/aarch64/plat_arch_config.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier:     BSD-3-Clause
- * https://spdx.org/licenses
- */
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/marvell/cache_llc.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-
-#define CCU_HTC_ASET			(MVEBU_CCU_BASE(MVEBU_AP0) + 0x264)
-#define MVEBU_IO_AFFINITY		(0xF00)
-
-
-static void plat_enable_affinity(void)
-{
-	int cluster_id;
-	int affinity;
-
-	/* set CPU Affinity */
-	cluster_id = plat_my_core_pos() / PLAT_MARVELL_CLUSTER_CORE_COUNT;
-	affinity = (MVEBU_IO_AFFINITY | (1 << cluster_id));
-	mmio_write_32(CCU_HTC_ASET, affinity);
-
-	/* set barier */
-	isb();
-}
-
-void marvell_psci_arch_init(int die_index)
-{
-#if LLC_ENABLE
-	/* check if LLC is in exclusive mode
-	 * as L2 is configured to UniqueClean eviction
-	 * (in a8k reset handler)
-	 */
-	if (llc_is_exclusive(0) == 0)
-		ERROR("LLC should be configured to exclusice mode\n");
-#endif
-
-	/* Enable Affinity */
-	plat_enable_affinity();
-}
diff --git a/plat/marvell/a3700/a3700/board/pm_src.c b/plat/marvell/armada/a3k/a3700/board/pm_src.c
index d6eca5d16..d6eca5d16 100644
--- a/plat/marvell/a3700/a3700/board/pm_src.c
+++ b/plat/marvell/armada/a3k/a3700/board/pm_src.c
diff --git a/plat/marvell/a3700/a3700/mvebu_def.h b/plat/marvell/armada/a3k/a3700/mvebu_def.h
index dad1085f8..dad1085f8 100644
--- a/plat/marvell/a3700/a3700/mvebu_def.h
+++ b/plat/marvell/armada/a3k/a3700/mvebu_def.h
diff --git a/plat/marvell/a3700/a3700/plat_bl31_setup.c b/plat/marvell/armada/a3k/a3700/plat_bl31_setup.c
index 6862a8670..6862a8670 100644
--- a/plat/marvell/a3700/a3700/plat_bl31_setup.c
+++ b/plat/marvell/armada/a3k/a3700/plat_bl31_setup.c
diff --git a/plat/marvell/a3700/a3700/platform.mk b/plat/marvell/armada/a3k/a3700/platform.mk
index 4f7ac08c4..050af4199 100644
--- a/plat/marvell/a3700/a3700/platform.mk
+++ b/plat/marvell/armada/a3k/a3700/platform.mk
@@ -5,6 +5,6 @@
 # https://spdx.org/licenses
 #
 
-include plat/marvell/a3700/common/a3700_common.mk
+include plat/marvell/armada/a3k/common/a3700_common.mk
 
-include plat/marvell/common/marvell_common.mk
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
new file mode 100644
index 000000000..8775e8934
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -0,0 +1,233 @@
+#
+# Copyright (C) 2018-2021 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	BSD-3-Clause
+# https://spdx.org/licenses
+#
+
+MARVELL_PLAT_BASE		:= plat/marvell/armada
+MARVELL_PLAT_INCLUDE_BASE	:= include/plat/marvell/armada
+PLAT_FAMILY			:= a3k
+PLAT_FAMILY_BASE		:= $(MARVELL_PLAT_BASE)/$(PLAT_FAMILY)
+PLAT_INCLUDE_BASE		:= $(MARVELL_PLAT_INCLUDE_BASE)/$(PLAT_FAMILY)
+PLAT_COMMON_BASE		:= $(PLAT_FAMILY_BASE)/common
+MARVELL_DRV_BASE		:= drivers/marvell
+MARVELL_COMMON_BASE		:= $(MARVELL_PLAT_BASE)/common
+HANDLE_EA_EL3_FIRST		:= 1
+
+include plat/marvell/marvell.mk
+
+#*********** A3700 *************
+
+# GICV3
+$(eval $(call add_define,CONFIG_GICV3))
+
+# CCI-400
+$(eval $(call add_define,USE_CCI))
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+MARVELL_GIC_SOURCES	:=	${GICV3_SOURCES}			\
+				plat/common/plat_gicv3.c
+
+PLAT_INCLUDES		:=	-I$(PLAT_FAMILY_BASE)/$(PLAT)		\
+				-I$(PLAT_COMMON_BASE)/include		\
+				-I$(PLAT_INCLUDE_BASE)/common		\
+				-I$(MARVELL_DRV_BASE)			\
+				-I$/drivers/arm/gic/common/
+
+PLAT_BL_COMMON_SOURCES	:=	$(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
+				$(MARVELL_DRV_BASE)/uart/a3700_console.S
+
+BL1_SOURCES		+=	$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
+				lib/cpus/aarch64/cortex_a53.S
+
+BL31_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
+
+MARVELL_DRV		:=	$(MARVELL_DRV_BASE)/comphy/phy-comphy-3700.c
+
+BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
+				$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
+				$(PLAT_COMMON_BASE)/plat_cci.c		\
+				$(PLAT_COMMON_BASE)/plat_pm.c		\
+				$(PLAT_COMMON_BASE)/dram_win.c		\
+				$(PLAT_COMMON_BASE)/io_addr_dec.c	\
+				$(PLAT_COMMON_BASE)/marvell_plat_config.c     \
+				$(PLAT_COMMON_BASE)/a3700_ea.c		\
+				$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
+				$(MARVELL_COMMON_BASE)/marvell_cci.c	\
+				$(MARVELL_COMMON_BASE)/marvell_ddr_info.c	\
+				$(MARVELL_COMMON_BASE)/marvell_gicv3.c	\
+				$(MARVELL_GIC_SOURCES)			\
+				drivers/arm/cci/cci.c			\
+				$(BL31_PORTING_SOURCES)			\
+				$(PLAT_COMMON_BASE)/a3700_sip_svc.c	\
+				$(MARVELL_DRV)
+
+ifeq ($(CM3_SYSTEM_RESET),1)
+BL31_SOURCES		+=	$(PLAT_COMMON_BASE)/cm3_system_reset.c
+endif
+
+ifdef WTP
+
+$(if $(wildcard $(value WTP)/*),,$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' directory does not exist"))
+$(if $(shell test -s "$(value WTP)/branch.txt" || git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid Marvell a3700_utils release tarball nor git repository"))
+
+DOIMAGEPATH	:= $(WTP)
+DOIMAGETOOL	:= $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
+
+BUILD_UART	:= uart-images
+UART_IMAGE	:= $(BUILD_UART).tgz.bin
+
+ifeq ($(MARVELL_SECURE_BOOT),1)
+DOIMAGE_CFG	:= $(BUILD_PLAT)/atf-tim.txt
+DOIMAGEUART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-tim.txt
+IMAGESPATH	:= $(DOIMAGEPATH)/tim/trusted
+TIMNCFG		:= $(BUILD_PLAT)/atf-timN.txt
+TIMNUARTCFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-timN.txt
+TIMNSIG		:= $(IMAGESPATH)/timnsign.txt
+TIM2IMGARGS	:= -i $(DOIMAGE_CFG) -n $(TIMNCFG)
+TIMN_IMAGE	:= $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
+else #MARVELL_SECURE_BOOT
+DOIMAGE_CFG	:= $(BUILD_PLAT)/atf-ntim.txt
+DOIMAGEUART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-ntim.txt
+IMAGESPATH	:= $(DOIMAGEPATH)/tim/untrusted
+TIM2IMGARGS	:= -i $(DOIMAGE_CFG)
+endif #MARVELL_SECURE_BOOT
+
+TIMBUILD	:= $(DOIMAGEPATH)/script/buildtim.sh
+TIM2IMG		:= $(DOIMAGEPATH)/script/tim2img.pl
+TIMDDRTOOL	:= $(DOIMAGEPATH)/tim/ddr/ddr_tool
+
+$(TIMBUILD): $(TIMDDRTOOL)
+
+# WTMI_IMG is used to specify the customized RTOS image running over
+# Service CPU (CM3 processor). By the default, it points to a
+# baremetal binary of fuse programming in A3700_utils.
+WTMI_IMG	:= $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
+
+# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
+# and sys-init image.
+WTMI_MULTI_IMG		:= $(DOIMAGEPATH)/wtmi/build/wtmi.bin
+
+WTMI_ENC_IMG		:= wtmi-enc.bin
+
+SRCPATH			:= $(dir $(BL33))
+
+CLOCKSPRESET		?= CPU_800_DDR_800
+
+DDR_TOPOLOGY		?= 0
+
+BOOTDEV			?= SPINOR
+PARTNUM			?= 0
+
+TIM_IMAGE		:= $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
+TIMBLDARGS		:= $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
+				$(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
+TIMBLDUARTARGS		:= $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
+				$(DDR_TOPOLOGY) 0 0 $(DOIMAGEUART_CFG) $(TIMNUARTCFG) $(TIMNSIG) 0
+
+CRYPTOPP_LIBDIR		?= $(CRYPTOPP_PATH)
+CRYPTOPP_INCDIR		?= $(CRYPTOPP_PATH)
+
+$(DOIMAGETOOL): FORCE
+	$(if $(CRYPTOPP_LIBDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_LIBDIR. Please set CRYPTOPP_PATH or CRYPTOPP_LIBDIR to point to the right directory"))
+	$(if $(CRYPTOPP_INCDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_INCDIR. Please set CRYPTOPP_PATH or CRYPTOPP_INCDIR to point to the right directory"))
+	$(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
+	$(if $(wildcard $(CRYPTOPP_INCDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_INCDIR' was set to '$(CRYPTOPP_INCDIR)', but '$(CRYPTOPP_INCDIR)' does not exist"))
+ifdef CRYPTOPP_PATH
+	$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
+endif
+	$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
+
+$(WTMI_MULTI_IMG): FORCE
+	$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
+
+$(BUILD_PLAT)/wtmi.bin: $(WTMI_MULTI_IMG)
+	$(Q)cp -a $(WTMI_MULTI_IMG) $(BUILD_PLAT)/wtmi.bin
+
+$(TIMDDRTOOL): FORCE
+	$(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for ddr tool requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
+	$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
+	$(if $(shell test -s "$(value MV_DDR_PATH)/branch.txt" || git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid Marvell mv_ddr release tarball nor git repository"))
+	$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
+
+$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(DOIMAGETOOL) $(TIMBUILD) $(TIMDDRTOOL)
+	@$(ECHO_BLANK_LINE)
+	@echo "Building uart images"
+	$(Q)mkdir -p $(BUILD_PLAT)/$(BUILD_UART)
+	$(Q)cp -a $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/$(BUILD_UART)/wtmi.bin
+	$(Q)cp -a $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/$(BUILD_UART)/$(BOOT_IMAGE)
+	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TIMBUILD) $(TIMBLDUARTARGS)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(DOIMAGEUART_CFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(DOIMAGEUART_CFG)
+ifeq ($(MARVELL_SECURE_BOOT),1)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMNUARTCFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMNUARTCFG)
+endif
+	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(DOIMAGETOOL) -r $(DOIMAGEUART_CFG) -v -D
+ifeq ($(MARVELL_SECURE_BOOT),1)
+	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(DOIMAGETOOL) -r $(TIMNUARTCFG)
+endif
+	$(Q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(BUILD_UART)/$(TIM_IMAGE) $(BUILD_UART)/wtmi_h.bin $(BUILD_UART)/boot-image_h.bin
+	@$(ECHO_BLANK_LINE)
+	@echo "Built $@ successfully"
+	@$(ECHO_BLANK_LINE)
+
+$(BUILD_PLAT)/$(FLASH_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(DOIMAGETOOL) $(TIMBUILD) $(TIMDDRTOOL) $(TIM2IMG)
+	@$(ECHO_BLANK_LINE)
+	@echo "Building flash image"
+	$(Q)cd $(BUILD_PLAT) && $(TIMBUILD) $(TIMBLDARGS)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(DOIMAGE_CFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(DOIMAGE_CFG)
+ifeq ($(MARVELL_SECURE_BOOT),1)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMNCFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMNCFG)
+	@$(ECHO_BLANK_LINE)
+	@echo "=======================================================";
+	@echo "  Secure boot. Encrypting wtmi and boot-image";
+	@echo "=======================================================";
+	@$(ECHO_BLANK_LINE)
+	$(Q)cp $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/wtmi-align.bin
+	$(Q)truncate -s %16 $(BUILD_PLAT)/wtmi-align.bin
+	$(Q)openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \
+	-out $(BUILD_PLAT)/$(WTMI_ENC_IMG) \
+	-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
+	-iv `cat $(IMAGESPATH)/iv.txt` -p
+	$(Q)truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE);
+	$(Q)openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \
+	-out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \
+	-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
+	-iv `cat $(IMAGESPATH)/iv.txt` -p
+endif
+	$(Q)cd $(BUILD_PLAT) && $(DOIMAGETOOL) -r $(DOIMAGE_CFG) -v -D
+ifeq ($(MARVELL_SECURE_BOOT),1)
+	$(Q)cd $(BUILD_PLAT) && $(DOIMAGETOOL) -r $(TIMNCFG)
+	$(Q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMNCFG)
+	$(Q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMNCFG)
+endif
+	$(Q)cd $(BUILD_PLAT) && $(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
+	@$(ECHO_BLANK_LINE)
+	@echo "Built $@ successfully"
+	@$(ECHO_BLANK_LINE)
+
+clean realclean distclean: mrvl_clean
+
+.PHONY: mrvl_clean
+mrvl_clean:
+	-$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) clean
+	-$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
+ifdef CRYPTOPP_PATH
+	-$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile clean
+endif
+
+else # WTP
+
+$(BUILD_PLAT)/$(UART_IMAGE) $(BUILD_PLAT)/$(FLASH_IMAGE):
+	$(error "Platform '${PLAT}' for target '$@' requires WTP. Please set WTP to point to the right directory")
+
+endif # WTP
+
+.PHONY: mrvl_uart
+mrvl_uart: $(BUILD_PLAT)/$(UART_IMAGE)
diff --git a/plat/marvell/a3700/common/a3700_ea.c b/plat/marvell/armada/a3k/common/a3700_ea.c
index dd46beb55..dd46beb55 100644
--- a/plat/marvell/a3700/common/a3700_ea.c
+++ b/plat/marvell/armada/a3k/common/a3700_ea.c
diff --git a/plat/marvell/a3700/common/a3700_sip_svc.c b/plat/marvell/armada/a3k/common/a3700_sip_svc.c
index e8ac5fc08..e8ac5fc08 100644
--- a/plat/marvell/a3700/common/a3700_sip_svc.c
+++ b/plat/marvell/armada/a3k/common/a3700_sip_svc.c
diff --git a/plat/marvell/a3700/common/aarch64/a3700_common.c b/plat/marvell/armada/a3k/common/aarch64/a3700_common.c
index 63512853c..63512853c 100644
--- a/plat/marvell/a3700/common/aarch64/a3700_common.c
+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_common.c
diff --git a/plat/marvell/a3700/common/aarch64/plat_helpers.S b/plat/marvell/armada/a3k/common/aarch64/plat_helpers.S
index 90d76f08e..90d76f08e 100644
--- a/plat/marvell/a3700/common/aarch64/plat_helpers.S
+++ b/plat/marvell/armada/a3k/common/aarch64/plat_helpers.S
diff --git a/plat/marvell/armada/a3k/common/cm3_system_reset.c b/plat/marvell/armada/a3k/common/cm3_system_reset.c
new file mode 100644
index 000000000..548ff5168
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/cm3_system_reset.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2020 Marek Behun, CZ.NIC
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mvebu_def.h>
+
+/* Cortex-M3 Secure Processor Mailbox Registers */
+#define MVEBU_RWTM_PARAM0_REG			(MVEBU_RWTM_REG_BASE)
+#define MVEBU_RWTM_CMD_REG			(MVEBU_RWTM_REG_BASE + 0x40)
+#define MVEBU_RWTM_HOST_INT_RESET_REG		(MVEBU_RWTM_REG_BASE + 0xC8)
+#define MVEBU_RWTM_HOST_INT_MASK_REG		(MVEBU_RWTM_REG_BASE + 0xCC)
+#define MVEBU_RWTM_HOST_INT_SP_COMPLETE		BIT(0)
+
+#define MVEBU_RWTM_REBOOT_CMD		0x0009
+#define MVEBU_RWTM_REBOOT_MAGIC		0xDEADBEEF
+
+static inline bool rwtm_completed(void)
+{
+	return (mmio_read_32(MVEBU_RWTM_HOST_INT_RESET_REG) &
+		MVEBU_RWTM_HOST_INT_SP_COMPLETE) != 0;
+}
+
+static bool rwtm_wait(int ms)
+{
+	while (ms && !rwtm_completed()) {
+		mdelay(1);
+		--ms;
+	}
+
+	return rwtm_completed();
+}
+
+void cm3_system_reset(void)
+{
+	int tries = 5;
+
+	for (; tries > 0; --tries) {
+		mmio_clrbits_32(MVEBU_RWTM_HOST_INT_RESET_REG,
+				MVEBU_RWTM_HOST_INT_SP_COMPLETE);
+
+		mmio_write_32(MVEBU_RWTM_PARAM0_REG, MVEBU_RWTM_REBOOT_MAGIC);
+		mmio_write_32(MVEBU_RWTM_CMD_REG, MVEBU_RWTM_REBOOT_CMD);
+
+		if (rwtm_wait(10)) {
+			break;
+		}
+
+		mdelay(100);
+	}
+
+	/* If we reach here, the command is not implemented. */
+	ERROR("System reset command not implemented in WTMI firmware!\n");
+}
diff --git a/plat/marvell/a3700/common/dram_win.c b/plat/marvell/armada/a3k/common/dram_win.c
index 694f6d480..e89f29504 100644
--- a/plat/marvell/a3700/common/dram_win.c
+++ b/plat/marvell/armada/a3k/common/dram_win.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2021 Marvell International Ltd.
  *
  * SPDX-License-Identifier:	BSD-3-Clause
  * https://spdx.org/licenses
@@ -92,33 +92,35 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = {
 	},
 
 	/*
-	 * If total dram size is more than 2GB, now there is only one case - 4GB
-	 *  dram; we will use below cpu windows configurations:
-	 *  - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as
-	 *    default;
-	 *  - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM;
-	 *    DDR window 0 is configured in tim header with 2GB size, no need to
-	 *    configure it again here;
+	 * If total DRAM size is more than 2GB, now there is only one case:
+	 * 4GB of DRAM; to better utilize address space (for maximization of
+	 * DRAM usage), we will use the configuration of CPU windows below:
+	 *  - Internal Regs and Boot ROM windows are kept as default;
+	 *  - CCI-400 is moved from its default address to another address
+	 *    (this is actually done even if DRAM size is not more than 2 GB,
+	 *     because the firmware is compiled with that address as a
+	 *     constant);
+	 *  - PCIe window is moved to another address;
+	 *  - Use 4 CPU decode windows for DRAM, which cover 3.75GB DRAM;
+	 *    DDR window 0 is configured in tim header with 2G B size, no need
+	 *    to configure it again here;
 	 *
-	 *	0xFFFFFFFF ---> |-----------------------|
-	 *			|	  Boot ROM	| 64KB
+	 *	0xFFFFFFFF ---> +-----------------------+
+	 *			|	 Boot ROM	| 64 KB
 	 *	0xFFF00000 ---> +-----------------------+
 	 *			:			:
-	 *	0xF0000000 ---> |-----------------------|
-	 *			|	  PCIE		| 128 MB
-	 *	0xE8000000 ---> |-----------------------|
-	 *			|	  DDR window 3	| 128 MB
-	 *	0xE0000000 ---> +-----------------------+
-	 *			:			:
-	 *	0xD8010000 ---> |-----------------------|
-	 *			|	  CCI Regs	| 64 KB
-	 *	0xD8000000 ---> +-----------------------+
-	 *			:			:
+	 *	0xFE010000 ---> +-----------------------+
+	 *			|	 CCI Regs	| 64 KB
+	 *	0xFE000000 ---> +-----------------------+
 	 *			:			:
+	 *	0xFA000000 ---> +-----------------------+
+	 *			|	 PCIE		| 128 MB
+	 *	0xF2000000 ---> +-----------------------+
+	 *			|	 DDR window 3	| 512 MB
 	 *	0xD2000000 ---> +-----------------------+
-	 *			|	 Internal Regs	| 32MB
+	 *			|	 Internal Regs	| 32 MB
 	 *	0xD0000000 ---> |-----------------------|
-	 *			 |	  DDR window 2	| 256 MB
+	 *			|	 DDR window 2	| 256 MB
 	 *	0xC0000000 ---> |-----------------------|
 	 *			|			|
 	 *			|	 DDR window 1	| 1 GB
@@ -155,14 +157,14 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = {
 						0xc0000000},
 		{CPU_WIN_ENABLED,
 			CPU_WIN_TARGET_DRAM,
-				0xe0000000,
-					0x08000000,
-						0xe0000000},
+				0xd2000000,
+					0x20000000,
+						0xd2000000},
 		{CPU_WIN_ENABLED,
 			CPU_WIN_TARGET_PCIE,
-				0xe8000000,
+				0xf2000000,
 					0x08000000,
-						0xe8000000},
+						0xf2000000},
 	},
 };
 
diff --git a/plat/marvell/a3700/common/include/a3700_plat_def.h b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
index c7f40adc3..83d95616b 100644
--- a/plat/marvell/a3700/common/include/a3700_plat_def.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2021 Marvell International Ltd.
  *
  * SPDX-License-Identifier:	BSD-3-Clause
  * https://spdx.org/licenses
@@ -41,8 +41,14 @@
 #define MVEBU_GICR_BASE			0x1D40000
 #define MVEBU_GICC_BASE			0x1D80000
 
-/* CCI-400 */
-#define MVEBU_CCI_BASE			0x8000000
+/*
+ * CCI-400 base address
+ * This address is absolute, not relative to MVEBU_REGS_BASE.
+ * This is not the default CCI base address (that would be 0xD8000000).
+ * Rather we remap CCI to this address to better utilize the address space.
+ * (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c)
+ */
+#define MVEBU_CCI_BASE			0xFE000000
 
 /*****************************************************************************
  * North and south bridge register base
@@ -119,4 +125,10 @@
  */
 #define MVEBU_COMPHY_REG_BASE			(MVEBU_REGS_BASE + 0x18300)
 
+/*****************************************************************************
+ * Cortex-M3 Secure Processor Mailbox constants
+ *****************************************************************************
+ */
+#define MVEBU_RWTM_REG_BASE			(MVEBU_REGS_BASE + 0xB0000)
+
 #endif /* A3700_PLAT_DEF_H */
diff --git a/plat/marvell/a3700/common/include/a3700_pm.h b/plat/marvell/armada/a3k/common/include/a3700_pm.h
index cc6cf436a..44dbb9f7d 100644
--- a/plat/marvell/a3700/common/include/a3700_pm.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_pm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2016 Marvell International Ltd.
+ * Copyright (C) 2016-2020 Marvell International Ltd.
  *
  * SPDX-License-Identifier:	BSD-3-Clause
  * https://spdx.org/licenses
@@ -48,4 +48,6 @@ struct pm_wake_up_src_config {
 
 struct pm_wake_up_src_config *mv_wake_up_src_config_get(void);
 
+void cm3_system_reset(void);
+
 #endif /* A3700_PM_H */
diff --git a/plat/marvell/a3700/common/include/ddr_info.h b/plat/marvell/armada/a3k/common/include/ddr_info.h
index 254f78c1b..254f78c1b 100644
--- a/plat/marvell/a3700/common/include/ddr_info.h
+++ b/plat/marvell/armada/a3k/common/include/ddr_info.h
diff --git a/plat/marvell/a3700/common/include/dram_win.h b/plat/marvell/armada/a3k/common/include/dram_win.h
index 26a013784..26a013784 100644
--- a/plat/marvell/a3700/common/include/dram_win.h
+++ b/plat/marvell/armada/a3k/common/include/dram_win.h
diff --git a/plat/marvell/a3700/common/include/io_addr_dec.h b/plat/marvell/armada/a3k/common/include/io_addr_dec.h
index 42ef30bc2..42ef30bc2 100644
--- a/plat/marvell/a3700/common/include/io_addr_dec.h
+++ b/plat/marvell/armada/a3k/common/include/io_addr_dec.h
diff --git a/plat/marvell/a3700/common/include/plat_macros.S b/plat/marvell/armada/a3k/common/include/plat_macros.S
index f689b4f39..f689b4f39 100644
--- a/plat/marvell/a3700/common/include/plat_macros.S
+++ b/plat/marvell/armada/a3k/common/include/plat_macros.S
diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index e6660d407..057ee2eb9 100644
--- a/plat/marvell/a3700/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2016-2019 Marvell International Ltd.
+ * Copyright (C) 2016-2021 Marvell International Ltd.
  *
  * SPDX-License-Identifier:	BSD-3-Clause
  * https://spdx.org/licenses
@@ -70,6 +70,14 @@
  * PLAT_MARVELL_FIP_BASE	= 0x4120000
  */
 
+/*
+ * Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0,
+ * it is allowed to load/copy images to 'NULL' pointers
+ */
+#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
+#define PLAT_ALLOW_ZERO_ADDR_COPY
+#endif
+
 #define PLAT_MARVELL_ATF_BASE			0x4000000
 #define PLAT_MARVELL_ATF_LOAD_ADDR		\
 			(PLAT_MARVELL_ATF_BASE + 0x100000)
@@ -81,11 +89,13 @@
 #define PLAT_MARVELL_CLUSTER_CORE_COUNT		U(2)
 /* DRAM[2MB..66MB] is used  as Trusted ROM */
 #define PLAT_MARVELL_TRUSTED_ROM_BASE		PLAT_MARVELL_ATF_LOAD_ADDR
-/* 64 MB TODO: reduce this to minimum needed according to fip image size*/
-#define PLAT_MARVELL_TRUSTED_ROM_SIZE		0x04000000
-/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
-#define PLAT_MARVELL_TRUSTED_DRAM_BASE		0x04400000
-#define PLAT_MARVELL_TRUSTED_DRAM_SIZE		0x01000000	/* 16 MB */
+/* 4 MB for FIP image */
+#define PLAT_MARVELL_TRUSTED_ROM_SIZE		0x00400000
+/* Reserve 12M for SCP (Secure PayLoad) Trusted RAM
+ * OP-TEE SHMEM follows this region
+ */
+#define PLAT_MARVELL_TRUSTED_RAM_BASE		0x04400000
+#define PLAT_MARVELL_TRUSTED_RAM_SIZE		0x00C00000	/* 12 MB DRAM */
 
 /*
  * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
@@ -138,7 +148,7 @@
 #define PLAT_MARVELL_SHARED_RAM_CACHED		1
 
 /* CCI related constants */
-#define PLAT_MARVELL_CCI_BASE		(MVEBU_REGS_BASE + MVEBU_CCI_BASE)
+#define PLAT_MARVELL_CCI_BASE			MVEBU_CCI_BASE
 #define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX	3
 #define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX	4
 
@@ -169,8 +179,7 @@
 #define PLAT_MARVELL_NSTIMER_FRAME_ID		1
 
 /* Mailbox base address */
-#define PLAT_MARVELL_MAILBOX_BASE		\
-			(MARVELL_TRUSTED_SRAM_BASE + 0x400)
+#define PLAT_MARVELL_MAILBOX_BASE	(MARVELL_SHARED_RAM_BASE + 0x400)
 #define PLAT_MARVELL_MAILBOX_SIZE		0x100
 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM		0x6D72766C	/* mrvl */
 
@@ -218,15 +227,9 @@
 #define CPU_DEC_RLR_REMAP_LOW_MASK		\
 			(0xffff <<  CPU_DEC_BR_BASE_OFFS)
 
+#define CPU_DEC_CCI_BASE_REG		(MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
+
 /* Securities */
 #define IRQ_SEC_OS_TICK_INT	MARVELL_IRQ_SEC_PHY_TIMER
 
-#define TRUSTED_DRAM_BASE	PLAT_MARVELL_TRUSTED_DRAM_BASE
-#define TRUSTED_DRAM_SIZE	PLAT_MARVELL_TRUSTED_DRAM_SIZE
-
-#ifdef BL32
-#define BL32_BASE		TRUSTED_DRAM_BASE
-#define BL32_LIMIT		TRUSTED_DRAM_SIZE
-#endif
-
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/marvell/a3700/common/io_addr_dec.c b/plat/marvell/armada/a3k/common/io_addr_dec.c
index b27633cf2..b27633cf2 100644
--- a/plat/marvell/a3700/common/io_addr_dec.c
+++ b/plat/marvell/armada/a3k/common/io_addr_dec.c
diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/armada/a3k/common/marvell_plat_config.c
index 3bf3d96bd..3bf3d96bd 100644
--- a/plat/marvell/a3700/common/marvell_plat_config.c
+++ b/plat/marvell/armada/a3k/common/marvell_plat_config.c
diff --git a/plat/marvell/armada/a3k/common/plat_cci.c b/plat/marvell/armada/a3k/common/plat_cci.c
new file mode 100644
index 000000000..56f091fef
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/plat_cci.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2021 Marek Behun <marek.behun@nic.cz>
+ *
+ * Based on plat/marvell/armada/common/marvell_cci.c
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <drivers/arm/cci.h>
+#include <lib/mmio.h>
+
+#include <plat_marvell.h>
+
+static const int cci_map[] = {
+	PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX,
+	PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX
+};
+
+/*
+ * This redefines the weak definition in
+ * plat/marvell/armada/common/marvell_cci.c
+ */
+void plat_marvell_interconnect_init(void)
+{
+	/*
+	 * To better utilize the address space, we remap CCI base address from
+	 * the default (0xD8000000) to MVEBU_CCI_BASE.
+	 * This has to be done here, rather than in cpu_wins_init(), because
+	 * cpu_wins_init() is called later.
+	 */
+	mmio_write_32(CPU_DEC_CCI_BASE_REG, MVEBU_CCI_BASE >> 20);
+
+	cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+}
diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index f8ce6fe29..2bae37e3f 100644
--- a/plat/marvell/a3700/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
  *
  * SPDX-License-Identifier:	BSD-3-Clause
  * https://spdx.org/licenses
@@ -763,6 +763,11 @@ static void __dead2 a3700_system_off(void)
 	panic();
 }
 
+#pragma weak cm3_system_reset
+void cm3_system_reset(void)
+{
+}
+
 /*****************************************************************************
  * A3700 handlers to reset the system
  *****************************************************************************
@@ -780,6 +785,9 @@ static void __dead2 a3700_system_reset(void)
 			   2 * sizeof(uint64_t));
 #endif
 
+	/* Use Cortex-M3 secure coprocessor for system reset */
+	cm3_system_reset();
+
 	/* Trigger the warm reset */
 	mmio_write_32(MVEBU_WARM_RESET_REG, MVEBU_WARM_RESET_MAGIC);
 
diff --git a/plat/marvell/a8k/a70x0/board/dram_port.c b/plat/marvell/armada/a8k/a70x0/board/dram_port.c
index 4fca7e383..355770b65 100644
--- a/plat/marvell/a8k/a70x0/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a70x0/board/dram_port.c
@@ -46,6 +46,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	   MV_DDR_TEMP_LOW} },		/* temperature */
 	MV_DDR_32BIT_ECC_PUP8_BUS_MASK,	/* subphys mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined*/
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{				/* electrical configuration */
diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
index d126f5567..a40926102 100644
--- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
@@ -102,6 +102,12 @@ struct addr_map_win ccu_memory_map[] = {	/* IO window */
 #ifdef IMAGE_BLE
 	{0x00000000f2000000,	0x4000000,	IO_0_TID}, /* IO window */
 #else
+#if LLC_SRAM
+	/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+	 * and changes the window target to SRAM_TID.
+	 */
+	{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
+#endif
 	{0x00000000f2000000,	0xe000000,	IO_0_TID},
 	{0x00000000c0000000,	0x30000000,	IO_0_TID}, /* IO window */
 	{0x0000000800000000,	0x100000000,	IO_0_TID}, /* IO window */
diff --git a/plat/marvell/a8k/a70x0/mvebu_def.h b/plat/marvell/armada/a8k/a70x0/mvebu_def.h
index 72bca12e3..72bca12e3 100644
--- a/plat/marvell/a8k/a70x0/mvebu_def.h
+++ b/plat/marvell/armada/a8k/a70x0/mvebu_def.h
diff --git a/plat/marvell/a8k/a70x0_amc/platform.mk b/plat/marvell/armada/a8k/a70x0/platform.mk
index d3a01676e..39eb71254 100644
--- a/plat/marvell/a8k/a70x0_amc/platform.mk
+++ b/plat/marvell/armada/a8k/a70x0/platform.mk
@@ -14,6 +14,7 @@ DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
 
-include plat/marvell/a8k/common/a8k_common.mk
+BOARD_DIR		:= $(shell dirname $(lastword $(MAKEFILE_LIST)))
+include plat/marvell/armada/a8k/common/a8k_common.mk
 
-include plat/marvell/common/marvell_common.mk
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a70x0_amc/board/dram_port.c b/plat/marvell/armada/a8k/a70x0_amc/board/dram_port.c
index aecf6c567..9c8c97e09 100644
--- a/plat/marvell/a8k/a70x0_amc/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a70x0_amc/board/dram_port.c
@@ -46,6 +46,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	   MV_DDR_TEMP_LOW} },		/* temperature */
 	MV_DDR_32BIT_ECC_PUP8_BUS_MASK,	/* subphys mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined*/
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{				/* electrical configuration */
diff --git a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
index f8a1c40be..3b68e91ba 100644
--- a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
@@ -93,6 +93,12 @@ struct addr_map_win ccu_memory_map[] = {
 #ifdef IMAGE_BLE
 	{0x00000000f2000000,	0x4000000,	IO_0_TID}, /* IO window */
 #else
+#if LLC_SRAM
+	/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+	 * and changes the window target to SRAM_TID.
+	 */
+	{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
+#endif
 	{0x00000000f2000000,	0xe000000,	IO_0_TID},
 	{0x00000000c0000000,    0x30000000,	IO_0_TID}, /* IO window */
 	{0x0000000800000000,    0x200000000,	IO_0_TID}, /* IO window */
diff --git a/plat/marvell/a8k/a70x0_amc/mvebu_def.h b/plat/marvell/armada/a8k/a70x0_amc/mvebu_def.h
index cedf3239a..cedf3239a 100644
--- a/plat/marvell/a8k/a70x0_amc/mvebu_def.h
+++ b/plat/marvell/armada/a8k/a70x0_amc/mvebu_def.h
diff --git a/plat/marvell/a8k/a70x0/platform.mk b/plat/marvell/armada/a8k/a70x0_amc/platform.mk
index d3a01676e..39eb71254 100644
--- a/plat/marvell/a8k/a70x0/platform.mk
+++ b/plat/marvell/armada/a8k/a70x0_amc/platform.mk
@@ -14,6 +14,7 @@ DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
 
-include plat/marvell/a8k/common/a8k_common.mk
+BOARD_DIR		:= $(shell dirname $(lastword $(MAKEFILE_LIST)))
+include plat/marvell/armada/a8k/common/a8k_common.mk
 
-include plat/marvell/common/marvell_common.mk
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/armada/a8k/a80x0/board/dram_port.c
index 02f4ffb0a..381c87150 100644
--- a/plat/marvell/a8k/a80x0/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a80x0/board/dram_port.c
@@ -52,8 +52,13 @@ static struct mv_ddr_topology_map board_topology_map = {
 	   MV_DDR_FREQ_SAR,		/* frequency */
 	   0, 0,			/* cas_l, cas_wl */
 	   MV_DDR_TEMP_LOW} },		/* temperature */
+#if DDR32
+	MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
+#else
 	MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
+#endif
 	MV_DDR_CFG_SPD,			/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined*/
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{				/* electrical configuration */
diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
index 7901dd225..4ccda14e9 100644
--- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
@@ -131,6 +131,12 @@ struct addr_map_win ccu_memory_map[] = {
 #ifdef IMAGE_BLE
 	{0x00000000f2000000,	0x4000000,  IO_0_TID}, /* IO window */
 #else
+#if LLC_SRAM
+	/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+	 * and changes the window target to SRAM_TID.
+	 */
+	{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
+#endif
 	{0x00000000f2000000,	0xe000000,  IO_0_TID}, /* IO window */
 	{0x00000000c0000000,	0x30000000,  IO_0_TID}, /* IO window */
 	{0x0000000800000000,	0x100000000,  IO_0_TID}, /* IO window */
diff --git a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
index abd85b5d2..afa3be158 100644
--- a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
+++ b/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
@@ -92,6 +92,7 @@ static const struct sata_params
 			  .g3_rx_selmupf = 0x2,
 			  .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
 			  .g3_rx_selmupi = 0x2,
+			  .polarity_invert = COMPHY_POLARITY_NO_INVERT,
 			  .valid = 0x1
 			}, /* Comphy1 */
 			{ 0 }, /* Comphy2 */
@@ -116,6 +117,7 @@ static const struct sata_params
 			 .g3_rx_selmupf = 0x2,
 			 .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
 			 .g3_rx_selmupi = 0x2,
+			 .polarity_invert = COMPHY_POLARITY_NO_INVERT,
 			 .valid = 0x1
 			}, /* Comphy3 */
 			{ 0 }, /* Comphy4 */
@@ -146,6 +148,7 @@ static const struct sata_params
 			  .g3_rx_selmupf = 0x2,
 			  .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
 			  .g3_rx_selmupi = 0x2,
+			  .polarity_invert = COMPHY_POLARITY_NO_INVERT,
 			  .valid = 0x1
 			}, /* Comphy1 */
 			{ 0 }, /* Comphy2 */
@@ -170,6 +173,7 @@ static const struct sata_params
 			  .g3_rx_selmupf = 0x2,
 			  .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
 			  .g3_rx_selmupi = 0x2,
+			  .polarity_invert = COMPHY_POLARITY_NO_INVERT,
 			  .valid = 0x1
 			}, /* Comphy3 */
 			{ 0 }, /* Comphy4 */
@@ -178,4 +182,11 @@ static const struct sata_params
 		},
 	},
 };
+
+static const struct usb_params
+	usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+		.polarity_invert = COMPHY_POLARITY_NO_INVERT
+	},
+};
 #endif /* PHY_PORTING_LAYER_H */
diff --git a/plat/marvell/a8k/a80x0/mvebu_def.h b/plat/marvell/armada/a8k/a80x0/mvebu_def.h
index 3fa119af6..3fa119af6 100644
--- a/plat/marvell/a8k/a80x0/mvebu_def.h
+++ b/plat/marvell/armada/a8k/a80x0/mvebu_def.h
diff --git a/plat/marvell/a8k/a80x0_mcbin/platform.mk b/plat/marvell/armada/a8k/a80x0/platform.mk
index 3749c3781..115dd4a82 100644
--- a/plat/marvell/a8k/a80x0_mcbin/platform.mk
+++ b/plat/marvell/armada/a8k/a80x0/platform.mk
@@ -14,6 +14,7 @@ DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_8K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
 
-include plat/marvell/a8k/common/a8k_common.mk
+BOARD_DIR		:= $(shell dirname $(lastword $(MAKEFILE_LIST)))
+include plat/marvell/armada/a8k/common/a8k_common.mk
 
-include plat/marvell/common/marvell_common.mk
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
index 25808523c..50a68b3a2 100644
--- a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
@@ -48,6 +48,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	   MV_DDR_TEMP_LOW} },		/* temperature */
 	   MV_DDR_64BIT_BUS_MASK,	/* subphys mask */
 	   MV_DDR_CFG_SPD,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined*/
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{				/* electrical configuration */
diff --git a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
new file mode 100644
index 000000000..75a1b0c30
--- /dev/null
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <armada_common.h>
+
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#include <mvebu_def.h>
+#ifndef IMAGE_BLE
+
+/*****************************************************************************
+ * GPIO Configuration
+ *****************************************************************************
+ */
+#define MPP_CONTROL_REGISTER		0xf2440018
+#define MPP_CONTROL_MPP_SEL_52_MASK	0xf0000
+#define GPIO_DATA_OUT1_REGISTER		0xf2440140
+#define GPIO_DATA_OUT_EN_CTRL1_REGISTER 0xf2440144
+#define GPIO52_MASK			0x100000
+
+/* Reset PCIe via GPIO number 52 */
+int marvell_gpio_config(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(MPP_CONTROL_REGISTER);
+	reg |= MPP_CONTROL_MPP_SEL_52_MASK;
+	mmio_write_32(MPP_CONTROL_REGISTER, reg);
+
+	reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER);
+	reg |= GPIO52_MASK;
+	mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg);
+
+	reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER);
+	reg &= ~GPIO52_MASK;
+	mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg);
+	udelay(100);
+
+	return 0;
+}
+
+/*****************************************************************************
+ * AMB Configuration
+ *****************************************************************************
+ */
+struct addr_map_win amb_memory_map[] = {
+	/* CP1 SPI1 CS0 Direct Mode access */
+	{0xf900,	0x1000000,	AMB_SPI1_CS0_ID},
+};
+
+int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
+			       uintptr_t base)
+{
+	*win = amb_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = ARRAY_SIZE(amb_memory_map);
+
+	return 0;
+}
+#endif
+
+/*****************************************************************************
+ * IO WIN Configuration
+ *****************************************************************************
+ */
+struct addr_map_win io_win_memory_map[] = {
+	/* CP1 (MCI0) internal regs */
+	{0x00000000f4000000,		0x2000000,  MCI_0_TID},
+#ifndef IMAGE_BLE
+	/* PCIe0-2 and SPI1_CS0 (RUNIT) on CP1*/
+	{0x00000000f9000000,		0x4000000,  MCI_0_TID},
+	/* MCI 0 indirect window */
+	{MVEBU_MCI_REG_BASE_REMAP(0),	0x100000,   MCI_0_TID},
+	/* MCI 1 indirect window */
+	{MVEBU_MCI_REG_BASE_REMAP(1),	0x100000,   MCI_1_TID},
+#endif
+};
+
+uint32_t marvell_get_io_win_gcr_target(int ap_index)
+{
+	return PIDI_TID;
+}
+
+int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
+				  uint32_t *size)
+{
+	*win = io_win_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = ARRAY_SIZE(io_win_memory_map);
+
+	return 0;
+}
+
+#ifndef IMAGE_BLE
+/*****************************************************************************
+ * IOB Configuration
+ *****************************************************************************
+ */
+struct addr_map_win iob_memory_map_cp0[] = {
+	/* CP0 */
+	/* PEX1_X1 window */
+	{0x00000000f7000000,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x00000000f8000000,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x00000000f6000000,	0x1000000,	PEX0_TID},
+	{0x00000000c0000000,	0x30000000,	PEX0_TID},
+	{0x0000000800000000,	0x100000000,	PEX0_TID},
+};
+
+struct addr_map_win iob_memory_map_cp1[] = {
+	/* CP1 */
+	/* SPI1_CS0 (RUNIT) window */
+	{0x00000000f9000000,	0x1000000,	RUNIT_TID},
+	/* PEX1_X1 window */
+	{0x00000000fb000000,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x00000000fc000000,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x00000000fa000000,	0x1000000,	PEX0_TID}
+};
+
+int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
+			       uintptr_t base)
+{
+	switch (base) {
+	case MVEBU_CP_REGS_BASE(0):
+		*win = iob_memory_map_cp0;
+		*size = ARRAY_SIZE(iob_memory_map_cp0);
+		return 0;
+	case MVEBU_CP_REGS_BASE(1):
+		*win = iob_memory_map_cp1;
+		*size = ARRAY_SIZE(iob_memory_map_cp1);
+		return 0;
+	default:
+		*size = 0;
+		*win = 0;
+		return 1;
+	}
+}
+#endif
+
+/*****************************************************************************
+ * CCU Configuration
+ *****************************************************************************
+ */
+struct addr_map_win ccu_memory_map[] = {
+#ifdef IMAGE_BLE
+	{0x00000000f2000000,	0x4000000,  IO_0_TID}, /* IO window */
+#else
+#if LLC_SRAM
+	/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+	 * and changes the window target to SRAM_TID.
+	 */
+	{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
+#endif
+	{0x00000000f2000000,	0xe000000,  IO_0_TID}, /* IO window */
+	{0x00000000c0000000,	0x30000000,  IO_0_TID}, /* IO window */
+	{0x0000000800000000,	0x100000000,  IO_0_TID}, /* IO window */
+#endif
+};
+
+uint32_t marvell_get_ccu_gcr_target(int ap)
+{
+	return DRAM_0_TID;
+}
+
+int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
+			       uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = ARRAY_SIZE(ccu_memory_map);
+
+	return 0;
+}
+
+/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
+
+/*****************************************************************************
+ * SKIP IMAGE Configuration
+ *****************************************************************************
+ */
+void *plat_marvell_get_skip_image_data(void)
+{
+	/* No recovery button on A8k-MCBIN board */
+	return NULL;
+}
diff --git a/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h b/plat/marvell/armada/a8k/a80x0_mcbin/mvebu_def.h
index 3fa119af6..3fa119af6 100644
--- a/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/mvebu_def.h
diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/armada/a8k/a80x0_mcbin/platform.mk
index 00d24b278..115dd4a82 100644
--- a/plat/marvell/a8k/a80x0/platform.mk
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/platform.mk
@@ -14,7 +14,7 @@ DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_8K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
 
-include plat/marvell/a8k/common/a8k_common.mk
+BOARD_DIR		:= $(shell dirname $(lastword $(MAKEFILE_LIST)))
+include plat/marvell/armada/a8k/common/a8k_common.mk
 
-include plat/marvell/common/marvell_common.mk
-PLAT_INCLUDES		+=	-Iplat/marvell/a8k/a80x0/board
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c b/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
new file mode 100644
index 000000000..3879c983a
--- /dev/null
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/mentor/mi2cv.h>
+#include <lib/mmio.h>
+
+#include <mv_ddr_if.h>
+#include <mvebu_def.h>
+#include <plat_marvell.h>
+
+#define MVEBU_AP_MPP_CTRL0_7_REG                MVEBU_AP_MPP_REGS(0)
+#define MVEBU_AP_MPP_CTRL4_OFFS                 16
+#define MVEBU_AP_MPP_CTRL5_OFFS                 20
+#define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA         0x3
+#define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA         0x3
+
+#define MVEBU_CP_MPP_CTRL37_OFFS		20
+#define MVEBU_CP_MPP_CTRL38_OFFS		24
+#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA	0x2
+#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA	0x2
+
+#define MVEBU_MPP_CTRL_MASK			0xf
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	/* Board with 1CS 8Gb x4 devices of Micron 2400T */
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+	{ { { {0x1, 0x0, 0, 0},	/* FIXME: change the cs mask for all 64 bit */
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0} },
+	   /* TODO: double check if the speed bin is 2400T */
+	   SPEED_BIN_DDR_2400T,		/* speed_bin */
+	   MV_DDR_DEV_WIDTH_8BIT,	/* sdram device width */
+	   MV_DDR_DIE_CAP_8GBIT,	/* die capacity */
+	   MV_DDR_FREQ_SAR,		/* frequency */
+	   0, 0,			/* cas_l, cas_wl */
+	   MV_DDR_TEMP_LOW} },		/* temperature */
+	   MV_DDR_64BIT_BUS_MASK,	/* subphys mask */
+	   MV_DDR_CFG_SPD,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined*/
+	{ {0} },			/* raw spd data */
+	{0},				/* timing parameters */
+	{				/* electrical configuration */
+		{			/* memory electrical configuration */
+			MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,	/* rtt_nom */
+			{
+				MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
+				MV_DDR_RTT_NOM_PARK_RZQ_DIV1  /* rtt_park 2cs */
+			},
+			{
+				MV_DDR_RTT_WR_DYN_ODT_OFF,	/* rtt_wr 1cs */
+				MV_DDR_RTT_WR_RZQ_DIV2		/* rtt_wr 2cs */
+			},
+			MV_DDR_DIC_RZQ_DIV7	/* dic */
+		},
+		{			/* phy electrical configuration */
+			MV_DDR_OHM_30,	/* data_drv_p */
+			MV_DDR_OHM_30,	/* data_drv_n */
+			MV_DDR_OHM_30,	/* ctrl_drv_p */
+			MV_DDR_OHM_30,	/* ctrl_drv_n */
+			{
+				MV_DDR_OHM_60,	/* odt_p 1cs */
+				MV_DDR_OHM_120	/* odt_p 2cs */
+			},
+			{
+				MV_DDR_OHM_60,	/* odt_n 1cs */
+				MV_DDR_OHM_120	/* odt_n 2cs */
+			},
+		},
+		{			/* mac electrical configuration */
+			MV_DDR_ODT_CFG_NORMAL,		/* odtcfg_pattern */
+			MV_DDR_ODT_CFG_ALWAYS_ON,	/* odtcfg_write */
+			MV_DDR_ODT_CFG_NORMAL,		/* odtcfg_read */
+		},
+	}
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+static void mpp_config(void)
+{
+	uint32_t val;
+	uintptr_t reg;
+
+       /* configure ap mmps 4, 5 to I2C */
+	reg = MVEBU_AP_MPP_CTRL0_7_REG;
+
+	val = mmio_read_32(reg);
+	val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_AP_MPP_CTRL4_OFFS) |
+		(MVEBU_MPP_CTRL_MASK << MVEBU_AP_MPP_CTRL5_OFFS));
+	val |= ((MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA << MVEBU_AP_MPP_CTRL4_OFFS) |
+		(MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA << MVEBU_AP_MPP_CTRL5_OFFS));
+
+	mmio_write_32(reg, val);
+}
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information received from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+void plat_marvell_dram_update_topology(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	INFO("Gathering DRAM information\n");
+
+	if (tm->cfg_src == MV_DDR_CFG_SPD) {
+		/* configure MPPs to enable i2c */
+		mpp_config();
+		/* initialize the MVEBU_AP_I2C_BASE I2C bus */
+		i2c_init((void *)MVEBU_AP_I2C_BASE);
+		/* select SPD memory page 0 to access DRAM configuration */
+		i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+		/* read data from spd */
+		i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
+			 sizeof(tm->spd_data.all_bytes));
+	}
+}
diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0_puzzle/board/marvell_plat_config.c
index fa4e144c9..0edc97745 100644
--- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/marvell_plat_config.c
@@ -165,6 +165,9 @@ struct addr_map_win ccu_memory_map[] = {
 #ifdef IMAGE_BLE
 	{0x00000000f2000000,	0x4000000,  IO_0_TID}, /* IO window */
 #else
+#if LLC_SRAM
+	{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+#endif
 	{0x00000000f2000000,	0xe000000,  IO_0_TID}, /* IO window */
 	{0x00000000c0000000,	0x30000000,  IO_0_TID}, /* IO window */
 	{0x0000000800000000,	0x100000000,  IO_0_TID}, /* IO window */
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
new file mode 100644
index 000000000..5147dd519
--- /dev/null
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2020 Sartura Ltd.
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <armada_common.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <drivers/console.h>
+#include <plat_marvell.h>
+
+/*****************************************************************************
+ * Platform specific power off functions
+ * Power off PSU / Send command to power management MCU / ...
+ *****************************************************************************
+ */
+
+unsigned char add_xor_checksum(unsigned char *buf, unsigned char xor_len)
+{
+	unsigned char xor_sum = 0;
+	unsigned int i;
+
+	for (i = 0; i < xor_len; i++)
+		xor_sum ^= buf[i];
+
+	return xor_sum;
+}
+
+int system_power_off(void)
+{
+	static console_t console;
+
+	/* WT61P803 MCU system_off_now command */
+	unsigned char system_off_now[4] = { '@', 'C', '0' };
+	int i, len;
+
+	len = sizeof(system_off_now);
+	system_off_now[len - 1] = add_xor_checksum(system_off_now, len);
+
+	console_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,
+		PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);
+
+	/* Send system_off_now to console */
+	for (i = 0; i < len; i++) {
+		console.putc(system_off_now[i],	&console);
+		udelay(1000);
+	}
+
+	console.flush(&console);
+	(void)console_unregister(&console);
+
+	mdelay(100);
+
+	return 0;
+}
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/mvebu_def.h b/plat/marvell/armada/a8k/a80x0_puzzle/mvebu_def.h
new file mode 100644
index 000000000..3fa119af6
--- /dev/null
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/mvebu_def.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef MVEBU_DEF_H
+#define MVEBU_DEF_H
+
+#include <a8k_plat_def.h>
+
+#define CP_COUNT		2	/* A80x0 has both CP0 & CP1 */
+#define I2C_SPD_ADDR		0x53	/* Access SPD data */
+#define I2C_SPD_P0_ADDR		0x36	/* Select SPD data page 0 */
+
+#endif /* MVEBU_DEF_H */
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/platform.mk b/plat/marvell/armada/a8k/a80x0_puzzle/platform.mk
new file mode 100644
index 000000000..3378d53d7
--- /dev/null
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/platform.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (C) 2018 Marvell International Ltd.
+#
+# SPDX-License-Identifier:     BSD-3-Clause
+# https://spdx.org/licenses
+#
+
+PCI_EP_SUPPORT		:= 0
+
+CP_NUM			:= 2
+$(eval $(call add_define,CP_NUM))
+
+DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_8K.cfg
+
+MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
+
+BOARD_DIR		:= 	$(shell dirname $(lastword $(MAKEFILE_LIST)))
+include plat/marvell/armada/a8k/common/a8k_common.mk
+
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index bf79ebeec..63cfce22c 100644
--- a/plat/marvell/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -1,17 +1,14 @@
 #
-# Copyright (C) 2016 - 2018 Marvell International Ltd.
+# Copyright (C) 2016 - 2020 Marvell International Ltd.
 #
 # SPDX-License-Identifier:     BSD-3-Clause
 # https://spdx.org/licenses
 
-include tools/marvell/doimage/doimage.mk
-
 PLAT_FAMILY		:= a8k
-PLAT_FAMILY_BASE	:= plat/marvell/$(PLAT_FAMILY)
-PLAT_INCLUDE_BASE	:= include/plat/marvell/$(PLAT_FAMILY)
-PLAT_COMMON_BASE	:= $(PLAT_FAMILY_BASE)/common
+PLAT_INCLUDE_BASE	:= include/plat/marvell/armada/$(PLAT_FAMILY)
+PLAT_COMMON_BASE	:= plat/marvell/armada/a8k/common
 MARVELL_DRV_BASE	:= drivers/marvell
-MARVELL_COMMON_BASE	:= plat/marvell/common
+MARVELL_COMMON_BASE	:= plat/marvell/armada/common
 
 MARVELL_SVC_TEST		:= 0
 $(eval $(call add_define,MARVELL_SVC_TEST))
@@ -22,7 +19,7 @@ ERRATA_A72_859971	:= 1
 MSS_SUPPORT		:= 1
 
 # Disable EL3 cache for power management
-BL31_CACHE_DISABLE	:= 1
+BL31_CACHE_DISABLE	:= 0
 $(eval $(call add_define,BL31_CACHE_DISABLE))
 
 $(eval $(call add_define,PCI_EP_SUPPORT))
@@ -34,11 +31,41 @@ $(eval $(call add_define,AP_NUM))
 DOIMAGEPATH		?=	tools/marvell/doimage
 DOIMAGETOOL		?=	${DOIMAGEPATH}/doimage
 
+include plat/marvell/marvell.mk
+include tools/marvell/doimage/doimage.mk
+
+ifeq (${MARVELL_SECURE_BOOT},1)
+DOIMAGE_SEC_FLAGS := -c $(DOIMAGE_SEC)
+DOIMAGE_LIBS_CHECK = \
+        if ! [ -d "/usr/include/mbedtls" ]; then \
+                        echo "****************************************" >&2; \
+                        echo "Missing mbedTLS installation! " >&2; \
+                        echo "Please download it from \"tls.mbed.org\"" >&2; \
+			echo "Alternatively on Debian/Ubuntu system install" >&2; \
+			echo "\"libmbedtls-dev\" package" >&2; \
+                        echo "Make sure to use version 2.1.0 or later" >&2; \
+                        echo "****************************************" >&2; \
+                exit 1; \
+        else if ! [ -f "/usr/include/libconfig.h" ]; then \
+                        echo "********************************************************" >&2; \
+                        echo "Missing Libconfig installation!" >&2; \
+                        echo "Please download it from \"www.hyperrealm.com/libconfig/\"" >&2; \
+                        echo "Alternatively on Debian/Ubuntu system install packages" >&2; \
+                        echo "\"libconfig8\" and \"libconfig8-dev\"" >&2; \
+                        echo "********************************************************" >&2; \
+                exit 1; \
+        fi \
+        fi
+else #MARVELL_SECURE_BOOT
+DOIMAGE_LIBS_CHECK =
+DOIMAGE_SEC_FLAGS =
+endif #MARVELL_SECURE_BOOT
+
 ROM_BIN_EXT ?= $(BUILD_PLAT)/ble.bin
 DOIMAGE_FLAGS	+= -b $(ROM_BIN_EXT) $(NAND_DOIMAGE_FLAGS) $(DOIMAGE_SEC_FLAGS)
 
 # Check whether to build system_power.c for the platform
-ifneq ("$(wildcard $(PLAT_FAMILY_BASE)/$(PLAT)/board/system_power.c)","")
+ifneq ("$(wildcard $(BOARD_DIR)/board/system_power.c)","")
 SYSTEM_POWER_SUPPORT = 1
 else
 SYSTEM_POWER_SUPPORT = 0
@@ -52,15 +79,16 @@ MARVELL_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
 				drivers/arm/gic/v2/gicv2_helpers.c	\
 				plat/common/plat_gicv2.c
 
-PLAT_INCLUDES		:=	-I$(PLAT_FAMILY_BASE)/$(PLAT)		\
+PLAT_INCLUDES		:=	-I$(BOARD_DIR)				\
+				-I$(BOARD_DIR)/board			\
 				-I$(PLAT_COMMON_BASE)/include		\
 				-I$(PLAT_INCLUDE_BASE)/common
 
 PLAT_BL_COMMON_SOURCES	:=	$(PLAT_COMMON_BASE)/aarch64/a8k_common.c \
 				drivers/ti/uart/aarch64/16550_console.S
 
-BLE_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \
-				$(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
+BLE_PORTING_SOURCES	:=	$(BOARD_DIR)/board/dram_port.c \
+				$(BOARD_DIR)/board/marvell_plat_config.c
 
 MARVELL_MOCHI_DRV	+=	$(MARVELL_DRV_BASE)/mochi/cp110_setup.c
 
@@ -85,12 +113,13 @@ MARVELL_DRV		:= 	$(MARVELL_DRV_BASE)/io_win.c	\
 				$(MARVELL_DRV_BASE)/ccu.c	\
 				$(MARVELL_DRV_BASE)/cache_llc.c	\
 				$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
-				$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c
+				$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
+				$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
 
-BL31_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
+BL31_PORTING_SOURCES	:=	$(BOARD_DIR)/board/marvell_plat_config.c
 
 ifeq ($(SYSTEM_POWER_SUPPORT),1)
-BL31_PORTING_SOURCES	+=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/system_power.c
+BL31_PORTING_SOURCES	+=	$(BOARD_DIR)/board/system_power.c
 endif
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		       \
@@ -123,8 +152,21 @@ BLE_PATH	?=  $(PLAT_COMMON_BASE)/ble
 include ${BLE_PATH}/ble.mk
 $(eval $(call MAKE_BL,e))
 
-mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL} ${BUILD_PLAT}/ble.bin
-	$(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
-	$(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
-	${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
+clean realclean distclean: mrvl_clean
+
+.PHONY: mrvl_clean
+mrvl_clean:
+	@echo "  Doimage CLEAN"
+	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
+
+${DOIMAGETOOL}: FORCE
+	@$(DOIMAGE_LIBS_CHECK)
+	${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH}
 
+${BUILD_PLAT}/${FLASH_IMAGE}: ${ROM_BIN_EXT} ${BUILD_PLAT}/${BOOT_IMAGE} ${DOIMAGETOOL}
+	@${ECHO_BLANK_LINE}
+	@echo "Building flash image"
+	${Q}${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
+	@${ECHO_BLANK_LINE}
+	@echo "Built $@ successfully"
+	@${ECHO_BLANK_LINE}
diff --git a/plat/marvell/a8k/common/aarch64/a8k_common.c b/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
index 7c2bf318f..4332a76ea 100644
--- a/plat/marvell/a8k/common/aarch64/a8k_common.c
+++ b/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
@@ -18,22 +18,27 @@
  */
 #if IMAGE_BL1
 const mmap_region_t plat_marvell_mmap[] = {
-	MARVELL_MAP_SHARED_RAM,
+	MARVELL_MAP_SECURE_RAM,
 	MAP_DEVICE0,
 	{0}
 };
 #endif
 #if IMAGE_BL2
 const mmap_region_t plat_marvell_mmap[] = {
-	MARVELL_MAP_SHARED_RAM,
+	MARVELL_MAP_SECURE_RAM,
 	MAP_DEVICE0,
 	MARVELL_MAP_DRAM,
+#ifdef SPD_opteed
+	MARVELL_MAP_OPTEE_CORE_MEM,
+	MARVELL_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
 	{0}
 };
 #endif
 
 #if IMAGE_BL2U
 const mmap_region_t plat_marvell_mmap[] = {
+	MARVELL_MAP_SECURE_RAM,
 	MAP_DEVICE0,
 	{0}
 };
@@ -48,7 +53,7 @@ const mmap_region_t plat_marvell_mmap[] = {
 
 #if IMAGE_BL31
 const mmap_region_t plat_marvell_mmap[] = {
-	MARVELL_MAP_SHARED_RAM,
+	MARVELL_MAP_SECURE_RAM,
 	MAP_DEVICE0,
 	MARVELL_MAP_DRAM,
 	{0}
@@ -56,6 +61,7 @@ const mmap_region_t plat_marvell_mmap[] = {
 #endif
 #if IMAGE_BL32
 const mmap_region_t plat_marvell_mmap[] = {
+	MARVELL_MAP_SECURE_RAM,
 	MAP_DEVICE0,
 	{0}
 };
diff --git a/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
new file mode 100644
index 000000000..d57651466
--- /dev/null
+++ b/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/marvell/cache_llc.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#define CCU_HTC_ASET			(MVEBU_CCU_BASE(MVEBU_AP0) + 0x264)
+#define MVEBU_IO_AFFINITY		(0xF00)
+#define MVEBU_SF_REG			(MVEBU_REGS_BASE + 0x40)
+#define MVEBU_SF_EN			BIT(8)
+#define MVEBU_DFX_REG(cluster_id)	(MVEBU_REGS_BASE + 0x6F82A0 + \
+					(cluster_id) * 0x4)
+#define MVEBU_DFX_CLK_EN_POS		0x3
+#define MVEBU_DFX_CL0_CLK_OFFS		16
+#define MVEBU_DFX_CL0_CLK_MASK		(0xF << MVEBU_DFX_CL0_CLK_OFFS)
+#define MVEBU_DFX_CL1_CLK_OFFS		8
+#define MVEBU_DFX_CL1_CLK_MASK		(0xF << MVEBU_DFX_CL1_CLK_OFFS)
+
+#ifdef MVEBU_SOC_AP807
+static void plat_enable_snoop_filter(void)
+{
+	int cpu_id = plat_my_core_pos();
+
+	/* Snoop filter needs to be enabled once per cluster */
+	if (cpu_id % 2)
+		return;
+
+	mmio_setbits_32(MVEBU_SF_REG, MVEBU_SF_EN);
+}
+#endif
+
+#ifndef MVEBU_SOC_AP807
+static void plat_config_dfx_clock(void)
+{
+	int cluster_id = plat_my_core_pos();
+	uint32_t val;
+
+	/* DFX clock needs to be configured once per cluster */
+	if ((cluster_id % PLAT_MAX_CPUS_PER_CLUSTER) != 0) {
+		return;
+	}
+
+	val = mmio_read_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER));
+	if (cluster_id == 0) {
+		val &= ~MVEBU_DFX_CL0_CLK_MASK;
+		val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL0_CLK_OFFS);
+	} else {
+		val &= ~MVEBU_DFX_CL1_CLK_MASK;
+		val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL1_CLK_OFFS);
+	}
+	mmio_write_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER), val);
+}
+#endif
+
+static void plat_enable_affinity(void)
+{
+	int cluster_id;
+	int affinity;
+
+	/* set CPU Affinity */
+	cluster_id = plat_my_core_pos() / PLAT_MARVELL_CLUSTER_CORE_COUNT;
+	affinity = (MVEBU_IO_AFFINITY | (1 << cluster_id));
+	mmio_write_32(CCU_HTC_ASET, affinity);
+
+	/* set barier */
+	isb();
+}
+
+void marvell_psci_arch_init(int die_index)
+{
+#if LLC_ENABLE
+	/* check if LLC is in exclusive mode
+	 * as L2 is configured to UniqueClean eviction
+	 * (in a8k reset handler)
+	 */
+	if (llc_is_exclusive(0) == 0)
+		ERROR("LLC should be configured to exclusice mode\n");
+#endif
+
+	/* Enable Affinity */
+	plat_enable_affinity();
+
+#ifdef MVEBU_SOC_AP807
+	plat_enable_snoop_filter();
+#else
+	plat_config_dfx_clock();
+#endif
+}
diff --git a/plat/marvell/a8k/common/aarch64/plat_helpers.S b/plat/marvell/armada/a8k/common/aarch64/plat_helpers.S
index fadc4c26b..fadc4c26b 100644
--- a/plat/marvell/a8k/common/aarch64/plat_helpers.S
+++ b/plat/marvell/armada/a8k/common/aarch64/plat_helpers.S
diff --git a/plat/marvell/a8k/common/ble/ble.ld.S b/plat/marvell/armada/a8k/common/ble/ble.ld.S
index d7a05928c..d7a05928c 100644
--- a/plat/marvell/a8k/common/ble/ble.ld.S
+++ b/plat/marvell/armada/a8k/common/ble/ble.ld.S
diff --git a/plat/marvell/a8k/common/ble/ble.mk b/plat/marvell/armada/a8k/common/ble/ble.mk
index b6a9cd291..78c62a010 100644
--- a/plat/marvell/a8k/common/ble/ble.mk
+++ b/plat/marvell/armada/a8k/common/ble/ble.mk
@@ -5,10 +5,10 @@
 
 MV_DDR_PATH		?=	drivers/marvell/mv_ddr
 
-MV_DDR_LIB		= 	$(CURDIR)/$(BUILD_PLAT)/ble/mv_ddr_lib.a
-LIBC_LIB		=	$(CURDIR)/$(BUILD_PLAT)/lib/libc.a
-BLE_LIBS		= 	$(MV_DDR_LIB) $(LIBC_LIB)
-PLAT_MARVELL		=	plat/marvell
+MV_DDR_LIB		=	$(BUILD_PLAT)/ble/mv_ddr_lib.a
+LIBC_LIB		=	$(BUILD_PLAT)/lib/libc.a
+BLE_LIBS		=	$(MV_DDR_LIB) $(LIBC_LIB)
+PLAT_MARVELL		=	plat/marvell/armada
 
 BLE_SOURCES		+= 	$(BLE_PATH)/ble_main.c				\
 				$(BLE_PATH)/ble_mem.S				\
@@ -26,7 +26,5 @@ PLAT_INCLUDES		+= 	-I$(MV_DDR_PATH)				\
 
 BLE_LINKERFILE		:=	$(BLE_PATH)/ble.ld.S
 
-FORCE:
-
 $(MV_DDR_LIB): FORCE
-	@+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(PLAT_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(CURDIR)/$(BUILD_PLAT)/ble
+	@+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(PLAT_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
diff --git a/plat/marvell/a8k/common/ble/ble_main.c b/plat/marvell/armada/a8k/common/ble/ble_main.c
index 5b3acec2d..5b3acec2d 100644
--- a/plat/marvell/a8k/common/ble/ble_main.c
+++ b/plat/marvell/armada/a8k/common/ble/ble_main.c
diff --git a/plat/marvell/a8k/common/ble/ble_mem.S b/plat/marvell/armada/a8k/common/ble/ble_mem.S
index a48d5463c..a48d5463c 100644
--- a/plat/marvell/a8k/common/ble/ble_mem.S
+++ b/plat/marvell/armada/a8k/common/ble/ble_mem.S
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
index de8031536..de8031536 100644
--- a/plat/marvell/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
diff --git a/plat/marvell/a8k/common/include/ddr_info.h b/plat/marvell/armada/a8k/common/include/ddr_info.h
index e19036a26..e19036a26 100644
--- a/plat/marvell/a8k/common/include/ddr_info.h
+++ b/plat/marvell/armada/a8k/common/include/ddr_info.h
diff --git a/plat/marvell/a8k/common/include/mentor_i2c_plat.h b/plat/marvell/armada/a8k/common/include/mentor_i2c_plat.h
index e03c448a6..e03c448a6 100644
--- a/plat/marvell/a8k/common/include/mentor_i2c_plat.h
+++ b/plat/marvell/armada/a8k/common/include/mentor_i2c_plat.h
diff --git a/plat/marvell/a8k/common/include/plat_macros.S b/plat/marvell/armada/a8k/common/include/plat_macros.S
index 8faccf00b..8faccf00b 100644
--- a/plat/marvell/a8k/common/include/plat_macros.S
+++ b/plat/marvell/armada/a8k/common/include/plat_macros.S
diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index ec1c9036c..7d8505991 100644
--- a/plat/marvell/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -92,13 +92,20 @@
 #define PLAT_MARVELL_CORE_COUNT			(PLAT_MARVELL_CLUSTER_COUNT * \
 						PLAT_MARVELL_CLUSTER_CORE_COUNT)
 
-/* DRAM[2MB..66MB] is used as Trusted ROM */
+#define PLAT_MAX_CPUS_PER_CLUSTER		PLAT_MARVELL_CLUSTER_CORE_COUNT
+
+/* Part of DRAM that is used as Trusted ROM */
 #define PLAT_MARVELL_TRUSTED_ROM_BASE		PLAT_MARVELL_ATF_LOAD_ADDR
-/* 64 MB TODO: reduce this to minimum needed according to fip image size */
-#define PLAT_MARVELL_TRUSTED_ROM_SIZE		0x04000000
-/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
-#define PLAT_MARVELL_TRUSTED_DRAM_BASE		0x04400000
-#define PLAT_MARVELL_TRUSTED_DRAM_SIZE		0x01000000	/* 16 MB */
+/* 4 MB for FIP image */
+#define PLAT_MARVELL_TRUSTED_ROM_SIZE		0x00400000
+/* Reserve 12MB for SCP (Secure PayLoad) Trusted RAM
+ * OP-TEE 4MB SHMEM follows this region
+ */
+#define PLAT_MARVELL_TRUSTED_RAM_BASE		0x04400000
+#define PLAT_MARVELL_TRUSTED_RAM_SIZE		0x00C00000	/* 12 MB DRAM */
+
+#define PLAT_MARVELL_LLC_SRAM_BASE		0x05400000
+#define PLAT_MARVELL_LLC_SRAM_SIZE		0x00100000	/* 1 MB SRAM */
 
 /*
  * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
@@ -182,22 +189,14 @@
 /* Mailbox base address (note the lower memory space
  * is reserved for BLE data)
  */
-#define PLAT_MARVELL_MAILBOX_BASE		(MARVELL_TRUSTED_SRAM_BASE \
-							+ 0x400)
+#define PLAT_MARVELL_MAILBOX_BASE		(MARVELL_SHARED_RAM_BASE  \
+						+ 0x400)
 #define PLAT_MARVELL_MAILBOX_SIZE		0x100
 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM		0x6D72766C	/* mrvl */
 
 /* Securities */
 #define IRQ_SEC_OS_TICK_INT			MARVELL_IRQ_SEC_PHY_TIMER
 
-#define TRUSTED_DRAM_BASE			PLAT_MARVELL_TRUSTED_DRAM_BASE
-#define TRUSTED_DRAM_SIZE			PLAT_MARVELL_TRUSTED_DRAM_SIZE
-
-#ifdef BL32
-#define BL32_BASE				TRUSTED_DRAM_BASE
-#define BL32_LIMIT				TRUSTED_DRAM_SIZE
-#endif
-
 #define MVEBU_PMU_IRQ_WA
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
index 58f23d8dd..d8d492193 100644
--- a/plat/marvell/a8k/common/mss/mss_a8k.mk
+++ b/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
@@ -5,10 +5,11 @@
 # https://spdx.org/licenses
 #
 
-PLAT_MARVELL		:=	plat/marvell
+PLAT_MARVELL		:=	plat/marvell/armada
 A8K_MSS_SOURCE		:=	$(PLAT_MARVELL)/a8k/common/mss
 
-BL2_SOURCES		+=	$(A8K_MSS_SOURCE)/mss_bl2_setup.c
+BL2_SOURCES		+=	$(A8K_MSS_SOURCE)/mss_bl2_setup.c \
+				$(MARVELL_MOCHI_DRV)
 
 BL31_SOURCES		+=	$(A8K_MSS_SOURCE)/mss_pm_ipc.c
 
diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index 728ee54a0..b919cb337 100644
--- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -10,6 +10,7 @@
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/marvell/ccu.h>
+#include <drivers/marvell/mochi/ap_setup.h>
 #include <drivers/marvell/mochi/cp110_setup.h>
 #include <lib/mmio.h>
 
@@ -18,9 +19,6 @@
 
 #include "mss_scp_bootloader.h"
 
-/* IO windows configuration */
-#define IOW_GCR_OFFSET		(0x70)
-
 /* MSS windows configuration */
 #define MSS_AEBR(base)			(base + 0x160)
 #define MSS_AIBR(base)			(base + 0x164)
@@ -51,7 +49,7 @@ struct addr_map_win ccu_mem_map[] = {
  */
 static int bl2_plat_mmap_init(void)
 {
-	int cfg_num, win_id, cfg_idx;
+	int cfg_num, win_id, cfg_idx, cp;
 
 	cfg_num =  ARRAY_SIZE(ccu_mem_map);
 
@@ -65,14 +63,29 @@ static int bl2_plat_mmap_init(void)
 	 * Do not touch CCU window 0,
 	 * it's used for the internal registers access
 	 */
-	for (cfg_idx = 0, win_id = 1; cfg_idx < cfg_num; cfg_idx++, win_id++) {
+	for (cfg_idx = 0, win_id = 1;
+	     (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) {
+		/* Skip already enabled CCU windows */
+		if (ccu_is_win_enabled(MVEBU_AP0, win_id))
+			continue;
 		/* Enable required CCU windows */
 		ccu_win_check(&ccu_mem_map[cfg_idx]);
 		ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
+		cfg_idx++;
 	}
 
-	/* Set the default target id to PIDI */
-	mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
+	/* Config address for each cp other than cp0 */
+	for (cp = 1; cp < CP_COUNT; cp++)
+		update_cp110_default_win(cp);
+
+	/* There is need to configure IO_WIN windows again to overwrite
+	 * temporary configuration done during update_cp110_default_win
+	 */
+	init_io_win(MVEBU_AP0);
+
+	/* Open AMB bridge required for MG access */
+	for (cp = 0; cp < CP_COUNT; cp++)
+		cp110_amb_init(MVEBU_CP_REGS_BASE(cp));
 
 	return 0;
 }
@@ -125,6 +138,8 @@ uint32_t bl2_plat_get_cp_count(int ap_idx)
 	if (revision == MVEBU_80X0_DEV_ID ||
 	    revision == MVEBU_80X0_CP115_DEV_ID)
 		return 2;
+	else if (revision == MVEBU_CN9130_DEV_ID)
+		return CP_COUNT;
 	else
 		return 1;
 }
diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.c b/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.c
index a0705832f..a0705832f 100644
--- a/plat/marvell/a8k/common/mss/mss_pm_ipc.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.c
diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.h b/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.h
index 1dfa9fa03..1dfa9fa03 100644
--- a/plat/marvell/a8k/common/mss/mss_pm_ipc.h
+++ b/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.h
diff --git a/plat/marvell/a8k/common/plat_bl1_setup.c b/plat/marvell/armada/a8k/common/plat_bl1_setup.c
index f9521c871..f9521c871 100644
--- a/plat/marvell/a8k/common/plat_bl1_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl1_setup.c
diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
index 98b3966ae..552c9b298 100644
--- a/plat/marvell/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
@@ -116,18 +116,15 @@ void bl31_plat_arch_setup(void)
 		marvell_bl31_plat_arch_setup();
 
 	for (cp = 0; cp < CP_COUNT; cp++) {
-	/* configure cp110 for CP0*/
-		if (cp == 1)
-			mci_initialize(MVEBU_MCI0);
-
-	/* initialize MCI & CP1 */
 		cp110_init(MVEBU_CP_REGS_BASE(cp),
 			   STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
 
-	/* Should be called only after setting IOB windows */
 		marvell_bl31_mpp_init(cp);
 	}
 
+	for (cp = 1; cp < CP_COUNT; cp++)
+		mci_link_tune(cp - 1);
+
 	/* initialize IPC between MSS and ATF */
 	if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
 	    mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c
index 7f9e24278..e4e09fb41 100644
--- a/plat/marvell/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c
@@ -74,18 +74,11 @@
 					 (0x24 << AVS_LOW_VDD_LIMIT_OFFSET) | \
 					 (0x1 << AVS_SOFT_RESET_OFFSET) | \
 					 (0x1 << AVS_ENABLE_OFFSET))
-/* VDD limit is 0.82V for all A3900 devices
- * AVS offsets are not the same as in A70x0
- */
-#define AVS_A3900_CLK_VALUE		((0x80u << 24) | \
-					 (0x2c2 << 13) | \
-					 (0x2c2 << 3) | \
-					 (0x1 << AVS_SOFT_RESET_OFFSET) | \
-					 (0x1 << AVS_ENABLE_OFFSET))
-/* VDD is 0.88V for 2GHz clock */
-#define AVS_A3900_HIGH_CLK_VALUE	((0x80u << 24) | \
-					 (0x2f5 << 13) | \
-					 (0x2f5 << 3) | \
+
+/* VDD is 0.88V for 2GHz clock on CN913x devices */
+#define AVS_AP807_CLK_VALUE		((0x80UL << 24) | \
+					 (0x2dc << 13) | \
+					 (0x2dc << 3) | \
 					 (0x1 << AVS_SOFT_RESET_OFFSET) | \
 					 (0x1 << AVS_ENABLE_OFFSET))
 
@@ -117,7 +110,6 @@
 #define EFUSE_AP_LD0_REVID_MASK		0xF
 #define EFUSE_AP_LD0_BIN_OFFS		16		/* LD0[80:79] */
 #define EFUSE_AP_LD0_BIN_MASK		0x3
-#define EFUSE_AP_LD0_SWREV_OFFS		50		/* LD0[115:113] */
 #define EFUSE_AP_LD0_SWREV_MASK		0x7
 
 #ifndef MVEBU_SOC_AP807
@@ -131,16 +123,18 @@
 	#define EFUSE_AP_LD0_SVC2_OFFS		26	/* LD0[96:89] */
 	#define EFUSE_AP_LD0_SVC3_OFFS		34	/* LD0[104:97] */
 	#define EFUSE_AP_LD0_WP_MASK		0xFF
+	#define EFUSE_AP_LD0_SWREV_OFFS		50	/* LD0[115:113] */
 #else
 	/* AP807 AVS work points in the LD0 eFuse
 	 * SVC1 work point:     LD0[91:81]
 	 * SVC2 work point:     LD0[102:92]
 	 * SVC3 work point:     LD0[113:103]
 	 */
-	#define EFUSE_AP_LD0_SVC1_OFFS		17	/* LD0[91:81] */
-	#define EFUSE_AP_LD0_SVC2_OFFS		28	/* LD0[102:92] */
-	#define EFUSE_AP_LD0_SVC3_OFFS		39	/* LD0[113:103] */
-	#define EFUSE_AP_LD0_WP_MASK		0x3FF
+	#define EFUSE_AP_LD0_SVC1_OFFS		18	/* LD0[91:81] */
+	#define EFUSE_AP_LD0_SVC2_OFFS		29	/* LD0[102:92] */
+	#define EFUSE_AP_LD0_SVC3_OFFS		40	/* LD0[113:103] */
+	#define EFUSE_AP_LD0_WP_MASK		0x7FF	/* 10 data,1 parity */
+	#define EFUSE_AP_LD0_SWREV_OFFS		51	/* LD0[116:114] */
 #endif
 
 #define EFUSE_AP_LD0_SVC4_OFFS			42	/* LD0[112:105] */
@@ -223,11 +217,9 @@ static void ble_plat_avs_config(void)
 						 FREQ_MODE_AP_SAR_REG_NUM)));
 	/* Check which SoC is running and act accordingly */
 	if (ble_get_ap_type() == CHIP_ID_AP807) {
-		/* Increase CPU voltage for higher CPU clock */
-		if (freq_mode == CPU_2000_DDR_1200_RCLK_1200)
-			avs_val = AVS_A3900_HIGH_CLK_VALUE;
-		else
-			avs_val = AVS_A3900_CLK_VALUE;
+
+		avs_val = AVS_AP807_CLK_VALUE;
+
 	} else {
 		/* Check which SoC is running and act accordingly */
 		device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
@@ -381,6 +373,7 @@ static void ble_plat_svc_config(void)
 	uint64_t efuse;
 	uint32_t device_id, single_cluster;
 	uint16_t  svc[4], perr[4], i, sw_ver;
+	uint8_t	 avs_data_bits, min_sw_ver, svc_fields;
 	unsigned int ap_type;
 
 	/* Set access to LD0 */
@@ -434,22 +427,28 @@ static void ble_plat_svc_config(void)
 			 & EFUSE_AP_LD0_WP_MASK;
 		INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
 		     svc[0], svc[1], svc[2], svc[3]);
+		avs_data_bits = 7;
+		min_sw_ver = 2; /* parity check from sw revision 2 */
+		svc_fields = 4;
 	} else {
 		INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n",
 		     svc[0], svc[1], svc[2]);
+		avs_data_bits = 10;
+		min_sw_ver = 1; /* parity check required from sw revision 1 */
+		svc_fields = 3;
 	}
 
 	/* Validate parity of SVC workpoint values */
-	for (i = 0; i < 4; i++) {
+	for (i = 0; i < svc_fields; i++) {
 		uint8_t parity, bit;
-
 		perr[i] = 0;
 
-		for (bit = 1, parity = svc[i] & 1; bit < 7; bit++)
+		for (bit = 1, parity = (svc[i] & 1); bit < avs_data_bits; bit++)
 			parity ^= (svc[i] >> bit) & 1;
 
-		/* Starting from SW version 2, the parity check is mandatory */
-		if ((sw_ver > 1) && (parity != ((svc[i] >> 7) & 1)))
+		/* From SW version 1 or 2 (AP806/AP807), check parity */
+		if ((sw_ver >= min_sw_ver) &&
+		    (parity != ((svc[i] >> avs_data_bits) & 1)))
 			perr[i] = 1; /* register the error */
 	}
 
@@ -463,7 +462,6 @@ static void ble_plat_svc_config(void)
 		NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
 			single_cluster == 0 ? "8040" : "8020", freq_pidi_mode);
 		switch (freq_pidi_mode) {
-		case CPU_1800_DDR_1200_RCLK_1200:
 		case CPU_1800_DDR_1050_RCLK_1050:
 			if (perr[1])
 				goto perror;
@@ -540,8 +538,19 @@ static void ble_plat_svc_config(void)
 				if (perr[0])
 					goto perror;
 				avs_workpoint = svc[0];
-			} else
-				avs_workpoint = 0;
+			} else {
+#if MARVELL_SVC_TEST
+				reg_val = mmio_read_32(AVS_EN_CTRL_REG);
+				avs_workpoint = (reg_val &
+					AVS_VDD_LOW_LIMIT_MASK) >>
+					AVS_LOW_VDD_LIMIT_OFFSET;
+				NOTICE("7040 1600Mhz, avs = 0x%x\n",
+					avs_workpoint);
+#else
+				NOTICE("SVC: AVS work point not changed\n");
+				return;
+#endif
+			}
 			break;
 		}
 	} else if (device_id == MVEBU_3900_DEV_ID) {
@@ -564,6 +573,31 @@ static void ble_plat_svc_config(void)
 			avs_workpoint = svc[0];
 			break;
 		}
+	} else if (device_id == MVEBU_CN9130_DEV_ID) {
+		NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
+		       "CN913x", freq_pidi_mode);
+		switch (freq_pidi_mode) {
+		case CPU_2200_DDR_1200_RCLK_1200:
+			if (perr[0])
+				goto perror;
+			avs_workpoint = svc[0];
+			break;
+		case CPU_2000_DDR_1200_RCLK_1200:
+			if (perr[1])
+				goto perror;
+			avs_workpoint = svc[1];
+			break;
+		case CPU_1600_DDR_1200_RCLK_1200:
+			if (perr[2])
+				goto perror;
+			avs_workpoint = svc[2];
+			break;
+		default:
+			ERROR("SVC: Unsupported Frequency 0x%x\n",
+				freq_pidi_mode);
+			return;
+
+		}
 	} else {
 		ERROR("SVC: Unsupported Device ID 0x%x\n", device_id);
 		return;
@@ -571,13 +605,17 @@ static void ble_plat_svc_config(void)
 
 	/* Set AVS control if needed */
 	if (avs_workpoint == 0) {
-		ERROR("SVC: AVS work point not changed\n");
+		ERROR("SVC: You are using a frequency setup which is\n");
+		ERROR("Not supported by this device\n");
+		ERROR("This may result in malfunction of the device\n");
 		return;
 	}
 
 	/* Remove parity bit */
 	if (ap_type != CHIP_ID_AP807)
 		avs_workpoint &= 0x7F;
+	else
+		avs_workpoint &= 0x3FF;
 
 	/* Update WP from EEPROM if needed */
 	avs_workpoint = avs_update_from_eeprom(avs_workpoint);
diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index 96e95c271..96e95c271 100644
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
diff --git a/plat/marvell/a8k/common/plat_pm_trace.c b/plat/marvell/armada/a8k/common/plat_pm_trace.c
index f589ff31b..f589ff31b 100644
--- a/plat/marvell/a8k/common/plat_pm_trace.c
+++ b/plat/marvell/armada/a8k/common/plat_pm_trace.c
diff --git a/plat/marvell/a8k/common/plat_thermal.c b/plat/marvell/armada/a8k/common/plat_thermal.c
index a2fc0d0ab..a2fc0d0ab 100644
--- a/plat/marvell/a8k/common/plat_thermal.c
+++ b/plat/marvell/armada/a8k/common/plat_thermal.c
diff --git a/plat/marvell/common/aarch64/marvell_bl2_mem_params_desc.c b/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c
index 6a8e11c90..8d909dc59 100644
--- a/plat/marvell/common/aarch64/marvell_bl2_mem_params_desc.c
+++ b/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c
@@ -100,6 +100,45 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
 
 	    .next_handoff_image_id = BL33_IMAGE_ID,
     },
+
+	/*
+	 * Fill BL32 external 1 related information.
+	 * A typical use for extra1 image is with OP-TEE
+	 * where it is the pager image.
+	 */
+	{
+	    .image_id = BL32_EXTRA1_IMAGE_ID,
+
+	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+	    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+	    .image_info.image_base = BL32_BASE,
+	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+
+	    .next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+
+	/*
+	 * Fill BL32 external 2 related information.
+	 * A typical use for extra2 image is with OP-TEE,
+	 * where it is the paged image.
+	 */
+	{
+	    .image_id = BL32_EXTRA2_IMAGE_ID,
+
+	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+#ifdef SPD_opteed
+	    .image_info.image_base = MARVELL_OPTEE_PAGEABLE_LOAD_BASE,
+	    .image_info.image_max_size = MARVELL_OPTEE_PAGEABLE_LOAD_SIZE,
+#endif
+	    .next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 # endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
diff --git a/plat/marvell/common/aarch64/marvell_common.c b/plat/marvell/armada/common/aarch64/marvell_common.c
index 21a62d483..21a62d483 100644
--- a/plat/marvell/common/aarch64/marvell_common.c
+++ b/plat/marvell/armada/common/aarch64/marvell_common.c
diff --git a/plat/marvell/common/aarch64/marvell_helpers.S b/plat/marvell/armada/common/aarch64/marvell_helpers.S
index 6f625b95d..b798f17c5 100644
--- a/plat/marvell/common/aarch64/marvell_helpers.S
+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2020, ARM Limited. All rights reserved.
  * Copyright (C) 2018 Marvell International Ltd.
  *
  * SPDX-License-Identifier:     BSD-3-Clause
@@ -90,10 +91,10 @@ func plat_crash_console_putc
 endfunc plat_crash_console_putc
 
 	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
+	 * void plat_crash_console_flush()
 	 * Function to force a write of all buffered
 	 * data that hasn't been output.
-	 * Out : return -1 on error else return 0.
+	 * Out : void.
 	 * Clobber list : r0
 	 * ---------------------------------------------
 	 */
@@ -185,7 +186,7 @@ func disable_sram
 
 	/* Invalidate all ways */
 	ldr	w1, =LLC_WAY_MASK
-	ldr	x0, =MASTER_L2X0_INV_WAY
+	ldr	x0, =MASTER_LLC_INV_WAY
 	str	w1, [x0]
 
 	/* Finally disable LLC */
diff --git a/plat/marvell/common/marvell_bl1_setup.c b/plat/marvell/armada/common/marvell_bl1_setup.c
index 7b7cef39b..7b7cef39b 100644
--- a/plat/marvell/common/marvell_bl1_setup.c
+++ b/plat/marvell/armada/common/marvell_bl1_setup.c
diff --git a/plat/marvell/common/marvell_bl2_setup.c b/plat/marvell/armada/common/marvell_bl2_setup.c
index 3c1c39112..3dfa82e0e 100644
--- a/plat/marvell/common/marvell_bl2_setup.c
+++ b/plat/marvell/armada/common/marvell_bl2_setup.c
@@ -17,6 +17,9 @@
 #include <drivers/console.h>
 #include <lib/utils.h>
 
+#ifdef SPD_opteed
+#include <optee_utils.h>
+#endif
 #include <marvell_def.h>
 #include <plat_marvell.h>
 
@@ -97,9 +100,29 @@ int marvell_bl2_handle_post_image_load(unsigned int image_id)
 	int err = 0;
 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
 
+#ifdef SPD_opteed
+	bl_mem_params_node_t *pager_mem_params = NULL;
+	bl_mem_params_node_t *paged_mem_params = NULL;
+#endif /* SPD_opteed */
 	assert(bl_mem_params);
 
 	switch (image_id) {
+	case BL32_IMAGE_ID:
+#ifdef SPD_opteed
+		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+		assert(pager_mem_params);
+
+		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+		assert(paged_mem_params);
+
+		err = parse_optee_header(&bl_mem_params->ep_info,
+					 &pager_mem_params->image_info,
+					 &paged_mem_params->image_info);
+		if (err != 0)
+			WARN("OPTEE header parse error.\n");
+#endif /* SPD_opteed */
+		bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl32_entry();
+		break;
 
 	case BL33_IMAGE_ID:
 		/* BL33 expects to receive the primary CPU MPID (through r0) */
diff --git a/plat/marvell/common/marvell_bl31_setup.c b/plat/marvell/armada/common/marvell_bl31_setup.c
index 26ba90654..26ba90654 100644
--- a/plat/marvell/common/marvell_bl31_setup.c
+++ b/plat/marvell/armada/common/marvell_bl31_setup.c
diff --git a/plat/marvell/common/marvell_cci.c b/plat/marvell/armada/common/marvell_cci.c
index 80351aedc..80351aedc 100644
--- a/plat/marvell/common/marvell_cci.c
+++ b/plat/marvell/armada/common/marvell_cci.c
diff --git a/plat/marvell/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index f41d7a47f..04eb51c48 100644
--- a/plat/marvell/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -3,11 +3,10 @@
 # SPDX-License-Identifier:     BSD-3-Clause
 # https://spdx.org/licenses
 
-MARVELL_PLAT_BASE		:= plat/marvell
-MARVELL_PLAT_INCLUDE_BASE	:= include/plat/marvell
+MARVELL_PLAT_BASE		:= plat/marvell/armada
+MARVELL_PLAT_INCLUDE_BASE	:= include/plat/marvell/armada
 
-include $(MARVELL_PLAT_BASE)/version.mk
-include $(MARVELL_PLAT_BASE)/marvell.mk
+include plat/marvell/version.mk
 
 VERSION_STRING			+=(Marvell-${SUBVERSION})
 
@@ -16,6 +15,11 @@ SEPARATE_CODE_AND_RODATA	:= 1
 # flag to switch from PLL to ARO
 ARO_ENABLE			:= 0
 $(eval $(call add_define,ARO_ENABLE))
+
+# Convert LLC to secure SRAM
+LLC_SRAM			:= 0
+$(eval $(call add_define,LLC_SRAM))
+
 # Enable/Disable LLC
 LLC_ENABLE			:= 1
 $(eval $(call add_define,LLC_ENABLE))
@@ -53,6 +57,10 @@ BL2_SOURCES		+=	drivers/io/io_fip.c					\
 				$(MARVELL_PLAT_BASE)/common/aarch64/marvell_bl2_mem_params_desc.c	\
 				$(MARVELL_PLAT_BASE)/common/marvell_image_load.c
 
+ifeq (${SPD},opteed)
+PLAT_INCLUDES		+=	-Iinclude/lib
+BL2_SOURCES		+=	lib/optee/optee_utils.c
+endif
 
 BL31_SOURCES		+=	$(MARVELL_PLAT_BASE)/common/marvell_bl31_setup.c	\
 				$(MARVELL_PLAT_BASE)/common/marvell_pm.c		\
@@ -64,9 +72,32 @@ BL31_SOURCES		+=	$(MARVELL_PLAT_BASE)/common/marvell_bl31_setup.c	\
 # PSCI functionality
 $(eval $(call add_define,CONFIG_ARM64))
 
+# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
+# in the FIP if the platform requires.
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
+endif
+
 # MSS (SCP) build
 ifeq (${MSS_SUPPORT}, 1)
 include $(MARVELL_PLAT_BASE)/common/mss/mss_common.mk
 endif
 
-fip: mrvl_flash
+$(BUILD_PLAT)/$(BOOT_IMAGE): $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(FIP_NAME)
+	$(if $(shell find $(BUILD_PLAT)/bl1.bin -type f -size +128k),$(error "Image '$(BUILD_PLAT)/bl1.bin' is bigger than 128kB"))
+	@cp $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+	@truncate -s %128K $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+	@cat $(BUILD_PLAT)/$(FIP_NAME) >> $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+	@truncate -s %4 $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+	@$(ECHO_BLANK_LINE)
+	@echo "Built $@ successfully"
+	@$(ECHO_BLANK_LINE)
+
+.PHONY: mrvl_bootimage
+mrvl_bootimage: $(BUILD_PLAT)/$(BOOT_IMAGE)
+
+.PHONY: mrvl_flash
+mrvl_flash: $(BUILD_PLAT)/$(FLASH_IMAGE)
diff --git a/plat/marvell/common/marvell_console.c b/plat/marvell/armada/common/marvell_console.c
index 22c5eb3af..c84b004be 100644
--- a/plat/marvell/common/marvell_console.c
+++ b/plat/marvell/armada/common/marvell_console.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,16 +14,15 @@
 
 #ifdef PLAT_a3700
 #include <drivers/marvell/uart/a3700_console.h>
-
-static console_a3700_t marvell_boot_console;
-static console_a3700_t marvell_runtime_console;
+#define console_marvell_register console_a3700_register
 #else
 #include <drivers/ti/uart/uart_16550.h>
-
-static console_16550_t marvell_boot_console;
-static console_16550_t marvell_runtime_console;
+#define console_marvell_register console_16550_register
 #endif
 
+static console_t marvell_boot_console;
+static console_t marvell_runtime_console;
+
 /*******************************************************************************
  * Functions that set up the console
  ******************************************************************************/
@@ -32,15 +31,10 @@ static console_16550_t marvell_runtime_console;
 void marvell_console_boot_init(void)
 {
 	int rc =
-#ifdef PLAT_a3700
-	console_a3700_register(
-#else
-	console_16550_register(
-#endif
-				PLAT_MARVELL_BOOT_UART_BASE,
-				PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
-				MARVELL_CONSOLE_BAUDRATE,
-				&marvell_boot_console);
+	console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
+				 PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
+				 MARVELL_CONSOLE_BAUDRATE,
+				 &marvell_boot_console);
 	if (rc == 0) {
 		/*
 		 * The crash console doesn't use the multi console API, it uses
@@ -50,40 +44,33 @@ void marvell_console_boot_init(void)
 		panic();
 	}
 
-	console_set_scope(&marvell_boot_console.console,
-			  CONSOLE_FLAG_BOOT);
+	console_set_scope(&marvell_boot_console, CONSOLE_FLAG_BOOT);
 }
 
 void marvell_console_boot_end(void)
 {
-	(void)console_flush();
+	console_flush();
 
-	(void)console_unregister(&marvell_boot_console.console);
+	(void)console_unregister(&marvell_boot_console);
 }
 
 /* Initialize the runtime console */
 void marvell_console_runtime_init(void)
 {
 	int rc =
-#ifdef PLAT_a3700
-	console_a3700_register(
-#else
-	console_16550_register(
-#endif
-				PLAT_MARVELL_BOOT_UART_BASE,
-				PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
-				MARVELL_CONSOLE_BAUDRATE,
-				&marvell_runtime_console);
+	console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
+				 PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
+				 MARVELL_CONSOLE_BAUDRATE,
+				 &marvell_runtime_console);
 	if (rc == 0)
 		panic();
 
-	console_set_scope(&marvell_runtime_console.console,
-			  CONSOLE_FLAG_RUNTIME);
+	console_set_scope(&marvell_runtime_console, CONSOLE_FLAG_RUNTIME);
 }
 
 void marvell_console_runtime_end(void)
 {
-	(void)console_flush();
+	console_flush();
 
-	(void)console_unregister(&marvell_runtime_console.console);
+	(void)console_unregister(&marvell_runtime_console);
 }
diff --git a/plat/marvell/common/marvell_ddr_info.c b/plat/marvell/armada/common/marvell_ddr_info.c
index 734099652..734099652 100644
--- a/plat/marvell/common/marvell_ddr_info.c
+++ b/plat/marvell/armada/common/marvell_ddr_info.c
diff --git a/plat/marvell/common/marvell_gicv2.c b/plat/marvell/armada/common/marvell_gicv2.c
index 2505c9f84..2505c9f84 100644
--- a/plat/marvell/common/marvell_gicv2.c
+++ b/plat/marvell/armada/common/marvell_gicv2.c
diff --git a/plat/marvell/common/marvell_gicv3.c b/plat/marvell/armada/common/marvell_gicv3.c
index 0bd554570..0bd554570 100644
--- a/plat/marvell/common/marvell_gicv3.c
+++ b/plat/marvell/armada/common/marvell_gicv3.c
diff --git a/plat/marvell/common/marvell_image_load.c b/plat/marvell/armada/common/marvell_image_load.c
index be16b0898..be16b0898 100644
--- a/plat/marvell/common/marvell_image_load.c
+++ b/plat/marvell/armada/common/marvell_image_load.c
diff --git a/plat/marvell/common/marvell_io_storage.c b/plat/marvell/armada/common/marvell_io_storage.c
index 065f95688..2627ba4ef 100644
--- a/plat/marvell/common/marvell_io_storage.c
+++ b/plat/marvell/armada/common/marvell_io_storage.c
@@ -43,6 +43,15 @@ static const io_uuid_spec_t bl31_uuid_spec = {
 static const io_uuid_spec_t bl32_uuid_spec = {
 	.uuid = UUID_SECURE_PAYLOAD_BL32,
 };
+
+static const io_uuid_spec_t bl32_extra1_uuid_spec = {
+	.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
+};
+
+static const io_uuid_spec_t bl32_extra2_uuid_spec = {
+	.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
+};
+
 static const io_uuid_spec_t bl33_uuid_spec = {
 	.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
 };
@@ -83,6 +92,16 @@ static const struct plat_io_policy policies[] = {
 		(uintptr_t)&bl32_uuid_spec,
 		open_fip
 	},
+	[BL32_EXTRA1_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl32_extra1_uuid_spec,
+		open_fip
+	},
+	[BL32_EXTRA2_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl32_extra2_uuid_spec,
+		open_fip
+	},
 	[BL33_IMAGE_ID] = {
 		&fip_dev_handle,
 		(uintptr_t)&bl33_uuid_spec,
diff --git a/plat/marvell/common/marvell_pm.c b/plat/marvell/armada/common/marvell_pm.c
index 3c675b296..3c675b296 100644
--- a/plat/marvell/common/marvell_pm.c
+++ b/plat/marvell/armada/common/marvell_pm.c
diff --git a/plat/marvell/common/marvell_topology.c b/plat/marvell/armada/common/marvell_topology.c
index a40ff6f50..a40ff6f50 100644
--- a/plat/marvell/common/marvell_topology.c
+++ b/plat/marvell/armada/common/marvell_topology.c
diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index 0291024d7..0291024d7 100644
--- a/plat/marvell/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c
diff --git a/plat/marvell/common/mss/mss_common.mk b/plat/marvell/armada/common/mss/mss_common.mk
index 898b6dccc..4ab43596c 100644
--- a/plat/marvell/common/mss/mss_common.mk
+++ b/plat/marvell/armada/common/mss/mss_common.mk
@@ -6,14 +6,14 @@
 #
 
 
-PLAT_MARVELL		:= 	plat/marvell
+PLAT_MARVELL		:= 	plat/marvell/armada
 MSS_SOURCE		:= 	$(PLAT_MARVELL)/common/mss
 
 BL2_SOURCES		+=	$(MSS_SOURCE)/mss_scp_bootloader.c		\
 				$(PLAT_MARVELL)/common/plat_delay_timer.c	\
 				drivers/delay_timer/delay_timer.c		\
 				$(MARVELL_DRV)					\
-				$(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
+				$(BOARD_DIR)/board/marvell_plat_config.c
 
 BL31_SOURCES		+=	$(MSS_SOURCE)/mss_ipc_drv.c
 
diff --git a/plat/marvell/common/mss/mss_ipc_drv.c b/plat/marvell/armada/common/mss/mss_ipc_drv.c
index 70ccfa5ac..70ccfa5ac 100644
--- a/plat/marvell/common/mss/mss_ipc_drv.c
+++ b/plat/marvell/armada/common/mss/mss_ipc_drv.c
diff --git a/plat/marvell/common/mss/mss_ipc_drv.h b/plat/marvell/armada/common/mss/mss_ipc_drv.h
index bcb4b2d8f..bcb4b2d8f 100644
--- a/plat/marvell/common/mss/mss_ipc_drv.h
+++ b/plat/marvell/armada/common/mss/mss_ipc_drv.h
diff --git a/plat/marvell/common/mss/mss_mem.h b/plat/marvell/armada/common/mss/mss_mem.h
index 5d68ac788..5d68ac788 100644
--- a/plat/marvell/common/mss/mss_mem.h
+++ b/plat/marvell/armada/common/mss/mss_mem.h
diff --git a/plat/marvell/common/mss/mss_scp_bl2_format.h b/plat/marvell/armada/common/mss/mss_scp_bl2_format.h
index 7cf8d3201..74dddc645 100644
--- a/plat/marvell/common/mss/mss_scp_bl2_format.h
+++ b/plat/marvell/armada/common/mss/mss_scp_bl2_format.h
@@ -8,12 +8,11 @@
 #ifndef MSS_SCP_BL2_FORMAT_H
 #define MSS_SCP_BL2_FORMAT_H
 
-#define MAX_NR_OF_FILES	5
+#define MAX_NR_OF_FILES	8
 #define FILE_MAGIC	0xddd01ff
 #define HEADER_VERSION	0x1
 
 #define MSS_IDRAM_SIZE	0x10000 /* 64KB */
-#define MG_SRAM_SIZE	0x20000 /* 128KB */
 
 /* Types definitions */
 typedef struct file_header {
@@ -31,6 +30,7 @@ enum cm3_t {
 	MSS_CP3,
 	MG_CP0,
 	MG_CP1,
+	MG_CP2,
 };
 
 typedef struct img_header {
diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/armada/common/mss/mss_scp_bootloader.c
index 7e442c615..adf570ea9 100644
--- a/plat/marvell/common/mss/mss_scp_bootloader.c
+++ b/plat/marvell/armada/common/mss/mss_scp_bootloader.c
@@ -12,6 +12,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
+#include <mg_conf_cm3/mg_conf_cm3.h>
 #include <lib/mmio.h>
 
 #include <plat_pm_trace.h>
@@ -225,12 +226,20 @@ static int load_img_to_cm3(enum cm3_t cm3_type,
 		}
 		break;
 	case MG_CP0:
-		/* TODO: */
-		NOTICE("Load image to CP0 MG not supported\n");
-		break;
 	case MG_CP1:
-		/* TODO: */
-		NOTICE("Load image to CP1 MG not supported\n");
+	case MG_CP2:
+		cp_index = cm3_type - MG_CP0;
+		if (bl2_plat_get_cp_count(0) <= cp_index) {
+			NOTICE("Skipping MG CP%d related image\n",
+			       cp_index);
+			break;
+		}
+		NOTICE("Load image to CP%d MG\n", cp_index);
+		ret = mg_image_load(single_img, image_size, cp_index);
+		if (ret != 0) {
+			ERROR("SCP Image load failed\n");
+			return -1;
+		}
 		break;
 	default:
 		ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type);
@@ -261,7 +270,7 @@ static int split_and_load_bl2_image(void *image)
 	}
 
 	if (file_hdr->nr_of_imgs > MAX_NR_OF_FILES) {
-		ERROR("SCP_BL2 concatenated image contains to many images\n");
+		ERROR("SCP_BL2 concatenated image contains too many images\n");
 		return -1;
 	}
 
diff --git a/plat/marvell/common/mss/mss_scp_bootloader.h b/plat/marvell/armada/common/mss/mss_scp_bootloader.h
index 4950d2472..4950d2472 100644
--- a/plat/marvell/common/mss/mss_scp_bootloader.h
+++ b/plat/marvell/armada/common/mss/mss_scp_bootloader.h
diff --git a/plat/marvell/common/plat_delay_timer.c b/plat/marvell/armada/common/plat_delay_timer.c
index 253975264..253975264 100644
--- a/plat/marvell/common/plat_delay_timer.c
+++ b/plat/marvell/armada/common/plat_delay_timer.c
diff --git a/plat/marvell/marvell.mk b/plat/marvell/marvell.mk
index d8be0dd17..b6a2b9995 100644
--- a/plat/marvell/marvell.mk
+++ b/plat/marvell/marvell.mk
@@ -16,39 +16,6 @@ $(eval $(call add_define,MARVELL_SECURE_BOOT))
 PALLADIUM			:= 0
 $(eval $(call add_define,PALLADIUM))
 
-ifeq (${MARVELL_SECURE_BOOT},1)
-DOIMAGE_SEC_FLAGS := -c $(DOIMAGE_SEC)
-DOIMAGE_LIBS_CHECK = \
-        if ! [ -d "/usr/include/mbedtls" ]; then \
-                        echo "****************************************" >&2; \
-                        echo "Missing mbedTLS installation! " >&2; \
-                        echo "Please download it from \"tls.mbed.org\"" >&2; \
-			echo "Alternatively on Debian/Ubuntu system install" >&2; \
-			echo "\"libmbedtls-dev\" package" >&2; \
-                        echo "Make sure to use version 2.1.0 or later" >&2; \
-                        echo "****************************************" >&2; \
-                exit 1; \
-        else if ! [ -f "/usr/include/libconfig.h" ]; then \
-                        echo "********************************************************" >&2; \
-                        echo "Missing Libconfig installation!" >&2; \
-                        echo "Please download it from \"www.hyperrealm.com/libconfig/\"" >&2; \
-                        echo "Alternatively on Debian/Ubuntu system install packages" >&2; \
-                        echo "\"libconfig8\" and \"libconfig8-dev\"" >&2; \
-                        echo "********************************************************" >&2; \
-                exit 1; \
-        fi \
-        fi
-else #MARVELL_SECURE_BOOT
-DOIMAGE_LIBS_CHECK =
-DOIMAGE_SEC_FLAGS =
-endif #MARVELL_SECURE_BOOT
-
-mrvl_clean:
-	@echo "  Doimage CLEAN"
-	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
-
-${DOIMAGETOOL}: mrvl_clean
-	@$(DOIMAGE_LIBS_CHECK)
-	${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH} VERSION=$(SUBVERSION) WTMI_IMG=$(WTMI_IMG)
-
-
+# Set board to work with DDR 32bit
+DDR32				:= 0
+$(eval $(call add_define,DDR32))
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
new file mode 100644
index 000000000..0befadfc6
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/mentor/mi2cv.h>
+#include <lib/mmio.h>
+
+#include <mv_ddr_if.h>
+#include <mvebu_def.h>
+#include <plat_marvell.h>
+
+#define MVEBU_CP_MPP_CTRL37_OFFS		20
+#define MVEBU_CP_MPP_CTRL38_OFFS		24
+#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA	0x2
+#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA	0x2
+
+#define MVEBU_MPP_CTRL_MASK			0xf
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+struct mv_ddr_iface dram_iface_ap0 = {
+	.ap_base = MVEBU_REGS_BASE_AP(0),
+	.state = MV_DDR_IFACE_NRDY,
+	.validation = MV_DDR_MEMORY_CHECK,
+	.sscg = SSCG_EN,
+	.id = 0,
+	.iface_base_addr = 0,
+	.tm = {
+		DEBUG_LEVEL_ERROR,
+		0x1, /* active interfaces */
+		/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+		{ { { {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0},
+		      {0x1, 0x0, 0, 0} },
+		   SPEED_BIN_DDR_2400T,		/* speed_bin */
+		   MV_DDR_DEV_WIDTH_8BIT,	/* sdram device width */
+		   MV_DDR_DIE_CAP_8GBIT,	/* die capacity */
+		   MV_DDR_FREQ_SAR,		/* frequency */
+		   0, 0,			/* cas_l, cas_wl */
+		   MV_DDR_TEMP_LOW} },		/* temperature */
+#if DDR32
+		MV_DDR_32BIT_ECC_PUP8_BUS_MASK,	/* subphys mask */
+#else
+		MV_DDR_64BIT_ECC_PUP8_BUS_MASK,	/* subphys mask */
+#endif
+		MV_DDR_CFG_SPD,			/* ddr configuration data src */
+		NOT_COMBINED,			/* ddr twin-die combined*/
+		{ {0} },			/* raw spd data */
+		{0},				/* timing parameters */
+		{	/* electrical configuration */
+			{	/* memory electrical configuration */
+				MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,  /* rtt_nom */
+				{	/* rtt_park 1cs */
+					MV_DDR_RTT_NOM_PARK_RZQ_DIV4,
+					/* rtt_park 2cs */
+					MV_DDR_RTT_NOM_PARK_RZQ_DIV1
+				},
+				{	/* rtt_wr 1cs */
+					MV_DDR_RTT_WR_DYN_ODT_OFF,
+					/* rtt_wr 2cs */
+					MV_DDR_RTT_WR_RZQ_DIV2
+				},
+				MV_DDR_DIC_RZQ_DIV7	/* dic */
+			},
+			{	/* phy electrical configuration */
+				MV_DDR_OHM_30,	/* data_drv_p */
+				MV_DDR_OHM_30,	/* data_drv_n */
+				MV_DDR_OHM_30,	/* ctrl_drv_p */
+				MV_DDR_OHM_30,	/* ctrl_drv_n */
+				{
+					MV_DDR_OHM_60,	/* odt_p 1cs */
+					MV_DDR_OHM_120	/* odt_p 2cs */
+				},
+				{
+					MV_DDR_OHM_60,	/* odt_n 1cs */
+					MV_DDR_OHM_120	/* odt_n 2cs */
+				},
+			},
+			{	/* mac electrical configuration */
+				MV_DDR_ODT_CFG_NORMAL,	/* odtcfg_pattern */
+				MV_DDR_ODT_CFG_ALWAYS_ON,/* odtcfg_write */
+				MV_DDR_ODT_CFG_NORMAL	/* odtcfg_read */
+			},
+		},
+	},
+};
+
+/* Pointer to the first DRAM interface in the system */
+struct mv_ddr_iface *ptr_iface = &dram_iface_ap0;
+
+struct mv_ddr_iface *mv_ddr_iface_get(void)
+{
+	/* Return current ddr interface */
+	return ptr_iface;
+}
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &ptr_iface->tm;
+}
+
+static void mpp_config(void)
+{
+	uintptr_t reg;
+	uint32_t val;
+
+	reg = MVEBU_CP_MPP_REGS(0, 4);
+	/* configure CP0 MPP 37 and 38 to i2c */
+	val = mmio_read_32(reg);
+	val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
+		(MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
+	val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
+			MVEBU_CP_MPP_CTRL37_OFFS) |
+		(MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
+			MVEBU_CP_MPP_CTRL38_OFFS);
+	mmio_write_32(reg, val);
+}
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information received from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+void plat_marvell_dram_update_topology(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	INFO("Gathering DRAM information\n");
+
+	if (tm->cfg_src == MV_DDR_CFG_SPD) {
+		/* configure MPPs to enable i2c */
+		mpp_config();
+
+		/* initialize i2c */
+		i2c_init((void *)MVEBU_CP0_I2C_BASE);
+
+		/* select SPD memory page 0 to access DRAM configuration */
+		i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+
+		/* read data from spd */
+		i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
+			 sizeof(tm->spd_data.all_bytes));
+	}
+}
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c b/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
new file mode 100644
index 000000000..7debd6582
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <armada_common.h>
+#include <mvebu_def.h>
+
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+
+/*****************************************************************************
+ * AMB Configuration
+ *****************************************************************************
+ */
+struct addr_map_win amb_memory_map_cp0[] = {
+	/* CP0 SPI1 CS0 Direct Mode access */
+	{0xe800,	0x2000000,	AMB_SPI1_CS0_ID},
+};
+
+int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
+			       uintptr_t base)
+{
+	switch (base) {
+	case MVEBU_CP_REGS_BASE(0):
+		*win = amb_memory_map_cp0;
+		*size = ARRAY_SIZE(amb_memory_map_cp0);
+		return 0;
+	case MVEBU_CP_REGS_BASE(1):
+	case MVEBU_CP_REGS_BASE(2):
+	default:
+		*size = 0;
+		*win = 0;
+		return 1;
+	}
+}
+#endif
+
+/*****************************************************************************
+ * IO WIN Configuration
+ *****************************************************************************
+ */
+struct addr_map_win io_win_memory_map[] = {
+#ifndef IMAGE_BLE
+	/* SB (MCi0) PCIe0-2 on CP1 */
+	{0x00000000e2000000,		0x3000000,	MCI_0_TID},
+	/* SB (MCi1) PCIe0-2 on CP2 */
+	{0x00000000e5000000,		0x3000000,	MCI_1_TID},
+	/* SB (MCi0) internal regs */
+	{0x00000000f4000000,		0x2000000,	MCI_0_TID},
+	/* SB (MCi1) internal regs */
+	{0x00000000f6000000,		0x2000000,	MCI_1_TID},
+	/* MCI 0 indirect window */
+	{MVEBU_MCI_REG_BASE_REMAP(0),	0x100000,	MCI_0_TID},
+	/* MCI 1 indirect window */
+	{MVEBU_MCI_REG_BASE_REMAP(1),	0x100000,	MCI_1_TID},
+#endif
+};
+
+/* Global Control Register - window default target */
+uint32_t marvell_get_io_win_gcr_target(int ap_index)
+{
+	/*
+	 * PIDI == iMCIP AP to SB internal MoChi connection.
+	 * In other words CP0
+	 */
+	return PIDI_TID;
+}
+
+int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
+				  uint32_t *size)
+{
+	*win = io_win_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = ARRAY_SIZE(io_win_memory_map);
+
+	return 0;
+}
+
+#ifndef IMAGE_BLE
+/*****************************************************************************
+ * IOB Configuration
+ *****************************************************************************
+ */
+struct addr_map_win iob_memory_map_cp0[] = {
+	/* SPI1_CS0 (RUNIT) window */
+	{0x00000000e8000000,	0x2000000,	RUNIT_TID},
+	/* PEX2_X1 window */
+	{0x00000000e1000000,	0x1000000,	PEX2_TID},
+	/* PEX1_X1 window */
+	{0x00000000e0000000,	0x1000000,	PEX1_TID},
+	/* PEX0_X4 window */
+	{0x00000000c0000000,	0x20000000,	PEX0_TID},
+};
+
+struct addr_map_win iob_memory_map_cp1[] = {
+
+	/* PEX2_X1 window */
+	{0x00000000e4000000,	0x1000000,	PEX2_TID},
+	/* PEX1_X1 window */
+	{0x00000000e3000000,	0x1000000,	PEX1_TID},
+	/* PEX0_X4 window */
+	{0x00000000e2000000,	0x1000000,	PEX0_TID},
+};
+
+struct addr_map_win iob_memory_map_cp2[] = {
+
+	/* PEX2_X1 window */
+	{0x00000000e7000000,	0x1000000,	PEX2_TID},
+	/* PEX1_X1 window */
+	{0x00000000e6000000,	0x1000000,	PEX1_TID},
+	/* PEX0_X4 window */
+	{0x00000000e5000000,	0x1000000,	PEX0_TID},
+};
+
+int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
+			       uintptr_t base)
+{
+	switch (base) {
+	case MVEBU_CP_REGS_BASE(0):
+		*win = iob_memory_map_cp0;
+		*size = ARRAY_SIZE(iob_memory_map_cp0);
+		return 0;
+	case MVEBU_CP_REGS_BASE(1):
+		*win = iob_memory_map_cp1;
+		*size = ARRAY_SIZE(iob_memory_map_cp1);
+		return 0;
+	case MVEBU_CP_REGS_BASE(2):
+		*win = iob_memory_map_cp2;
+		*size = ARRAY_SIZE(iob_memory_map_cp2);
+		return 0;
+	default:
+		*size = 0;
+		*win = 0;
+		return 1;
+	}
+}
+#endif
+
+/*****************************************************************************
+ * CCU Configuration
+ *****************************************************************************
+ */
+struct addr_map_win ccu_memory_map[] = {	/* IO window */
+#ifdef IMAGE_BLE
+	{0x00000000f2000000,	0x6000000,	IO_0_TID}, /* IO window */
+#else
+#if LLC_SRAM
+	{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
+#endif
+	{0x00000000f2000000,	0xe000000,	IO_0_TID}, /* IO window */
+	{0x00000000c0000000,	0x30000000,	IO_0_TID}, /* IO window */
+	{0x0000002000000000,	0x70e000000,	IO_0_TID}, /* IO for CV-OS */
+#endif
+};
+
+uint32_t marvell_get_ccu_gcr_target(int ap)
+{
+	return DRAM_0_TID;
+}
+
+int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
+			       uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = ARRAY_SIZE(ccu_memory_map);
+
+	return 0;
+}
+
+#ifdef IMAGE_BLE
+/*****************************************************************************
+ * SKIP IMAGE Configuration
+ *****************************************************************************
+ */
+void *plat_get_skip_image_data(void)
+{
+	/* No recovery button on CN-9130 board? */
+	return NULL;
+}
+#endif
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
new file mode 100644
index 000000000..6b554074c
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef __PHY_PORTING_LAYER_H
+#define __PHY_PORTING_LAYER_H
+
+
+#define MAX_LANE_NR		6
+#define XFI_PARAMS static const struct xfi_params
+
+
+XFI_PARAMS xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+	/* AP0 */
+	{
+		/* CP 0 */
+		{
+			{ 0 }, /* Comphy0 not relevant*/
+			{ 0 }, /* Comphy1 not relevant*/
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
+					.align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c,
+				.g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1,
+				.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
+				.g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
+				.valid = 1 }, /* Comphy2 */
+			{ 0 }, /* Comphy3 not relevant*/
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
+					.align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c,
+				.g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1,
+				.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
+				.g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
+				.valid = 1 }, /* Comphy4 */
+			{ 0 }, /* Comphy5 not relevant*/
+		},
+#if CP_NUM > 1
+		/* CP 1 */
+		{
+			{ 0 }, /* Comphy0 not relevant*/
+			{ 0 }, /* Comphy1 not relevant*/
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
+					.align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c,
+				.g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1,
+				.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
+				.g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
+				.valid = 1 }, /* Comphy2 */
+			{ 0 }, /* Comphy3 not relevant*/
+			/* different from defaults */
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
+					.align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0xc,
+				.g1_emph = 0x5,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1,
+				.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
+				.g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
+				.valid = 1}, /* Comphy4 */
+			{ 0 }, /* Comphy5 not relevant*/
+		},
+#if CP_NUM > 2
+		/* CP 2 */
+		{
+			{ 0 }, /* Comphy0 not relevant*/
+			{ 0 }, /* Comphy1 not relevant*/
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
+					.align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c,
+				.g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1,
+				.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
+				.g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
+				.valid = 1 }, /* Comphy2 */
+			{ 0 }, /* Comphy3 not relevant*/
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
+					.align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c,
+				.g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1,
+				.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
+				.g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
+				.valid = 1 }, /* Comphy4 */
+			{ 0 }, /* Comphy5 not relevant*/
+		},
+#endif
+#endif
+	},
+};
+
+#define SATA_PARAMS static const struct sata_params
+SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+		.g1_amp = 0x8, .g2_amp = 0xa,
+		.g3_amp = 0x1e,
+		.g1_emph = 0x1, .g2_emph = 0x2,
+		.g3_emph = 0xe,
+		.g1_emph_en = 0x1, .g2_emph_en = 0x1,
+		.g3_emph_en = 0x1,
+		.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
+		.g3_tx_amp_adj = 0x1,
+		.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
+		.g3_tx_emph_en = 0x0,
+		.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
+		.g3_tx_emph = 0x1,
+		.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
+		.g3_ffe_cap_sel = 0xf,
+		.align90 = 0x61,
+		.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
+		.g3_rx_selmuff = 0x3,
+		.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
+		.g3_rx_selmufi = 0x3,
+		.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
+		.g3_rx_selmupf = 0x2,
+		.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
+		.g3_rx_selmupi = 0x2,
+		.polarity_invert = COMPHY_POLARITY_NO_INVERT,
+		.valid = 0x1
+	},
+};
+
+static const struct usb_params
+	usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+		.polarity_invert = COMPHY_POLARITY_NO_INVERT
+	},
+};
+#endif /* __PHY_PORTING_LAYER_H */
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h b/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h
new file mode 100644
index 000000000..490be7350
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef __MVEBU_DEF_H__
+#define __MVEBU_DEF_H__
+
+#include <a8k_plat_def.h>
+
+/*
+ * CN-9130 has single CP0 inside the package and 2 additional one
+ * from MoChi interface. In case of db-9130-modular board the MCI interface
+ * is routed to:
+ * - on-board CP115 (MCI0)
+ * - extension board CP115 (MCI1)
+ */
+#define CP_COUNT		CP_NUM
+#define MVEBU_SOC_AP807		1
+#define I2C_SPD_ADDR		0x53	/* Access SPD data */
+#define I2C_SPD_P0_ADDR		0x36	/* Select SPD data page 0 */
+
+#endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/platform.mk b/plat/marvell/octeontx/otx2/t91/t9130/platform.mk
new file mode 100644
index 000000000..1e2716df0
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130/platform.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (C) 2018 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	BSD-3-Clause
+# https://spdx.org/licenses
+#
+
+PCI_EP_SUPPORT		:= 0
+
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
+DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
+
+MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/ap807_setup.c
+
+BOARD_DIR		:= $(shell dirname $(lastword $(MAKEFILE_LIST)))
+include plat/marvell/armada/a8k/common/a8k_common.mk
+
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk
index e072e12d5..bb2225537 100644
--- a/plat/marvell/version.mk
+++ b/plat/marvell/version.mk
@@ -1 +1 @@
-SUBVERSION = devel-18.12.0
+SUBVERSION = devel-18.12.2