diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 1697c55dc..4def14373 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -208,14 +208,20 @@ endfunc cortex_a76_disable_wa_cve_2018_3639 func cortex_a76_reset_func mov x19, x30 + #if WORKAROUND_CVE_2018_3639 + /* If the PE implements SSBS, we don't need the dynamic workaround */ + mrs x0, id_aa64pfr1_el1 + lsr x0, x0, #ID_AA64PFR1_EL1_SSBS_SHIFT + and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK + cbnz x0, 1f + mrs x0, CORTEX_A76_CPUACTLR2_EL1 orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE msr CORTEX_A76_CPUACTLR2_EL1, x0 isb -#endif -#if IMAGE_BL31 && WORKAROUND_CVE_2018_3639 +#ifdef IMAGE_BL31 /* * The Cortex-A76 generic vectors are overwritten to use the vectors * defined above. This is required in order to apply mitigation @@ -226,6 +232,9 @@ func cortex_a76_reset_func isb #endif +1: +#endif + #if ERRATA_DSU_936184 bl errata_dsu_936184_wa #endif |