diff options
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch64/aem_generic.S | 38 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a65.S | 81 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a65ae.S | 81 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_hercules.S | 65 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_hercules_ae.S | 100 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 21 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 93 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_zeus.S | 12 | ||||
| -rw-r--r-- | lib/cpus/aarch64/wa_cve_2017_5715_mmu.S | 4 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 29 |
11 files changed, 502 insertions, 26 deletions
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S index 51b5ce91c..6291e43e1 100644 --- a/lib/cpus/aarch64/aem_generic.S +++ b/lib/cpus/aarch64/aem_generic.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,15 +18,43 @@ func aem_generic_core_pwr_dwn msr sctlr_el3, x1 isb + /* --------------------------------------------- + * AEM model supports L3 caches in which case L2 + * will be private per core caches and flush + * from L1 to L2 is not sufficient. + * --------------------------------------------- + */ + mrs x1, clidr_el1 + + /* --------------------------------------------- + * Check if L3 cache is implemented. + * --------------------------------------------- + */ + tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) + + /* --------------------------------------------- + * There is no L3 cache, flush L1 to L2 only. + * --------------------------------------------- + */ mov x0, #DCCISW + b.eq dcsw_op_level1 + + mov x18, x30 /* --------------------------------------------- - * Flush L1 cache to PoU. + * Flush L1 cache to L2. * --------------------------------------------- */ - b dcsw_op_louis -endfunc aem_generic_core_pwr_dwn + bl dcsw_op_level1 + mov x30, x18 + /* --------------------------------------------- + * Flush L2 cache to L3. + * --------------------------------------------- + */ + mov x0, #DCCISW + b dcsw_op_level2 +endfunc aem_generic_core_pwr_dwn func aem_generic_cluster_pwr_dwn /* --------------------------------------------- @@ -39,7 +67,7 @@ func aem_generic_cluster_pwr_dwn isb /* --------------------------------------------- - * Flush L1 and L2 caches to PoC. + * Flush all caches to PoC. * --------------------------------------------- */ mov x0, #DCCISW diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S new file mode 100644 index 000000000..666324c1e --- /dev/null +++ b/lib/cpus/aarch64/cortex_a65.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> + +#include <asm_macros.S> +#include <common/bl_common.h> +#include <common/debug.h> +#include <cortex_a65.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if !HW_ASSISTED_COHERENCY +#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS +#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +/* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A65. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ +func cortex_a65_reset_func + mov x19, x30 + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + + ret x19 +endfunc cortex_a65_reset_func + +func cortex_a65_cpu_pwr_dwn + mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A65_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a65_cpu_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex-A65. Must follow AAPCS. + */ +func cortex_a65_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a65_errata_report +#endif + +.section .rodata.cortex_a65_regs, "aS" +cortex_a65_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a65_cpu_reg_dump + adr x6, cortex_a65_regs + mrs x8, CORTEX_A65_ECTLR_EL1 + ret +endfunc cortex_a65_cpu_reg_dump + +declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ + cortex_a65_reset_func, \ + cortex_a65_cpu_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S new file mode 100644 index 000000000..ac6583ebc --- /dev/null +++ b/lib/cpus/aarch64/cortex_a65ae.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> + +#include <asm_macros.S> +#include <common/bl_common.h> +#include <common/debug.h> +#include <cortex_a65ae.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if !HW_ASSISTED_COHERENCY +#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS +#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +/* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A65. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ +func cortex_a65ae_reset_func + mov x19, x30 + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + + ret x19 +endfunc cortex_a65ae_reset_func + +func cortex_a65ae_cpu_pwr_dwn + mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a65ae_cpu_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex-A65AE. Must follow AAPCS. + */ +func cortex_a65ae_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a65ae_errata_report +#endif + +.section .rodata.cortex_a65ae_regs, "aS" +cortex_a65ae_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a65ae_cpu_reg_dump + adr x6, cortex_a65ae_regs + mrs x8, CORTEX_A65AE_ECTLR_EL1 + ret +endfunc cortex_a65ae_cpu_reg_dump + +declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \ + cortex_a65ae_reset_func, \ + cortex_a65ae_cpu_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 868667ebc..baefa4676 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -85,7 +85,7 @@ bic x3, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE csel x3, x3, x1, eq msr CORTEX_A76_CPUACTLR2_EL1, x3 - eret /* ERET implies ISB */ + exception_return /* exception_return contains ISB */ .endif 1: /* diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S index 4e048145f..a23919626 100644 --- a/lib/cpus/aarch64/cortex_hercules.S +++ b/lib/cpus/aarch64/cortex_hercules.S @@ -16,12 +16,49 @@ #error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled" #endif + +/* -------------------------------------------------- + * Errata Workaround for Hercules Erratum 1688305. + * This applies to revision r0p0 and r1p0 of Hercules. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_hercules_1688305_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1688305 + cbz x0, 1f + mrs x1, CORTEX_HERCULES_ACTLR2_EL1 + orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1 + msr CORTEX_HERCULES_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_hercules_1688305_wa + +func check_errata_1688305 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1688305 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-Hercules * ------------------------------------------------- */ -#if ENABLE_AMU func cortex_hercules_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_HERCULES_1688305 + mov x0, x18 + bl errata_hercules_1688305_wa +#endif + +#if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT @@ -39,11 +76,11 @@ func cortex_hercules_reset_func /* Enable group1 counters */ mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 - isb +#endif - ret + isb + ret x19 endfunc cortex_hercules_reset_func -#endif /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -66,6 +103,18 @@ endfunc cortex_hercules_core_pwr_dwn */ #if REPORT_ERRATA func cortex_hercules_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305 + + ldp x8, x30, [sp], #16 ret endfunc cortex_hercules_errata_report #endif @@ -89,12 +138,6 @@ func cortex_hercules_cpu_reg_dump ret endfunc cortex_hercules_cpu_reg_dump -#if ENABLE_AMU -#define HERCULES_RESET_FUNC cortex_hercules_reset_func -#else -#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC -#endif - declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \ - HERCULES_RESET_FUNC, \ + cortex_hercules_reset_func, \ cortex_hercules_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_hercules_ae.S new file mode 100644 index 000000000..c4a216353 --- /dev/null +++ b/lib/cpus/aarch64/cortex_hercules_ae.S @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_hercules_ae.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-Hercules-AE + * ------------------------------------------------- + */ +#if ENABLE_AMU +func cortex_hercules_ae_reset_func + /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ + mrs x0, actlr_el3 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el3, x0 + + /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ + mrs x0, actlr_el2 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el2, x0 + + /* Enable group0 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK + msr CPUAMCNTENSET0_EL0, x0 + + /* Enable group1 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK + msr CPUAMCNTENSET1_EL0, x0 + isb + + ret +endfunc cortex_hercules_ae_reset_func +#endif + + /* ------------------------------------------------------- + * HW will do the cache maintenance while powering down + * ------------------------------------------------------- + */ +func cortex_hercules_ae_core_pwr_dwn + /* ------------------------------------------------------- + * Enable CPU power down bit in power control register + * ------------------------------------------------------- + */ + mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hercules_ae_core_pwr_dwn + + /* + * Errata printing function for cortex_hercules_ae. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_hercules_ae_errata_report + ret +endfunc cortex_hercules_ae_errata_report +#endif + + /* ------------------------------------------------------- + * This function provides cortex_hercules_ae specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * ------------------------------------------------------- + */ +.section .rodata.cortex_hercules_ae_regs, "aS" +cortex_hercules_ae_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hercules_ae_cpu_reg_dump + adr x6, cortex_hercules_ae_regs + mrs x8, CORTEX_HERCULES_CPUECTLR_EL1 + ret +endfunc cortex_hercules_ae_cpu_reg_dump + +#if ENABLE_AMU +#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func +#else +#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC +#endif + +declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \ + HERCULES_AE_RESET_FUNC, \ + cortex_hercules_ae_core_pwr_dwn diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index de1177c39..808c7f807 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -227,6 +227,27 @@ func cpu_rev_var_hs ret endfunc cpu_rev_var_hs +/* + * Compare the CPU's revision-variant (x0) with a given range (x1 - x2), for errata + * application purposes. If the revision-variant is between or includes the given + * values, this indicates that errata applies; otherwise not. + * + * Shall clobber: x0-x4 + */ + .globl cpu_rev_var_range +func cpu_rev_var_range + mov x3, #ERRATA_APPLIES + mov x4, #ERRATA_NOT_APPLIES + cmp x0, x1 + csel x1, x3, x4, hs + cbz x1, 1f + cmp x0, x2 + csel x1, x3, x4, ls +1: + mov x0, x1 + ret +endfunc cpu_rev_var_range + #if REPORT_ERRATA /* * void print_errata_status(void); diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index b143a2e7b..d537ed6a8 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <neoverse_n1.h> #include <cpuamu.h> #include <cpu_macros.S> +#include <context.h> /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 @@ -20,6 +21,8 @@ #error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif + .global neoverse_n1_errata_ic_trap_handler + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1043202. * This applies to revision r0p0 and r1p0 of Neoverse N1. @@ -43,6 +46,7 @@ func errata_n1_1043202_wa msr CPUPMR_EL3, x0 ldr x0, =0x800200071 msr CPUPCR_EL3, x0 + isb 1: ret x17 endfunc errata_n1_1043202_wa @@ -336,6 +340,41 @@ func check_errata_1315703 b cpu_rev_var_ls endfunc check_errata_1315703 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Erratum 1542419. + * This applies to revisions r3p0 - r4p0 of Neoverse N1 + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1542419_wa + /* Compare x0 against revision r3p0 and r4p0 */ + mov x17, x30 + bl check_errata_1542419 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0, =0x0 + msr CPUPSELR_EL3, x0 + ldr x0, =0xEE670D35 + msr CPUPOR_EL3, x0 + ldr x0, =0xFFFF0FFF + msr CPUPMR_EL3, x0 + ldr x0, =0x08000020007D + msr CPUPCR_EL3, x0 + isb +1: + ret x17 +endfunc errata_n1_1542419_wa + +func check_errata_1542419 + /* Applies to everything r3p0 - r4p0. */ + mov x1, #0x30 + mov x2, #0x40 + b cpu_rev_var_range +endfunc check_errata_1542419 + func neoverse_n1_reset_func mov x19, x30 @@ -405,6 +444,11 @@ func neoverse_n1_reset_func bl errata_n1_1315703_wa #endif +#if ERRATA_N1_1542419 + mov x0, x18 + bl errata_n1_1542419_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -421,6 +465,13 @@ func neoverse_n1_reset_func msr CPUAMCNTENSET_EL0, x0 #endif +#if NEOVERSE_N1_EXTERNAL_LLC + /* Some system may have External LLC, core needs to be made aware */ + mrs x0, NEOVERSE_N1_CPUECTLR_EL1 + orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT + msr NEOVERSE_N1_CPUECTLR_EL1, x0 +#endif + #if ERRATA_DSU_936184 bl errata_dsu_936184_wa #endif @@ -470,6 +521,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 + report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 ldp x8, x30, [sp], #16 @@ -477,6 +529,42 @@ func neoverse_n1_errata_report endfunc neoverse_n1_errata_report #endif +/* + * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB + * inner-shareable invalidation to an arbitrary address followed by a DSB. + * + * x1: Exception Syndrome + */ +func neoverse_n1_errata_ic_trap_handler + cmp x1, #NEOVERSE_N1_EC_IC_TRAP + b.ne 1f + tlbi vae3is, xzr + dsb sy + + # Skip the IC instruction itself + mrs x3, elr_el3 + add x3, x3, #4 + msr elr_el3, x3 + + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + +#if IMAGE_BL31 && RAS_EXTENSION + /* + * Issue Error Synchronization Barrier to synchronize SErrors before + * exiting EL3. We're running with EAs unmasked, so any synchronized + * errors would be taken immediately; therefore no need to inspect + * DISR_EL1 register. + */ + esb +#endif + exception_return +1: + ret +endfunc neoverse_n1_errata_ic_trap_handler + /* --------------------------------------------- * This function provides neoverse_n1 specific * register information for crash reporting. @@ -496,6 +584,7 @@ func neoverse_n1_cpu_reg_dump ret endfunc neoverse_n1_cpu_reg_dump -declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ +declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ neoverse_n1_reset_func, \ + neoverse_n1_errata_ic_trap_handler, \ neoverse_n1_core_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S index 3d850137c..44882b459 100644 --- a/lib/cpus/aarch64/neoverse_zeus.S +++ b/lib/cpus/aarch64/neoverse_zeus.S @@ -46,6 +46,16 @@ func neoverse_zeus_errata_report endfunc neoverse_zeus_errata_report #endif +func neoverse_zeus_reset_func + mov x19, x30 + + /* Disable speculative loads */ + msr SSBS, xzr + + isb + ret x19 +endfunc neoverse_zeus_reset_func + /* --------------------------------------------- * This function provides Neoverse-Zeus specific * register information for crash reporting. @@ -66,5 +76,5 @@ func neoverse_zeus_cpu_reg_dump endfunc neoverse_zeus_cpu_reg_dump declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \ - CPU_NO_RESET_FUNC, \ + neoverse_zeus_reset_func, \ neoverse_zeus_core_pwr_dwn diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S index 9277cc624..5134ee3f1 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,7 +48,7 @@ vector_base wa_cve_2017_5715_mmu_vbar ccmp w0, w1, #0, eq /* Static predictor will predict a fall through */ bne 1f - eret + exception_return 1: .endif diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 260402351..e3bfc2f2e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -20,6 +20,10 @@ WORKAROUND_CVE_2017_5715 ?=1 WORKAROUND_CVE_2018_3639 ?=1 DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0 +# Flag to indicate internal or external Last level cache +# By default internal +NEOVERSE_N1_EXTERNAL_LLC ?=0 + # Process SKIP_A57_L1_FLUSH_PWR_DWN flag $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) @@ -43,6 +47,9 @@ $(eval $(call add_define,WORKAROUND_CVE_2018_3639)) $(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639)) $(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639)) +$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC)) +$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC)) + ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0) ifeq (${WORKAROUND_CVE_2018_3639},0) $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") @@ -234,9 +241,13 @@ ERRATA_A76_1275112 ?=0 # only to revision <= r3p0 of the Cortex A76 cpu. ERRATA_A76_1286807 ?=0 +# Flag to apply erratum 1688305 workaround during reset. This erratum applies +# to revisions r0p0 - r1p0 of the Hercules cpu. +ERRATA_HERCULES_1688305 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. -ERRATA_N1_1043202 ?=1 +ERRATA_N1_1043202 ?=0 # Flag to apply erratum 1073348 workaround during reset. This erratum applies # only to revision r0p0 and r1p0 of the Neoverse N1 cpu. @@ -276,7 +287,11 @@ ERRATA_N1_1275112 ?=0 # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. -ERRATA_N1_1315703 ?=1 +ERRATA_N1_1315703 ?=0 + +# Flag to apply erratum 1542419 workaround during reset. This erratum applies +# to revisions r3p0 - r4p0 of the Neoverse N1 cpu. +ERRATA_N1_1542419 ?=0 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. @@ -463,6 +478,10 @@ $(eval $(call add_define,ERRATA_A76_1275112)) $(eval $(call assert_boolean,ERRATA_A76_1286807)) $(eval $(call add_define,ERRATA_A76_1286807)) +# Process ERRATA_HERCULES_1688305 flag +$(eval $(call assert_boolean,ERRATA_HERCULES_1688305)) +$(eval $(call add_define,ERRATA_HERCULES_1688305)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) @@ -507,6 +526,10 @@ $(eval $(call add_define,ERRATA_N1_1275112)) $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) +# Process ERRATA_N1_1542419 flag +$(eval $(call assert_boolean,ERRATA_N1_1542419)) +$(eval $(call add_define,ERRATA_N1_1542419)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) |