diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cpu_macros.S | 21 | ||||
| -rw-r--r-- | include/lib/cpus/wa_cve_2018_3639.h | 12 | ||||
| -rw-r--r-- | include/lib/el3_runtime/aarch64/context.h | 15 |
3 files changed, 42 insertions, 6 deletions
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index bfe2449e9..cd8f3e8fb 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -18,6 +18,9 @@ /* Special constant to specify that CPU has no reset function */ #define CPU_NO_RESET_FUNC 0 +#define CPU_NO_EXTRA1_FUNC 0 +#define CPU_NO_EXTRA2_FUNC 0 + /* Word size for 64-bit CPUs */ #define CPU_WORD_SIZE 8 @@ -48,6 +51,8 @@ CPU_RESET_FUNC: /* cpu_ops reset_func */ #endif CPU_EXTRA1_FUNC: .space 8 +CPU_EXTRA2_FUNC: + .space 8 #ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ CPU_PWR_DWN_OPS: /* cpu_ops power down functions */ .space (8 * CPU_MAX_PWR_DWN_OPS) @@ -119,6 +124,10 @@ CPU_OPS_SIZE = . * This is a placeholder for future per CPU operations. Currently, * some CPUs use this entry to set a test function to determine if * the workaround for CVE-2017-5715 needs to be applied or not. + * _extra2: + * This is a placeholder for future per CPU operations. Currently + * some CPUs use this entry to set a function to disable the + * workaround for CVE-2018-3639. * _power_down_ops: * Comma-separated list of functions to perform power-down * operatios on the CPU. At least one, and up to @@ -129,7 +138,7 @@ CPU_OPS_SIZE = . * used to handle power down at subsequent levels */ .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ - _extra1:req, _power_down_ops:vararg + _extra1:req, _extra2:req, _power_down_ops:vararg .section cpu_ops, "a" .align 3 .type cpu_ops_\_name, %object @@ -138,6 +147,7 @@ CPU_OPS_SIZE = . .quad \_resetfunc #endif .quad \_extra1 + .quad \_extra2 #ifdef IMAGE_BL31 1: /* Insert list of functions */ @@ -196,14 +206,15 @@ CPU_OPS_SIZE = . .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ _power_down_ops:vararg - declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, \ + declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \ \_power_down_ops .endm - .macro declare_cpu_ops_workaround_cve_2017_5715 _name:req, _midr:req, \ - _resetfunc:req, _extra1:req, _power_down_ops:vararg + .macro declare_cpu_ops_wa _name:req, _midr:req, \ + _resetfunc:req, _extra1:req, _extra2:req, \ + _power_down_ops:vararg declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ - \_extra1, \_power_down_ops + \_extra1, \_extra2, \_power_down_ops .endm #if REPORT_ERRATA diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h new file mode 100644 index 000000000..36546f70d --- /dev/null +++ b/include/lib/cpus/wa_cve_2018_3639.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WA_CVE_2018_3639_H__ +#define __WA_CVE_2018_3639_H__ + +void *wa_cve_2018_3639_get_disable_ptr(void); + +#endif /* __WA_CVE_2018_3639_H__ */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index cdd74a34c..a4f3ea1bb 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -128,8 +128,8 @@ * Constants that allow assembler code to access members of and the 'fp_regs' * structure at their correct offsets. ******************************************************************************/ -#if CTX_INCLUDE_FPREGS #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) +#if CTX_INCLUDE_FPREGS #define CTX_FP_Q0 U(0x0) #define CTX_FP_Q1 U(0x10) #define CTX_FP_Q2 U(0x20) @@ -170,8 +170,14 @@ #else #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ #endif +#else +#define CTX_FPREGS_END U(0) #endif +#define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) +#define CTX_CVE_2018_3639_DISABLE U(0) +#define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ + #ifndef __ASSEMBLY__ #include <cassert.h> @@ -195,6 +201,7 @@ #define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) #endif #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) +#define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) /* * AArch64 general purpose register context structure. Usually x0-x18, @@ -227,6 +234,9 @@ DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); */ DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); +/* Function pointer used by CVE-2018-3639 dynamic mitigation */ +DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); + /* * Macros to access members of any of the above structures using their * offsets @@ -251,6 +261,7 @@ typedef struct cpu_context { #if CTX_INCLUDE_FPREGS fp_regs_t fpregs_ctx; #endif + cve_2018_3639_t cve_2018_3639_ctx; } cpu_context_t; /* Macros to access members of the 'cpu_context_t' structure */ @@ -276,6 +287,8 @@ CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ #endif CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ assert_core_context_el3state_offset_mismatch); +CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ + assert_core_context_cve_2018_3639_offset_mismatch); /* * Helper macro to set the general purpose registers that correspond to |