diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/st/stm32_i2c.h | 258 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_clk.h | 43 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_clkfunc.h | 13 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_rcc.h | 3 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_reset.h | 15 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp_clkfunc.h | 25 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp_pmic.h | 37 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp_reset.h | 15 |
8 files changed, 247 insertions, 162 deletions
diff --git a/include/drivers/st/stm32_i2c.h b/include/drivers/st/stm32_i2c.h index de2ca59c8..170d4cf81 100644 --- a/include/drivers/st/stm32_i2c.h +++ b/include/drivers/st/stm32_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -111,94 +111,113 @@ #define I2C_ICR_TIMOUTCF BIT(12) #define I2C_ICR_ALERTCF BIT(13) -struct stm32_i2c_init_s { - uint32_t timing; /* Specifies the I2C_TIMINGR_register value - * This parameter is calculated by referring - * to I2C initialization section in Reference - * manual. - */ - - uint32_t own_address1; /* Specifies the first device own address. - * This parameter can be a 7-bit or 10-bit - * address. - */ - - uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing - * mode is selected. - * This parameter can be a value of @ref - * I2C_ADDRESSING_MODE. - */ - - uint32_t dual_address_mode; /* Specifies if dual addressing mode is - * selected. - * This parameter can be a value of @ref - * I2C_DUAL_ADDRESSING_MODE. - */ - - uint32_t own_address2; /* Specifies the second device own address - * if dual addressing mode is selected. - * This parameter can be a 7-bit address. - */ - - uint32_t own_address2_masks; /* Specifies the acknowledge mask address - * second device own address if dual - * addressing mode is selected. - * This parameter can be a value of @ref - * I2C_OWN_ADDRESS2_MASKS. - */ - - uint32_t general_call_mode; /* Specifies if general call mode is - * selected. - * This parameter can be a value of @ref - * I2C_GENERAL_CALL_ADDRESSING_MODE. - */ - - uint32_t no_stretch_mode; /* Specifies if nostretch mode is - * selected. - * This parameter can be a value of @ref - * I2C_NOSTRETCH_MODE. - */ +enum i2c_speed_e { + I2C_SPEED_STANDARD, /* 100 kHz */ + I2C_SPEED_FAST, /* 400 kHz */ + I2C_SPEED_FAST_PLUS, /* 1 MHz */ +}; + +#define STANDARD_RATE 100000 +#define FAST_RATE 400000 +#define FAST_PLUS_RATE 1000000 +struct stm32_i2c_init_s { + uint32_t own_address1; /* + * Specifies the first device own + * address. This parameter can be a + * 7-bit or 10-bit address. + */ + + uint32_t addressing_mode; /* + * Specifies if 7-bit or 10-bit + * addressing mode is selected. + * This parameter can be a value of + * @ref I2C_ADDRESSING_MODE. + */ + + uint32_t dual_address_mode; /* + * Specifies if dual addressing mode is + * selected. + * This parameter can be a value of @ref + * I2C_DUAL_ADDRESSING_MODE. + */ + + uint32_t own_address2; /* + * Specifies the second device own + * address if dual addressing mode is + * selected. This parameter can be a + * 7-bit address. + */ + + uint32_t own_address2_masks; /* + * Specifies the acknowledge mask + * address second device own address + * if dual addressing mode is selected + * This parameter can be a value of @ref + * I2C_OWN_ADDRESS2_MASKS. + */ + + uint32_t general_call_mode; /* + * Specifies if general call mode is + * selected. + * This parameter can be a value of @ref + * I2C_GENERAL_CALL_ADDRESSING_MODE. + */ + + uint32_t no_stretch_mode; /* + * Specifies if nostretch mode is + * selected. + * This parameter can be a value of @ref + * I2C_NOSTRETCH_MODE. + */ + + uint32_t rise_time; /* + * Specifies the SCL clock pin rising + * time in nanoseconds. + */ + + uint32_t fall_time; /* + * Specifies the SCL clock pin falling + * time in nanoseconds. + */ + + enum i2c_speed_e speed_mode; /* + * Specifies the I2C clock source + * frequency mode. + * This parameter can be a value of @ref + * i2c_speed_mode_e. + */ + + int analog_filter; /* + * Specifies if the I2C analog noise + * filter is selected. + * This parameter can be 0 (filter + * off), all other values mean filter + * on. + */ + + uint8_t digital_filter_coef; /* + * Specifies the I2C digital noise + * filter coefficient. + * This parameter can be a value + * between 0 and + * STM32_I2C_DIGITAL_FILTER_MAX. + */ }; enum i2c_state_e { - I2C_STATE_RESET = 0x00U, /* Peripheral is not yet - * initialized. - */ - I2C_STATE_READY = 0x20U, /* Peripheral Initialized - * and ready for use. - */ - I2C_STATE_BUSY = 0x24U, /* An internal process is - * ongoing. - */ - I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process - * is ongoing. - */ - I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process - * is ongoing. - */ - I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is - * ongoing. - */ - I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode - * and Data Transmission - * process is ongoing. - */ - I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode - * and Data Reception - * process is ongoing. - */ - I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */ - I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */ - I2C_STATE_ERROR = 0xE0U /* Error. */ - + I2C_STATE_RESET = 0x00U, /* Not yet initialized */ + I2C_STATE_READY = 0x20U, /* Ready for use */ + I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */ + I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */ + I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */ }; enum i2c_mode_e { - I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */ - I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */ - I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */ - I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */ + I2C_MODE_NONE = 0x00U, /* No active communication */ + I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */ + I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */ + I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */ }; @@ -213,26 +232,12 @@ enum i2c_mode_e { struct i2c_handle_s { uint32_t i2c_base_addr; /* Registers base address */ - - struct stm32_i2c_init_s i2c_init; /* Communication parameters */ - - uint8_t *p_buff; /* Pointer to transfer buffer */ - - uint16_t xfer_size; /* Transfer size */ - - uint16_t xfer_count; /* Transfer counter */ - - uint32_t prev_state; /* Communication previous - * state - */ - - uint8_t lock; /* Locking object */ - - enum i2c_state_e i2c_state; /* Communication state */ - - enum i2c_mode_e i2c_mode; /* Communication mode */ - - uint32_t i2c_err; /* Error code */ + unsigned int dt_status; /* DT nsec/sec status */ + unsigned int clock; /* Clock reference */ + uint8_t lock; /* Locking object */ + enum i2c_state_e i2c_state; /* Communication state */ + enum i2c_mode_e i2c_mode; /* Communication mode */ + uint32_t i2c_err; /* Error code */ }; #define I2C_ADDRESSINGMODE_7BIT 0x00000001U @@ -250,15 +255,15 @@ struct i2c_handle_s { #define I2C_MEMADD_SIZE_8BIT 0x00000001U #define I2C_MEMADD_SIZE_16BIT 0x00000002U -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE 0x00000000U +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE 0x00000000U -#define I2C_NO_STARTSTOP 0x00000000U -#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) -#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ +#define I2C_NO_STARTSTOP 0x00000000U +#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) +#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) #define I2C_FLAG_TXE I2C_ISR_TXE #define I2C_FLAG_TXIS I2C_ISR_TXIS @@ -281,21 +286,36 @@ struct i2c_handle_s { I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ I2C_CR2_RD_WRN) -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +#define I2C_TIMEOUT_BUSY_MS 25U -int stm32_i2c_init(struct i2c_handle_s *hi2c); +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/* STM32 specific defines */ +#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ +#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ +#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD +#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ +#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ +#define STM32_I2C_DIGITAL_FILTER_MAX 16 + +int stm32_i2c_get_setup_from_fdt(void *fdt, int node, + struct stm32_i2c_init_s *init); +int stm32_i2c_init(struct i2c_handle_s *hi2c, + struct stm32_i2c_init_s *init_data); int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr, uint16_t mem_addr, uint16_t mem_add_size, - uint8_t *p_data, uint16_t size, uint32_t timeout); + uint8_t *p_data, uint16_t size, uint32_t timeout_ms); int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, uint16_t mem_addr, uint16_t mem_add_size, - uint8_t *p_data, uint16_t size, uint32_t timeout); -int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr, - uint32_t trials, uint32_t timeout); - -int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c, - uint32_t analog_filter); + uint8_t *p_data, uint16_t size, uint32_t timeout_ms); +int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint8_t *p_data, uint16_t size, + uint32_t timeout_ms); +int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint8_t *p_data, uint16_t size, + uint32_t timeout_ms); +bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint32_t trials, uint32_t timeout_ms); #endif /* STM32_I2C_H */ diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index 5594e2327..1e0d949ac 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,25 +7,42 @@ #ifndef STM32MP1_CLK_H #define STM32MP1_CLK_H -#include <stdbool.h> - #include <arch_helpers.h> int stm32mp1_clk_probe(void); int stm32mp1_clk_init(void); -bool stm32mp1_clk_is_enabled(unsigned long id); -int stm32mp1_clk_enable(unsigned long id); -int stm32mp1_clk_disable(unsigned long id); -unsigned long stm32mp1_clk_get_rate(unsigned long id); -void stm32mp1_stgen_increment(unsigned long long offset_in_ms); -static inline uint32_t get_timer(uint32_t base) +bool stm32mp1_rcc_is_secure(void); + +void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure); +void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure); + +static inline void stm32mp1_clk_enable_non_secure(unsigned long id) +{ + __stm32mp1_clk_enable(id, false); +} + +static inline void stm32mp1_clk_enable_secure(unsigned long id) +{ + __stm32mp1_clk_enable(id, true); +} + +static inline void stm32mp1_clk_disable_non_secure(unsigned long id) { - if (base == 0U) { - return (uint32_t)(~read_cntpct_el0()); - } + __stm32mp1_clk_disable(id, false); +} - return base - (uint32_t)(~read_cntpct_el0()); +static inline void stm32mp1_clk_disable_secure(unsigned long id) +{ + __stm32mp1_clk_disable(id, true); } +unsigned int stm32mp1_clk_get_refcount(unsigned long id); + +/* SMP protection on RCC registers access */ +void stm32mp1_clk_rcc_regs_lock(void); +void stm32mp1_clk_rcc_regs_unlock(void); + +void stm32mp1_stgen_increment(unsigned long long offset_in_ms); + #endif /* STM32MP1_CLK_H */ diff --git a/include/drivers/st/stm32mp1_clkfunc.h b/include/drivers/st/stm32mp1_clkfunc.h index 106dcae01..f30393734 100644 --- a/include/drivers/st/stm32mp1_clkfunc.h +++ b/include/drivers/st/stm32mp1_clkfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,6 @@ enum stm32mp_osc_id { _LSI, _LSE, _I2S_CKIN, - _USB_PHY_48, NB_OSC, _UNKNOWN_OSC_ID = 0xFF }; @@ -31,14 +30,4 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, const char *prop_name, uint32_t dflt_value); -uint32_t fdt_rcc_read_addr(void); -int fdt_rcc_read_uint32_array(const char *prop_name, - uint32_t *array, uint32_t count); -int fdt_rcc_subnode_offset(const char *name); -const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); -bool fdt_get_rcc_secure_status(void); - -uintptr_t fdt_get_stgen_base(void); -int fdt_get_clock_id(int node); - #endif /* STM32MP1_CLKFUNC_H */ diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 2f29e84d5..1922c4815 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -280,6 +280,9 @@ /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ #define RCC_MP_ENCLRR_OFFSET U(4) +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + /* Fields of RCC_BDCR register */ #define RCC_BDCR_LSEON BIT(0) #define RCC_BDCR_LSEBYP BIT(1) diff --git a/include/drivers/st/stm32mp1_reset.h b/include/drivers/st/stm32mp1_reset.h deleted file mode 100644 index cd488cc33..000000000 --- a/include/drivers/st/stm32mp1_reset.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP1_RESET_H -#define STM32MP1_RESET_H - -#include <stdint.h> - -void stm32mp1_reset_assert(uint32_t reset_id); -void stm32mp1_reset_deassert(uint32_t reset_id); - -#endif /* STM32MP1_RESET_H */ diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h new file mode 100644 index 000000000..5beb06bb2 --- /dev/null +++ b/include/drivers/st/stm32mp_clkfunc.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_CLKFUNC_H +#define STM32MP_CLKFUNC_H + +#include <stdbool.h> + +#include <libfdt.h> + +int fdt_get_rcc_node(void *fdt); +uint32_t fdt_rcc_read_addr(void); +int fdt_rcc_read_uint32_array(const char *prop_name, + uint32_t *array, uint32_t count); +int fdt_rcc_subnode_offset(const char *name); +const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); +bool fdt_get_rcc_secure_status(void); + +uintptr_t fdt_get_stgen_base(void); +int fdt_get_clock_id(int node); + +#endif /* STM32MP_CLKFUNC_H */ diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h index 700039b26..984cd6014 100644 --- a/include/drivers/st/stm32mp_pmic.h +++ b/include/drivers/st/stm32mp_pmic.h @@ -11,10 +11,41 @@ #include <platform_def.h> -bool dt_check_pmic(void); -int dt_pmic_enable_boot_on_regulators(void); -void initialize_pmic_i2c(void); +/* + * dt_pmic_status - Check PMIC status from device tree + * + * Returns the status of the PMIC (secure, non-secure), or a negative value on + * error + */ +int dt_pmic_status(void); + +/* + * dt_pmic_configure_boot_on_regulators - Configure boot-on and always-on + * regulators from device tree configuration + * + * Returns 0 on success, and negative values on errors + */ +int dt_pmic_configure_boot_on_regulators(void); + +/* + * initialize_pmic_i2c - Initialize I2C for the PMIC control + * + * Returns true if PMIC is available, false if not found, panics on errors + */ +bool initialize_pmic_i2c(void); + +/* + * initialize_pmic - Main PMIC initialization function, called at platform init + * + * Panics on errors + */ void initialize_pmic(void); + +/* + * pmic_ddr_power_init - Initialize regulators required for DDR + * + * Returns 0 on success, and negative values on errors + */ int pmic_ddr_power_init(enum ddr_type ddr_type); #endif /* STM32MP_PMIC_H */ diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h new file mode 100644 index 000000000..2da5adf44 --- /dev/null +++ b/include/drivers/st/stm32mp_reset.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_RESET_H +#define STM32MP_RESET_H + +#include <stdint.h> + +void stm32mp_reset_assert(uint32_t reset_id); +void stm32mp_reset_deassert(uint32_t reset_id); + +#endif /* STM32MP_RESET_H */ |