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-rw-r--r--include/arch/aarch32/arch.h20
-rw-r--r--include/arch/aarch64/arch.h4
-rw-r--r--include/lib/smccc.h22
-rw-r--r--include/lib/utils_def.h4
4 files changed, 27 insertions, 23 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 20175481f..8492b3ea4 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -388,13 +388,17 @@
#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
-#define SPSR_MODE32(mode, isa, endian, aif) \
- ((MODE_RW_32 << MODE_RW_SHIFT | \
- ((mode) & MODE32_MASK) << MODE32_SHIFT | \
- ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
- ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
- ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \
- (~(SPSR_SSBS_BIT)))
+#define SPSR_MODE32(mode, isa, endian, aif) \
+( \
+ ( \
+ (MODE_RW_32 << MODE_RW_SHIFT) | \
+ (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
+ (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
+ (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
+ (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \
+ ) & \
+ (~(SPSR_SSBS_BIT)) \
+)
/*
* TTBR definitions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 2b2c11652..19dd8c5e3 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -264,8 +264,8 @@
(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
(U(1) << 11) | (U(1) << 5) | (U(1) << 4))
-#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
- (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
+#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
+ (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
#define SCTLR_AARCH32_EL1_RES1 \
((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
(U(1) << 4) | (U(1) << 3))
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 5e13e6f0a..26509aeca 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -122,18 +122,18 @@
*/
#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
_n0, _n1, _n2, _n3, _n4, _n5) \
- CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
+ CASSERT((uint32_t)(_tl) != (uint32_t)SMC_UNK, invalid_svc_uuid);\
static const uuid_t _name = { \
- {(_tl >> 24) & 0xFF, \
- (_tl >> 16) & 0xFF, \
- (_tl >> 8) & 0xFF, \
- (_tl & 0xFF)}, \
- {(_tm >> 8) & 0xFF, \
- (_tm & 0xFF)}, \
- {(_th >> 8) & 0xFF, \
- (_th & 0xFF)}, \
- _cl, _ch, \
- { _n0, _n1, _n2, _n3, _n4, _n5 } \
+ {((_tl) >> 24) & 0xFF, \
+ ((_tl) >> 16) & 0xFF, \
+ ((_tl) >> 8) & 0xFF, \
+ ((_tl) & 0xFF)}, \
+ {((_tm) >> 8) & 0xFF, \
+ ((_tm) & 0xFF)}, \
+ {((_th) >> 8) & 0xFF, \
+ ((_th) & 0xFF)}, \
+ (_cl), (_ch), \
+ { (_n0), (_n1), (_n2), (_n3), (_n4), (_n5) } \
}
/*
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 09ae3999d..2d0e9c08e 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -17,7 +17,7 @@
#define IS_POWER_OF_TWO(x) \
(((x) & ((x) - 1)) == 0)
-#define SIZE_FROM_LOG2_WORDS(n) (4 << (n))
+#define SIZE_FROM_LOG2_WORDS(n) (U(4) << (n))
#define BIT_32(nr) (U(1) << (nr))
#define BIT_64(nr) (ULL(1) << (nr))