diff options
Diffstat (limited to 'include')
107 files changed, 1920 insertions, 1434 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 34036d785..20175481f 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -162,6 +162,7 @@ #define SDCR_SPD_DISABLE U(0x2) #define SDCR_SPD_ENABLE U(0x3) #define SDCR_SCCD_BIT (U(1) << 23) +#define SDCR_SPME_BIT (U(1) << 17) #define SDCR_RESET_VAL U(0x0) /* HSCTLR definitions */ @@ -243,6 +244,8 @@ #define VTTBR_BADDR_SHIFT U(0) /* HDCR definitions */ +#define HDCR_HLP_BIT (U(1) << 26) +#define HDCR_HPME_BIT (U(1) << 7) #define HDCR_RESET_VAL U(0x0) /* HSTR definitions */ @@ -419,8 +422,10 @@ #define PMCR_N_SHIFT U(11) #define PMCR_N_MASK U(0x1f) #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) +#define PMCR_LP_BIT (U(1) << 7) #define PMCR_LC_BIT (U(1) << 6) #define PMCR_DP_BIT (U(1) << 5) +#define PMCR_RESET_VAL U(0x0) /******************************************************************************* * Definitions of register offsets, fields and macros for CPU system diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 0bd897814..7559de446 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -112,15 +112,41 @@ * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from * Secure EL1 are disabled. * - * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in - * Secure state. This bit is RES0 in versions of the architecture + * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited + * in Secure state. This bit is RES0 in versions of the architecture * earlier than ARMv8.5, setting it to 1 doesn't have any effect on * them. * --------------------------------------------------------------------- */ ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) stcopr r0, SDCR + + /* --------------------------------------------------------------------- + * Initialise PMCR, setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR.LP: Set to one so that event counter overflow, that + * is recorded in PMOVSCLR[0-30], occurs on the increment + * that changes PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU + * is implemented. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5, setting it to 1 doesn't have any effect + * on them. + * This bit is Reserved, UNK/SBZP in ARMv7. + * + * PMCR.LC: Set to one so that cycle counter overflow, that + * is recorded in PMOVSCLR[31], occurs on the increment + * that changes PMCCNTR[63] from 1 to 0. + * This bit is Reserved, UNK/SBZP in ARMv7. + * + * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode. + * --------------------------------------------------------------------- + */ + ldr r0, =(PMCR_RESET_VAL | PMCR_DP_BIT | PMCR_LC_BIT | \ + PMCR_LP_BIT) +#else + ldr r0, =(PMCR_RESET_VAL | PMCR_DP_BIT) #endif + stcopr r0, PMCR /* * If Data Independent Timing (DIT) functionality is implemented, @@ -313,7 +339,7 @@ bl zeromem #endif -#ifdef IMAGE_BL1 +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) /* ----------------------------------------------------- * Copy data from ROM to RAM. * ----------------------------------------------------- diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h index b2ee3cfe0..2ce7874ef 100644 --- a/include/arch/aarch32/smccc_helpers.h +++ b/include/arch/aarch32/smccc_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -130,6 +130,22 @@ CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); ((smc_ctx_t *)(_h))->r3 = (_r3); \ SMC_RET3(_h, (_r0), (_r1), (_r2)); \ } +#define SMC_RET5(_h, _r0, _r1, _r2, _r3, _r4) { \ + ((smc_ctx_t *)(_h))->r4 = (_r4); \ + SMC_RET4(_h, (_r0), (_r1), (_r2), (_r3)); \ +} +#define SMC_RET6(_h, _r0, _r1, _r2, _r3, _r4, _r5) { \ + ((smc_ctx_t *)(_h))->r5 = (_r5); \ + SMC_RET5(_h, (_r0), (_r1), (_r2), (_r3), (_r4)); \ +} +#define SMC_RET7(_h, _r0, _r1, _r2, _r3, _r4, _r5, _r6) { \ + ((smc_ctx_t *)(_h))->r6 = (_r6); \ + SMC_RET6(_h, (_r0), (_r1), (_r2), (_r3), (_r4), (_r5)); \ +} +#define SMC_RET8(_h, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) { \ + ((smc_ctx_t *)(_h))->r7 = (_r7); \ + SMC_RET7(_h, (_r0), (_r1), (_r2), (_r3), (_r4), (_r5), (_r6)); \ +} /* * Helper macro to retrieve the SMC parameters from smc_ctx_t. diff --git a/include/arch/aarch32/smccc_macros.S b/include/arch/aarch32/smccc_macros.S index 1fe6c64dc..4ec229218 100644 --- a/include/arch/aarch32/smccc_macros.S +++ b/include/arch/aarch32/smccc_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,7 +58,6 @@ stm r0!, {r2} stcopr r4, SCR - isb #else /* Save the banked registers including the current SPSR and LR */ mrs r4, sp_usr @@ -85,10 +84,34 @@ /* lr_mon is already saved by caller */ ldcopr r4, SCR + +#if ARM_ARCH_MAJOR > 7 + /* + * Check if earlier initialization of SDCR.SCCD to 1 + * failed, meaning that ARMv8-PMU is not implemented, + * cycle counting is not disabled and PMCR should be + * saved in Non-secure context. + */ + ldcopr r5, SDCR + tst r5, #SDCR_SCCD_BIT + bne 1f +#endif + /* Secure Cycle Counter is not disabled */ #endif - str r4, [sp, #SMC_CTX_SCR] - ldcopr r4, PMCR - str r4, [sp, #SMC_CTX_PMCR] + ldcopr r5, PMCR + + /* Check caller's security state */ + tst r4, #SCR_NS_BIT + beq 2f + + /* Save PMCR if called from Non-secure state */ + str r5, [sp, #SMC_CTX_PMCR] + + /* Disable cycle counter when event counting is prohibited */ +2: orr r5, r5, #PMCR_DP_BIT + stcopr r5, PMCR + isb +1: str r4, [sp, #SMC_CTX_SCR] .endm /* @@ -114,11 +137,30 @@ isb /* + * Restore PMCR when returning to Non-secure state + */ + tst r1, #SCR_NS_BIT + beq 2f + + /* + * Back to Non-secure state + */ +#if ARM_ARCH_MAJOR > 7 + /* + * Check if earlier initialization SDCR.SCCD to 1 + * failed, meaning that ARMv8-PMU is not implemented and + * PMCR should be restored from Non-secure context. + */ + ldcopr r1, SDCR + tst r1, #SDCR_SCCD_BIT + bne 2f +#endif + /* * Restore the PMCR register. */ ldr r1, [r0, #SMC_CTX_PMCR] stcopr r1, PMCR - +2: /* Restore the banked registers including the current SPSR */ add r1, r0, #SMC_CTX_SP_USR diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index fa857fb1b..1fcd0f9ba 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -112,6 +112,7 @@ /* CLIDR definitions */ #define LOUIS_SHIFT U(21) #define LOC_SHIFT U(24) +#define CTYPE_SHIFT(n) U(3 * (n - 1)) #define CLIDR_FIELD_WIDTH U(3) /* CSSELR definitions */ @@ -132,12 +133,15 @@ #define ID_AA64PFR0_EL2_SHIFT U(8) #define ID_AA64PFR0_EL3_SHIFT U(12) #define ID_AA64PFR0_AMU_SHIFT U(44) -#define ID_AA64PFR0_AMU_LENGTH U(4) #define ID_AA64PFR0_AMU_MASK ULL(0xf) #define ID_AA64PFR0_ELX_MASK ULL(0xf) +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ULL(0xf) #define ID_AA64PFR0_SVE_SHIFT U(32) #define ID_AA64PFR0_SVE_MASK ULL(0xf) -#define ID_AA64PFR0_SVE_LENGTH U(4) +#define ID_AA64PFR0_SEL2_SHIFT U(36) +#define ID_AA64PFR0_SEL2_MASK ULL(0xf) #define ID_AA64PFR0_MPAM_SHIFT U(40) #define ID_AA64PFR0_MPAM_MASK ULL(0xf) #define ID_AA64PFR0_DIT_SHIFT U(48) @@ -148,18 +152,14 @@ #define ID_AA64PFR0_CSV2_MASK ULL(0xf) #define ID_AA64PFR0_CSV2_LENGTH U(4) -/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ -#define ID_AA64DFR0_PMS_SHIFT U(32) -#define ID_AA64DFR0_PMS_LENGTH U(4) -#define ID_AA64DFR0_PMS_MASK ULL(0xf) - +/* Exception level handling */ #define EL_IMPL_NONE ULL(0) #define EL_IMPL_A64ONLY ULL(1) #define EL_IMPL_A64_A32 ULL(2) -#define ID_AA64PFR0_GIC_SHIFT U(24) -#define ID_AA64PFR0_GIC_WIDTH U(4) -#define ID_AA64PFR0_GIC_MASK ULL(0xf) +/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ +#define ID_AA64DFR0_PMS_SHIFT U(32) +#define ID_AA64DFR0_PMS_MASK ULL(0xf) /* ID_AA64ISAR1_EL1 definitions */ #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 @@ -287,6 +287,7 @@ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) #define SCR_ATA_BIT (U(1) << 26) #define SCR_FIEN_BIT (U(1) << 21) +#define SCR_EEL2_BIT (U(1) << 18) #define SCR_API_BIT (U(1) << 17) #define SCR_APK_BIT (U(1) << 16) #define SCR_TWE_BIT (U(1) << 13) @@ -304,20 +305,25 @@ #define SCR_RESET_VAL SCR_RES1_BITS /* MDCR_EL3 definitions */ +#define MDCR_SCCD_BIT (ULL(1) << 23) +#define MDCR_SPME_BIT (ULL(1) << 17) +#define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_SPD32(x) ((x) << 14) #define MDCR_SPD32_LEGACY ULL(0x0) #define MDCR_SPD32_DISABLE ULL(0x2) #define MDCR_SPD32_ENABLE ULL(0x3) -#define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_NSPB(x) ((x) << 12) #define MDCR_NSPB_EL1 ULL(0x3) #define MDCR_TDOSA_BIT (ULL(1) << 10) #define MDCR_TDA_BIT (ULL(1) << 9) #define MDCR_TPM_BIT (ULL(1) << 6) -#define MDCR_SCCD_BIT (ULL(1) << 23) #define MDCR_EL3_RESET_VAL ULL(0x0) /* MDCR_EL2 definitions */ +#define MDCR_EL2_HLP (U(1) << 26) +#define MDCR_EL2_HCCD (U(1) << 23) +#define MDCR_EL2_TTRF (U(1) << 19) +#define MDCR_EL2_HPMD (U(1) << 17) #define MDCR_EL2_TPMS (U(1) << 14) #define MDCR_EL2_E2PB(x) ((x) << 12) #define MDCR_EL2_E2PB_EL1 U(0x3) @@ -595,6 +601,8 @@ #define ESR_EC_SHIFT U(26) #define ESR_EC_MASK U(0x3f) #define ESR_EC_LENGTH U(6) +#define ESR_ISS_SHIFT U(0) +#define ESR_ISS_LENGTH U(25) #define EC_UNKNOWN U(0x0) #define EC_WFE_WFI U(0x1) #define EC_AARCH32_CP15_MRC_MCR U(0x3) @@ -621,6 +629,7 @@ #define EC_AARCH32_FP U(0x28) #define EC_AARCH64_FP U(0x2c) #define EC_SERROR U(0x2f) +#define EC_BRK U(0x3c) /* * External Abort bit in Instruction and Data Aborts synchronous exception @@ -677,10 +686,14 @@ #define PMCR_EL0_N_SHIFT U(11) #define PMCR_EL0_N_MASK U(0x1f) #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) +#define PMCR_EL0_LP_BIT (U(1) << 7) #define PMCR_EL0_LC_BIT (U(1) << 6) #define PMCR_EL0_DP_BIT (U(1) << 5) #define PMCR_EL0_X_BIT (U(1) << 4) #define PMCR_EL0_D_BIT (U(1) << 3) +#define PMCR_EL0_C_BIT (U(1) << 2) +#define PMCR_EL0_P_BIT (U(1) << 1) +#define PMCR_EL0_E_BIT (U(1) << 0) /******************************************************************************* * Definitions for system register interface to SVE @@ -891,4 +904,12 @@ ******************************************************************************/ #define SSBS S3_3_C4_C2_6 +/******************************************************************************* + * Armv8.5 - Memory Tagging Extension Registers + ******************************************************************************/ +#define TFSRE0_EL1 S3_0_C5_C6_1 +#define TFSR_EL1 S3_0_C5_C6_0 +#define RGSR_EL1 S3_0_C1_C0_5 +#define GCR_EL1 S3_0_C1_C0_6 + #endif /* ARCH_H */ diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 2f29f4873..0491f48c6 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -34,14 +34,6 @@ static inline bool is_armv8_3_pauth_present(void) return (read_id_aa64isar1_el1() & mask) != 0U; } -static inline bool is_armv8_3_pauth_apa_api_present(void) -{ - uint64_t mask = (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | - (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); - - return (read_id_aa64isar1_el1() & mask) != 0U; -} - static inline bool is_armv8_4_ttst_present(void) { return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index c17370647..c60f2e8f7 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -501,6 +501,12 @@ DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) +/* Armv8.5 MTE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 79e0ad7f3..a7d5a3dd6 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -218,4 +218,13 @@ ret .endm + /* + * Macro for mitigating against speculative execution beyond ERET. + */ + .macro exception_return + eret + dsb nsh + isb + .endm + #endif /* ASM_MACROS_S */ diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 22b32b491..156b18a4f 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -113,15 +113,52 @@ * prohibited in Secure state. This bit is RES0 in versions of the * architecture earlier than ARMv8.5, setting it to 1 doesn't have any * effect on them. + * + * MDCR_EL3.SPME: Set to zero so that event counting by the programmable + * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 + * Debug is not implemented this bit does not have any effect on the + * counters unless there is support for the implementation defined + * authentication interface ExternalSecureNoninvasiveDebugEnabled(). * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ - MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) \ - & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) + MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ + ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \ + MDCR_TPM_BIT)) msr mdcr_el3, x0 /* --------------------------------------------------------------------- + * Initialise PMCR_EL0 setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR_EL0.LP: Set to one so that event counter overflow, that + * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment + * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU + * is implemented. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5, setting it to 1 doesn't have any effect + * on them. + * + * PMCR_EL0.LC: Set to one so that cycle counter overflow, that + * is recorded in PMOVSCLR_EL0[31], occurs on the increment + * that changes PMCCNTR_EL0[63] from 1 to 0. + * + * PMCR_EL0.DP: Set to one so that the cycle counter, + * PMCCNTR_EL0 does not count when event counting is prohibited. + * + * PMCR_EL0.X: Set to zero to disable export of events. + * + * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 + * counts on every clock cycle. + * --------------------------------------------------------------------- + */ + mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ + PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ + ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) + + msr pmcr_el0, x0 + + /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. * --------------------------------------------------------------------- @@ -195,11 +232,18 @@ * * _exception_vectors: * Address of the exception vectors to program in the VBAR_EL3 register. + * + * _pie_fixup_size: + * Size of memory region to fixup Global Descriptor Table (GDT). + * + * A non-zero value is expected when firmware needs GDT to be fixed-up. + * * ----------------------------------------------------------------------------- */ .macro el3_entrypoint_common \ _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ - _init_memory, _init_c_runtime, _exception_vectors + _init_memory, _init_c_runtime, _exception_vectors, \ + _pie_fixup_size .if \_init_sctlr /* ------------------------------------------------------------- @@ -246,6 +290,26 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + .if \_pie_fixup_size +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE - 1) + mov_imm x1, \_pie_fixup_size + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + .endif /* _pie_fixup_size */ + /* --------------------------------------------------------------------- * Set the exception vectors. * --------------------------------------------------------------------- @@ -303,7 +367,7 @@ * --------------------------------------------------------------------- */ .if \_init_c_runtime -#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3) +#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) /* ------------------------------------------------------------- * Invalidate the RW memory used by the BL31 image. This * includes the data and NOBITS sections. This is done to @@ -318,6 +382,14 @@ add x1, x1, :lo12:__RW_END__ sub x1, x1, x0 bl inv_dcache_range +#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION + adrp x0, __NOBITS_START__ + add x0, x0, :lo12:__NOBITS_START__ + adrp x1, __NOBITS_END__ + add x1, x1, :lo12:__NOBITS_END__ + sub x1, x1, x0 + bl inv_dcache_range +#endif #endif adrp x0, __BSS_START__ add x0, x0, :lo12:__BSS_START__ @@ -336,7 +408,7 @@ bl zeromem #endif -#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM) +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) adrp x0, __DATA_RAM_START__ add x0, x0, :lo12:__DATA_RAM_START__ adrp x1, __DATA_ROM_START__ diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index 8bb1bab24..935bf7766 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -134,7 +134,7 @@ typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -uint32_t get_scr_el3_from_routing_model(uint32_t security_state); +u_register_t get_scr_el3_from_routing_model(uint32_t security_state); int32_t set_routing_model(uint32_t type, uint32_t flags); int32_t register_interrupt_type_handler(uint32_t type, interrupt_type_handler_t handler, diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 896a03f0a..77fb1f679 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,6 +106,7 @@ IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END); IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END); #endif +IMPORT_SYM(uintptr_t, __RW_END__, BL_END); #if defined(IMAGE_BL1) IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h new file mode 100644 index 000000000..0248de9cf --- /dev/null +++ b/include/common/fdt_fixup.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FDT_FIXUP_H +#define FDT_FIXUP_H + +int dt_add_psci_node(void *fdt); +int dt_add_psci_cpu_enable_methods(void *fdt); +int fdt_add_reserved_memory(void *dtb, const char *node_name, + uintptr_t base, size_t size); + +#endif /* FDT_FIXUP_H */ diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h index 79d001d28..f467958b7 100644 --- a/include/common/fdt_wrappers.h +++ b/include/common/fdt_wrappers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,5 +20,9 @@ int fdtw_read_string(const void *dtb, int node, const char *prop, char *str, size_t size); int fdtw_write_inplace_cells(void *dtb, int node, const char *prop, unsigned int cells, void *value); +int fdtw_read_bytes(const void *dtb, int node, const char *prop, + unsigned int length, void *value); +int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop, + unsigned int length, const void *data); #endif /* FDT_WRAPPERS_H */ diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h new file mode 100644 index 000000000..9c0035f96 --- /dev/null +++ b/include/drivers/allwinner/axp.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AXP_H +#define AXP_H + +#include <stdint.h> + +#define NA 0xff + +enum { + AXP803_CHIP_ID = 0x41, + AXP805_CHIP_ID = 0x40, +}; + +struct axp_regulator { + const char *dt_name; + uint16_t min_volt; + uint16_t max_volt; + uint16_t step; + unsigned char split; + unsigned char volt_reg; + unsigned char switch_reg; + unsigned char switch_bit; +}; + +extern const uint8_t axp_chip_id; +extern const char *const axp_compatible; +extern const struct axp_regulator axp_regulators[]; + +/* + * Since the PMIC can be connected to multiple bus types, + * low-level read/write functions must be provided by the platform + */ +int axp_read(uint8_t reg); +int axp_write(uint8_t reg, uint8_t val); +int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask); +#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) +#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) + +int axp_check_id(void); +void axp_power_off(void); +void axp_setup_regulators(const void *fdt); + +#endif /* AXP_H */ diff --git a/include/drivers/meson/gxl/crypto/sha_dma.h b/include/drivers/amlogic/crypto/sha_dma.h index 52129a61f..52129a61f 100644 --- a/include/drivers/meson/gxl/crypto/sha_dma.h +++ b/include/drivers/amlogic/crypto/sha_dma.h diff --git a/include/drivers/meson/meson_console.h b/include/drivers/amlogic/meson_console.h index 70e3b0bd4..70e3b0bd4 100644 --- a/include/drivers/meson/meson_console.h +++ b/include/drivers/amlogic/meson_console.h diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h index cd9925b32..825214d20 100644 --- a/include/drivers/arm/cryptocell/712/rsa.h +++ b/include/drivers/arm/cryptocell/712/rsa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,19 +21,21 @@ extern "C" /************************ Defines ******************************/ -/* the modulus size ion bits */ +/* the modulus size in bits */ +#if (KEY_SIZE == 2048) #define RSA_MOD_SIZE_IN_BITS 2048UL +#elif (KEY_SIZE == 3072) +#define RSA_MOD_SIZE_IN_BITS 3072UL +#else +#error Unsupported CryptoCell key size requested +#endif + #define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS)) #define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS)) #define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8) #define RSA_EXP_SIZE_IN_BITS 17UL #define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS)) -/* size of buffer for Barrett modulus tag NP, used in PKA algorithms */ -#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS 132 -#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS)) -#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS)) - /* * @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr: * diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h index 68b9ef8ae..ed1f2835c 100644 --- a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h +++ b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,14 @@ extern "C" /***********************/ /*RSA definitions*/ +#if (KEY_SIZE == 2048) #define SB_RSA_MOD_SIZE_IN_WORDS 64 +#elif (KEY_SIZE == 3072) +#define SB_RSA_MOD_SIZE_IN_WORDS 96 +#else +#error Unsupported CryptoCell key size requested +#endif + #define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5 @@ -43,9 +50,12 @@ typedef struct { /********* Supported algorithms definitions ***********/ /*! RSA supported algorithms */ +/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library + * version - it means 2k in version 1 and 3k in version 2 (yes, really). + */ typedef enum { - RSA_PSS_2048 = 0x01, /*!< RSA PSS 2048 after hash SHA 256 */ - RSA_PKCS15_2048 = 0x02, /*!< RSA PKX15 */ + RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */ + RSA_PKCS15 = 0x02, /*!< RSA PKX15 */ RSA_Last = 0x7FFFFFFF } CCSbRsaAlg_t; diff --git a/include/drivers/arm/gic600_multichip.h b/include/drivers/arm/gic600_multichip.h new file mode 100644 index 000000000..bda406bba --- /dev/null +++ b/include/drivers/arm/gic600_multichip.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GIC600_MULTICHIP_H +#define GIC600_MULTICHIP_H + +#include <stdint.h> + +/* + * GIC-600 microarchitecture supports coherent multichip environments containing + * up to 16 chips. + */ +#define GIC600_MAX_MULTICHIP 16 + +/* SPI IDs array consist of min and max ids */ +#define GIC600_SPI_IDS_SIZE 2 + +/******************************************************************************* + * GIC-600 multichip data structure describes platform specific attributes + * related to GIC-600 multichip. Platform port is expected to define these + * attributes to initialize the multichip related registers and create + * successful connections between the GIC-600s in a multichip system. + * + * The 'rt_owner_base' field contains the base address of the GIC Distributor + * which owns the routing table. + * + * The 'rt_owner' field contains the chip number which owns the routing table. + * Chip number or chip_id starts from 0. + * + * The 'chip_count' field contains the total number of chips in a multichip + * system. This should match the number of entries in 'chip_addrs' and 'spi_ids' + * fields. + * + * The 'chip_addrs' field contains array of chip addresses. These addresses are + * implementation specific values. + * + * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids + * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and + * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be + * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0} + * should be passed. + ******************************************************************************/ +struct gic600_multichip_data { + uintptr_t rt_owner_base; + unsigned int rt_owner; + unsigned int chip_count; + uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; + unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE]; +}; + +void gic600_multichip_init(struct gic600_multichip_data *multichip_data); +#endif /* GIC600_MULTICHIP_H */ diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 9c72d4dff..c4f42d04d 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -366,6 +366,7 @@ typedef struct gicv3_its_ctx { * GICv3 EL3 driver API ******************************************************************************/ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); +int gicv3_rdistif_probe(const uintptr_t gicr_frame); void gicv3_distif_init(void); void gicv3_rdistif_init(unsigned int proc_num); void gicv3_rdistif_on(unsigned int proc_num); diff --git a/include/drivers/arm/scu.h b/include/drivers/arm/scu.h new file mode 100644 index 000000000..992539f21 --- /dev/null +++ b/include/drivers/arm/scu.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCU_H +#define SCU_H + +#include <stdint.h> + +#define SCU_CTRL_REG 0x00 +#define SCU_CFG_REG 0x04 + +#define SCU_ENABLE_BIT (1 << 0) + +void enable_snoop_ctrl_unit(uintptr_t base); +uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base); + +#endif /* SCU_H */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 3a4210569..f211035d7 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,6 +37,13 @@ typedef struct crypto_lib_desc_s { /* Verify a hash. Return one of the 'enum crypto_ret_value' options */ int (*verify_hash)(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); + +#if MEASURED_BOOT + /* Calculate a hash. Return hash value */ + int (*calc_hash)(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output); +#endif /* MEASURED_BOOT */ + } crypto_lib_desc_t; /* Public functions */ @@ -48,7 +55,21 @@ int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +#if MEASURED_BOOT +int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output); + /* Macro to register a cryptographic library */ +#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ + _calc_hash) \ + const crypto_lib_desc_t crypto_lib_desc = { \ + .name = _name, \ + .init = _init, \ + .verify_signature = _verify_signature, \ + .verify_hash = _verify_hash, \ + .calc_hash = _calc_hash \ + } +#else #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ @@ -56,6 +77,7 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, .verify_signature = _verify_signature, \ .verify_hash = _verify_hash \ } +#endif /* MEASURED_BOOT */ extern const crypto_lib_desc_t crypto_lib_desc; diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h index acfde268a..6e179bbd1 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,11 @@ #define TF_MBEDTLS_ECDSA 2 #define TF_MBEDTLS_RSA_AND_ECDSA 3 +#define TF_MBEDTLS_USE_RSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA \ + || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) +#define TF_MBEDTLS_USE_ECDSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA \ + || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) + /* * Hash algorithms currently supported on mbed TLS libraries */ @@ -54,19 +59,14 @@ #define MBEDTLS_PLATFORM_C -#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) +#if TF_MBEDTLS_USE_ECDSA #define MBEDTLS_ECDSA_C #define MBEDTLS_ECP_C #define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA) -#define MBEDTLS_RSA_C -#define MBEDTLS_X509_RSASSA_PSS_SUPPORT -#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) +#endif +#if TF_MBEDTLS_USE_RSA #define MBEDTLS_RSA_C #define MBEDTLS_X509_RSASSA_PSS_SUPPORT -#define MBEDTLS_ECDSA_C -#define MBEDTLS_ECP_C -#define MBEDTLS_ECP_DP_SECP256R1_ENABLED #endif #define MBEDTLS_SHA256_C @@ -80,28 +80,41 @@ #define MBEDTLS_X509_CRT_PARSE_C /* MPI / BIGNUM options */ -#define MBEDTLS_MPI_WINDOW_SIZE 2 -#define MBEDTLS_MPI_MAX_SIZE 256 +#define MBEDTLS_MPI_WINDOW_SIZE 2 + +#if TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE <= 2048 +#define MBEDTLS_MPI_MAX_SIZE 256 +#else +#define MBEDTLS_MPI_MAX_SIZE 512 +#endif +#else +#define MBEDTLS_MPI_MAX_SIZE 256 +#endif /* Memory buffer allocator options */ -#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 +#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 #ifndef __ASSEMBLER__ /* System headers required to build mbed TLS with the current configuration */ #include <stdlib.h> -#include "mbedtls/check_config.h" +#include <mbedtls/check_config.h> #endif /* * Determine Mbed TLS heap size * 13312 = 13*1024 - * 7168 = 7*1024 + * 11264 = 11*1024 + * 7168 = 7*1024 */ -#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) \ - || (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) +#if TF_MBEDTLS_USE_ECDSA #define TF_MBEDTLS_HEAP_SIZE U(13312) -#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA) +#elif TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE <= 2048 #define TF_MBEDTLS_HEAP_SIZE U(7168) +#else +#define TF_MBEDTLS_HEAP_SIZE U(11264) +#endif #endif #endif /* MBEDTLS_CONFIG_H */ diff --git a/include/drivers/console.h b/include/drivers/console.h index cada771b4..a4859d80f 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,8 @@ #define CONSOLE_FLAG_CRASH (U(1) << 2) /* Bits 3 to 7 reserved for additional scopes in future expansion. */ #define CONSOLE_FLAG_SCOPE_MASK ((U(1) << 8) - 1) -/* Bits 8 to 31 reserved for non-scope use in future expansion. */ +/* Bits 8 to 31 for non-scope use. */ +#define CONSOLE_FLAG_TRANSLATE_CRLF (U(1) << 8) /* Returned by getc callbacks when receive FIFO is empty. */ #define ERROR_NO_PENDING_CHAR (-1) diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h index 684f1c3c3..20a554357 100644 --- a/include/drivers/delay_timer.h +++ b/include/drivers/delay_timer.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Linaro Limited * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +8,11 @@ #ifndef DELAY_TIMER_H #define DELAY_TIMER_H +#include <stdbool.h> #include <stdint.h> +#include <arch_helpers.h> + /******************************************************************** * A simple timer driver providing synchronous delay functionality. * The driver must be initialized with a structure that provides a @@ -23,6 +27,25 @@ typedef struct timer_ops { uint32_t clk_div; } timer_ops_t; +static inline uint64_t timeout_cnt_us2cnt(uint32_t us) +{ + return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL; +} + +static inline uint64_t timeout_init_us(uint32_t us) +{ + uint64_t cnt = timeout_cnt_us2cnt(us); + + cnt += read_cntpct_el0(); + + return cnt; +} + +static inline bool timeout_elapsed(uint64_t expire_cnt) +{ + return read_cntpct_el0() > expire_cnt; +} + void mdelay(uint32_t msec); void udelay(uint32_t usec); void timer_init(const timer_ops_t *ops_ptr); diff --git a/include/drivers/io/io_driver.h b/include/drivers/io/io_driver.h index 2b704f491..d8bb435aa 100644 --- a/include/drivers/io/io_driver.h +++ b/include/drivers/io/io_driver.h @@ -39,7 +39,7 @@ typedef struct io_dev_funcs { io_type_t (*type)(void); int (*open)(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); - int (*seek)(io_entity_t *entity, int mode, ssize_t offset); + int (*seek)(io_entity_t *entity, int mode, signed long long offset); int (*size)(io_entity_t *entity, size_t *length); int (*read)(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); diff --git a/include/drivers/io/io_mtd.h b/include/drivers/io/io_mtd.h new file mode 100644 index 000000000..1395ff601 --- /dev/null +++ b/include/drivers/io/io_mtd.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IO_MTD_H +#define IO_MTD_H + +#include <stdint.h> +#include <stdio.h> + +#include <drivers/io/io_storage.h> + +/* MTD devices ops */ +typedef struct io_mtd_ops { + /* + * Initialize MTD framework and retrieve device information. + * + * @size: [out] MTD device size in bytes. + * @erase_size: [out] MTD erase size in bytes. + * Return 0 on success, a negative error code otherwise. + */ + int (*init)(unsigned long long *size, unsigned int *erase_size); + + /* + * Execute a read memory operation. + * + * @offset: Offset in bytes to start read operation. + * @buffer: [out] Buffer to store read data. + * @length: Required length to be read in bytes. + * @out_length: [out] Length read in bytes. + * Return 0 on success, a negative error code otherwise. + */ + int (*read)(unsigned int offset, uintptr_t buffer, size_t length, + size_t *out_length); + + /* + * Execute a write memory operation. + * + * @offset: Offset in bytes to start write operation. + * @buffer: Buffer to be written in device. + * @length: Required length to be written in bytes. + * Return 0 on success, a negative error code otherwise. + */ + int (*write)(unsigned int offset, uintptr_t buffer, size_t length); +} io_mtd_ops_t; + +typedef struct io_mtd_dev_spec { + unsigned long long device_size; + unsigned int erase_size; + io_mtd_ops_t ops; +} io_mtd_dev_spec_t; + +struct io_dev_connector; + +int register_io_dev_mtd(const struct io_dev_connector **dev_con); + +#endif /* IO_MTD_H */ diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index 084c67c47..0e6ffd619 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,7 @@ typedef enum { IO_TYPE_DUMMY, IO_TYPE_FIRMWARE_IMAGE_PACKAGE, IO_TYPE_BLOCK, + IO_TYPE_MTD, IO_TYPE_MMC, IO_TYPE_STM32IMAGE, IO_TYPE_MAX @@ -86,7 +87,7 @@ int io_dev_close(uintptr_t dev_handle); /* Synchronous operations */ int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle); -int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset); +int io_seek(uintptr_t handle, io_seek_mode_t mode, signed long long offset); int io_size(uintptr_t handle, size_t *length); diff --git a/include/drivers/nand.h b/include/drivers/nand.h new file mode 100644 index 000000000..1dbb008f9 --- /dev/null +++ b/include/drivers/nand.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_NAND_H +#define DRIVERS_NAND_H + +#include <stddef.h> +#include <stdint.h> + +#include <lib/utils_def.h> + +#define PSEC_TO_MSEC(x) div_round_up((x), 1000000000ULL) + +struct ecc { + unsigned int mode; /* ECC mode NAND_ECC_MODE_{NONE|HW|ONDIE} */ + unsigned int size; /* Data byte per ECC step */ + unsigned int bytes; /* ECC bytes per step */ + unsigned int max_bit_corr; /* Max correctible bits per ECC steps */ +}; + +struct nand_device { + unsigned int block_size; + unsigned int page_size; + unsigned long long size; + unsigned int nb_planes; + unsigned int buswidth; + struct ecc ecc; + int (*mtd_block_is_bad)(unsigned int block); + int (*mtd_read_page)(struct nand_device *nand, unsigned int page, + uintptr_t buffer); +}; + +/* + * Read bytes from NAND device + * + * @offset: Byte offset to read from in device + * @buffer: [out] Bytes read from device + * @length: Number of bytes to read + * @length_read: [out] Number of bytes read from device + * Return: 0 on success, a negative errno on failure + */ +int nand_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *length_read); + +/* + * Get NAND device instance + * + * Return: NAND device instance reference + */ +struct nand_device *get_nand_device(void); + +#endif /* DRIVERS_NAND_H */ diff --git a/include/drivers/partition/gpt.h b/include/drivers/partition/gpt.h index 3ae160fdc..d923e9535 100644 --- a/include/drivers/partition/gpt.h +++ b/include/drivers/partition/gpt.h @@ -10,9 +10,9 @@ #include <drivers/partition/partition.h> #define PARTITION_TYPE_GPT 0xee -#define GPT_HEADER_OFFSET PARTITION_BLOCK_SIZE +#define GPT_HEADER_OFFSET PLAT_PARTITION_BLOCK_SIZE #define GPT_ENTRY_OFFSET (GPT_HEADER_OFFSET + \ - PARTITION_BLOCK_SIZE) + PLAT_PARTITION_BLOCK_SIZE) #define GUID_LEN 16 #define GPT_SIGNATURE "EFI PART" diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index d94c7824a..5f6483373 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h @@ -17,7 +17,15 @@ CASSERT(PLAT_PARTITION_MAX_ENTRIES <= 128, assert_plat_partition_max_entries); -#define PARTITION_BLOCK_SIZE 512 +#if !PLAT_PARTITION_BLOCK_SIZE +# define PLAT_PARTITION_BLOCK_SIZE 512 +#endif /* PLAT_PARTITION_BLOCK_SIZE */ + +CASSERT((PLAT_PARTITION_BLOCK_SIZE == 512) || + (PLAT_PARTITION_BLOCK_SIZE == 4096), + assert_plat_partition_block_size); + +#define LEGACY_PARTITION_BLOCK_SIZE 512 #define EFI_NAMELEN 36 diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h new file mode 100644 index 000000000..18e4b73da --- /dev/null +++ b/include/drivers/raw_nand.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_RAW_NAND_H +#define DRIVERS_RAW_NAND_H + +#include <stdint.h> + +#include <drivers/nand.h> + +/* NAND ONFI default value mode 0 in picosecond */ +#define NAND_TADL_MIN 400000UL +#define NAND_TALH_MIN 20000UL +#define NAND_TALS_MIN 50000UL +#define NAND_TAR_MIN 25000UL +#define NAND_TCCS_MIN 500000UL +#define NAND_TCEA_MIN 100000UL +#define NAND_TCEH_MIN 20000UL +#define NAND_TCH_MIN 20000UL +#define NAND_TCHZ_MAX 100000UL +#define NAND_TCLH_MIN 20000UL +#define NAND_TCLR_MIN 20000UL +#define NAND_TCLS_MIN 50000UL +#define NAND_TCOH_MIN 0UL +#define NAND_TCS_MIN 70000UL +#define NAND_TDH_MIN 20000UL +#define NAND_TDS_MIN 40000UL +#define NAND_TFEAT_MAX 1000000UL +#define NAND_TIR_MIN 10000UL +#define NAND_TITC_MIN 1000000UL +#define NAND_TR_MAX 200000000UL +#define NAND_TRC_MIN 100000UL +#define NAND_TREA_MAX 40000UL +#define NAND_TREH_MIN 30000UL +#define NAND_TRHOH_MIN 0UL +#define NAND_TRHW_MIN 200000UL +#define NAND_TRHZ_MAX 200000UL +#define NAND_TRLOH_MIN 0UL +#define NAND_TRP_MIN 50000UL +#define NAND_TRR_MIN 40000UL +#define NAND_TRST_MAX 250000000000ULL +#define NAND_TWB_MAX 200000UL +#define NAND_TWC_MIN 100000UL +#define NAND_TWH_MIN 30000UL +#define NAND_TWHR_MIN 120000UL +#define NAND_TWP_MIN 50000UL +#define NAND_TWW_MIN 100000UL + +/* NAND request types */ +#define NAND_REQ_CMD 0x0000U +#define NAND_REQ_ADDR 0x1000U +#define NAND_REQ_DATAIN 0x2000U +#define NAND_REQ_DATAOUT 0x3000U +#define NAND_REQ_WAIT 0x4000U +#define NAND_REQ_MASK GENMASK(14, 12) +#define NAND_REQ_BUS_WIDTH_8 BIT(15) + +#define PARAM_PAGE_SIZE 256 + +/* NAND ONFI commands */ +#define NAND_CMD_READ_1ST 0x00U +#define NAND_CMD_CHANGE_1ST 0x05U +#define NAND_CMD_READID_SIG_ADDR 0x20U +#define NAND_CMD_READ_2ND 0x30U +#define NAND_CMD_STATUS 0x70U +#define NAND_CMD_READID 0x90U +#define NAND_CMD_CHANGE_2ND 0xE0U +#define NAND_CMD_READ_PARAM_PAGE 0xECU +#define NAND_CMD_RESET 0xFFU + +#define ONFI_REV_21 BIT(3) +#define ONFI_FEAT_BUS_WIDTH_16 BIT(0) +#define ONFI_FEAT_EXTENDED_PARAM BIT(7) + +/* NAND ECC type */ +#define NAND_ECC_NONE U(0) +#define NAND_ECC_HW U(1) +#define NAND_ECC_ONDIE U(2) + +/* NAND bus width */ +#define NAND_BUS_WIDTH_8 U(0) +#define NAND_BUS_WIDTH_16 U(1) + +struct nand_req { + struct nand_device *nand; + uint16_t type; + uint8_t *addr; + unsigned int length; + unsigned int delay_ms; + unsigned int inst_delay; +}; + +struct nand_param_page { + /* Rev information and feature block */ + uint32_t page_sig; + uint16_t rev; + uint16_t features; + uint16_t opt_cmd; + uint8_t jtg; + uint8_t train_cmd; + uint16_t ext_param_length; + uint8_t nb_param_pages; + uint8_t reserved1[17]; + /* Manufacturer information */ + uint8_t manufacturer[12]; + uint8_t model[20]; + uint8_t manufacturer_id; + uint16_t data_code; + uint8_t reserved2[13]; + /* Memory organization */ + uint32_t bytes_per_page; + uint16_t spare_per_page; + uint32_t bytes_per_partial; + uint16_t spare_per_partial; + uint32_t num_pages_per_blk; + uint32_t num_blk_in_lun; + uint8_t num_lun; + uint8_t num_addr_cycles; + uint8_t bit_per_cell; + uint16_t max_bb_per_lun; + uint16_t blk_endur; + uint8_t valid_blk_begin; + uint16_t blk_enbur_valid; + uint8_t nb_prog_page; + uint8_t partial_prog_attr; + uint8_t nb_ecc_bits; + uint8_t plane_addr; + uint8_t mplanes_ops; + uint8_t ez_nand; + uint8_t reserved3[12]; + /* Electrical parameters */ + uint8_t io_pin_cap_max; + uint16_t sdr_timing_mode; + uint16_t sdr_prog_cache_timing; + uint16_t tprog; + uint16_t tbers; + uint16_t tr; + uint16_t tccs; + uint8_t nvddr_timing_mode; + uint8_t nvddr2_timing_mode; + uint8_t nvddr_features; + uint16_t clk_input_cap_typ; + uint16_t io_pin_cap_typ; + uint16_t input_pin_cap_typ; + uint8_t input_pin_cap_max; + uint8_t drv_strength_support; + uint16_t tr_max; + uint16_t tadl; + uint16_t tr_typ; + uint8_t reserved4[6]; + /* Vendor block */ + uint16_t vendor_revision; + uint8_t vendor[88]; + uint16_t crc16; +} __packed; + +struct nand_ctrl_ops { + int (*exec)(struct nand_req *req); + void (*setup)(struct nand_device *nand); +}; + +struct rawnand_device { + struct nand_device *nand_dev; + const struct nand_ctrl_ops *ops; +}; + +int nand_raw_init(unsigned long long *size, unsigned int *erase_size); +int nand_wait_ready(unsigned long delay); +int nand_read_page_cmd(unsigned int page, unsigned int offset, + uintptr_t buffer, unsigned int len); +int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, + unsigned int len); +void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops); + +/* + * Platform can implement this to override default raw NAND instance + * configuration. + * + * @device: target raw NAND instance. + * Return 0 on success, negative value otherwise. + */ +int plat_get_raw_nand_data(struct rawnand_device *device); + +#endif /* DRIVERS_RAW_NAND_H */ diff --git a/include/drivers/rpi3/mailbox/rpi3_mbox.h b/include/drivers/rpi3/mailbox/rpi3_mbox.h new file mode 100644 index 000000000..c1074402b --- /dev/null +++ b/include/drivers/rpi3/mailbox/rpi3_mbox.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_MBOX_H +#define RPI3_MBOX_H + +#include <stdint.h> + +/* This struct must be aligned to 16 bytes */ +typedef struct __packed __aligned(16) rpi3_mbox_request { + uint32_t size; /* Buffer size in bytes */ + uint32_t code; /* Request/response code */ + uint32_t tags[0]; +} rpi3_mbox_request_t; + +#define RPI3_MBOX_BUFFER_SIZE U(256) + +/* Constants to perform a request/check the status of a request. */ +#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) +#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) +#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) + +/* Command constants */ +#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) +#define RPI3_TAG_END U(0x00000000) + +#define RPI3_TAG_REQUEST U(0x00000000) +#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ +#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) + +#define RPI3_CHANNEL_ARM_TO_VC U(0x8) +#define RPI3_CHANNEL_MASK U(0xF) + +void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size); + +#endif diff --git a/include/drivers/rpi3/rng/rpi3_rng.h b/include/drivers/rpi3/rng/rpi3_rng.h new file mode 100644 index 000000000..ea5a67708 --- /dev/null +++ b/include/drivers/rpi3/rng/rpi3_rng.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_RNG_H +#define RPI3_RNG_H + +void rpi3_rng_read(void *buf, size_t len); + +#endif diff --git a/include/drivers/spi_mem.h b/include/drivers/spi_mem.h new file mode 100644 index 000000000..d1953acf4 --- /dev/null +++ b/include/drivers/spi_mem.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_SPI_MEM_H +#define DRIVERS_SPI_MEM_H + +#include <errno.h> +#include <stdbool.h> +#include <stdint.h> + +#define SPI_MEM_BUSWIDTH_1_LINE 1U +#define SPI_MEM_BUSWIDTH_2_LINE 2U +#define SPI_MEM_BUSWIDTH_4_LINE 4U + +/* + * enum spi_mem_data_dir - Describes the direction of a SPI memory data + * transfer from the controller perspective. + * @SPI_MEM_DATA_IN: data coming from the SPI memory. + * @SPI_MEM_DATA_OUT: data sent to the SPI memory. + */ +enum spi_mem_data_dir { + SPI_MEM_DATA_IN, + SPI_MEM_DATA_OUT, +}; + +/* + * struct spi_mem_op - Describes a SPI memory operation. + * + * @cmd.buswidth: Number of IO lines used to transmit the command. + * @cmd.opcode: Operation opcode. + * @addr.nbytes: Number of address bytes to send. Can be zero if the operation + * does not need to send an address. + * @addr.buswidth: Number of IO lines used to transmit the address. + * @addr.val: Address value. This value is always sent MSB first on the bus. + * Note that only @addr.nbytes are taken into account in this + * address value, so users should make sure the value fits in the + * assigned number of bytes. + * @dummy.nbytes: Number of dummy bytes to send after an opcode or address. Can + * be zero if the operation does not require dummy bytes. + * @dummy.buswidth: Number of IO lines used to transmit the dummy bytes. + * @data.buswidth: Number of IO lines used to send/receive the data. + * @data.dir: Direction of the transfer. + * @data.nbytes: Number of data bytes to transfer. + * @data.buf: Input or output data buffer depending on data::dir. + */ +struct spi_mem_op { + struct { + uint8_t buswidth; + uint8_t opcode; + } cmd; + + struct { + uint8_t nbytes; + uint8_t buswidth; + uint64_t val; + } addr; + + struct { + uint8_t nbytes; + uint8_t buswidth; + } dummy; + + struct { + uint8_t buswidth; + enum spi_mem_data_dir dir; + unsigned int nbytes; + void *buf; + } data; +}; + +/* SPI mode flags */ +#define SPI_CPHA BIT(0) /* clock phase */ +#define SPI_CPOL BIT(1) /* clock polarity */ +#define SPI_CS_HIGH BIT(2) /* CS active high */ +#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */ +#define SPI_3WIRE BIT(4) /* SI/SO signals shared */ +#define SPI_PREAMBLE BIT(5) /* Skip preamble bytes */ +#define SPI_TX_DUAL BIT(6) /* transmit with 2 wires */ +#define SPI_TX_QUAD BIT(7) /* transmit with 4 wires */ +#define SPI_RX_DUAL BIT(8) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(9) /* receive with 4 wires */ + +struct spi_bus_ops { + /* + * Claim the bus and prepare it for communication. + * + * @cs: The chip select. + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ + int (*claim_bus)(unsigned int cs); + + /* + * Release the SPI bus. + */ + void (*release_bus)(void); + + /* + * Set transfer speed. + * + * @hz: The transfer speed in Hertz. + * Returns: 0 on success, a negative error code otherwise. + */ + int (*set_speed)(unsigned int hz); + + /* + * Set the SPI mode/flags. + * + * @mode: Requested SPI mode (SPI_... flags). + * Returns: 0 on success, a negative error code otherwise. + */ + int (*set_mode)(unsigned int mode); + + /* + * Execute a SPI memory operation. + * + * @op: The memory operation to execute. + * Returns: 0 on success, a negative error code otherwise. + */ + int (*exec_op)(const struct spi_mem_op *op); +}; + +int spi_mem_exec_op(const struct spi_mem_op *op); +int spi_mem_init_slave(void *fdt, int bus_node, + const struct spi_bus_ops *ops); + +#endif /* DRIVERS_SPI_MEM_H */ diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h new file mode 100644 index 000000000..40e206375 --- /dev/null +++ b/include/drivers/spi_nand.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_SPI_NAND_H +#define DRIVERS_SPI_NAND_H + +#include <drivers/nand.h> +#include <drivers/spi_mem.h> + +#define SPI_NAND_OP_GET_FEATURE 0x0FU +#define SPI_NAND_OP_SET_FEATURE 0x1FU +#define SPI_NAND_OP_READ_ID 0x9FU +#define SPI_NAND_OP_LOAD_PAGE 0x13U +#define SPI_NAND_OP_RESET 0xFFU +#define SPI_NAND_OP_READ_FROM_CACHE 0x03U +#define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU +#define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU + +/* Configuration register */ +#define SPI_NAND_REG_CFG 0xB0U +#define SPI_NAND_CFG_ECC_EN BIT(4) +#define SPI_NAND_CFG_QE BIT(0) + +/* Status register */ +#define SPI_NAND_REG_STATUS 0xC0U +#define SPI_NAND_STATUS_BUSY BIT(0) +#define SPI_NAND_STATUS_ECC_UNCOR BIT(5) + +struct spinand_device { + struct nand_device *nand_dev; + struct spi_mem_op spi_read_cache_op; + uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ +}; + +int spi_nand_init(unsigned long long *size, unsigned int *erase_size); + +/* + * Platform can implement this to override default SPI-NAND instance + * configuration. + * + * @device: target SPI-NAND instance. + * Return 0 on success, negative value otherwise. + */ +int plat_get_spi_nand_data(struct spinand_device *device); + +#endif /* DRIVERS_SPI_NAND_H */ diff --git a/include/drivers/spi_nor.h b/include/drivers/spi_nor.h new file mode 100644 index 000000000..72cfe5b34 --- /dev/null +++ b/include/drivers/spi_nor.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_SPI_NOR_H +#define DRIVERS_SPI_NOR_H + +#include <drivers/spi_mem.h> + +/* OPCODE */ +#define SPI_NOR_OP_WREN 0x06U /* Write enable */ +#define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */ +#define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */ +#define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */ +#define SPI_NOR_OP_READ_SR 0x05U /* Read status register */ +#define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */ +#define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */ +#define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */ + +/* Used for Spansion flashes only. */ +#define SPINOR_OP_BRWR 0x17U /* Bank register write */ +#define SPINOR_OP_BRRD 0x16U /* Bank register read */ + +#define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */ +#define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */ +#define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */ +#define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */ +#define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */ +#define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */ + +/* Flags for NOR specific configuration */ +#define SPI_NOR_USE_FSR BIT(0) +#define SPI_NOR_USE_BANK BIT(1) + +struct nor_device { + struct spi_mem_op read_op; + uint32_t size; + uint32_t flags; + uint8_t selected_bank; + uint8_t bank_write_cmd; + uint8_t bank_read_cmd; +}; + +int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *length_read); +int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size); + +/* + * Platform can implement this to override default NOR instance configuration. + * + * @device: target NOR instance. + * Return 0 on success, negative value otherwise. + */ +int plat_get_nor_data(struct nor_device *device); + +#endif /* DRIVERS_SPI_NOR_H */ diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h index 2171550b3..d833e7ab2 100644 --- a/include/drivers/st/bsec.h +++ b/include/drivers/st/bsec.h @@ -199,7 +199,6 @@ bool bsec_read_sp_lock(uint32_t otp); bool bsec_wr_lock(uint32_t otp); uint32_t bsec_otp_lock(uint32_t service, uint32_t value); -bool bsec_mode_is_closed_device(void); uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word); uint32_t bsec_check_nsec_access_rights(uint32_t otp); diff --git a/include/drivers/st/io_stm32image.h b/include/drivers/st/io_stm32image.h index 68060558b..f9fa3630c 100644 --- a/include/drivers/st/io_stm32image.h +++ b/include/drivers/st/io_stm32image.h @@ -23,7 +23,7 @@ struct stm32image_part_info { struct stm32image_device_info { struct stm32image_part_info part_info[STM32_PART_NUM]; - uint32_t device_size; + unsigned long long device_size; uint32_t lba_size; }; diff --git a/include/drivers/st/stm32_fmc2_nand.h b/include/drivers/st/stm32_fmc2_nand.h new file mode 100644 index 000000000..81d5b9de1 --- /dev/null +++ b/include/drivers/st/stm32_fmc2_nand.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32_FMC2_NAND_H +#define STM32_FMC2_NAND_H + +int stm32_fmc2_init(void); + +#endif /* STM32_FMC2_NAND_H */ diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h new file mode 100644 index 000000000..df04730d6 --- /dev/null +++ b/include/drivers/st/stm32_hash.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_HASH_H +#define STM32_HASH_H + +enum stm32_hash_algo_mode { + HASH_MD5SUM, + HASH_SHA1, + HASH_SHA224, + HASH_SHA256 +}; + +int stm32_hash_update(const uint8_t *buffer, size_t length); +int stm32_hash_final(uint8_t *digest); +int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length, + uint8_t *digest); +void stm32_hash_init(enum stm32_hash_algo_mode mode); +int stm32_hash_register(void); + +#endif /* STM32_HASH_H */ diff --git a/include/drivers/st/stm32_iwdg.h b/include/drivers/st/stm32_iwdg.h new file mode 100644 index 000000000..bad25244a --- /dev/null +++ b/include/drivers/st/stm32_iwdg.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_IWDG_H +#define STM32_IWDG_H + +#include <stdint.h> + +#define IWDG_HW_ENABLED BIT(0) +#define IWDG_DISABLE_ON_STOP BIT(1) +#define IWDG_DISABLE_ON_STANDBY BIT(2) + +int stm32_iwdg_init(void); +void stm32_iwdg_refresh(void); + +#endif /* STM32_IWDG_H */ diff --git a/include/drivers/st/stm32_qspi.h b/include/drivers/st/stm32_qspi.h new file mode 100644 index 000000000..f47fca445 --- /dev/null +++ b/include/drivers/st/stm32_qspi.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32_QSPI_H +#define STM32_QSPI_H + +int stm32_qspi_init(void); + +#endif /* STM32_QSPI_H */ diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h index aa9472c83..4853208c2 100644 --- a/include/drivers/st/stm32_sdmmc2.h +++ b/include/drivers/st/stm32_sdmmc2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,7 @@ struct stm32_sdmmc2_params { unsigned int dirpol; unsigned int clock_id; unsigned int reset_id; + unsigned int max_freq; bool use_dma; }; diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h index 32e38f0ac..2b95fa33a 100644 --- a/include/drivers/ti/uart/uart_16550.h +++ b/include/drivers/ti/uart/uart_16550.h @@ -87,6 +87,11 @@ typedef struct { * framework. The |console| pointer must point to storage that will be valid * for the lifetime of the console, such as a global or static local variable. * Its contents will be reinitialized from scratch. + * When |clock| has a value of 0, the UART will *not* be initialised. This + * means the UART should already be enabled and the baudrate and clock setup + * should have been done already, either by platform specific code or by + * previous firmware stages. The |baud| parameter will be ignored in this + * case as well. */ int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_16550_t *console); diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h index 86c409ce1..d4a4a85dd 100644 --- a/include/export/lib/utils_def_exp.h +++ b/include/export/lib/utils_def_exp.h @@ -25,11 +25,13 @@ # define L(_x) (_x) # define LL(_x) (_x) #else -# define U(_x) (_x##U) +# define U_(_x) (_x##U) +# define U(_x) U_(_x) # define UL(_x) (_x##UL) # define ULL(_x) (_x##ULL) # define L(_x) (_x##L) # define LL(_x) (_x##LL) + #endif #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H */ diff --git a/include/export/plat/mediatek/common/plat_params_exp.h b/include/export/plat/mediatek/common/plat_params_exp.h new file mode 100644 index 000000000..d65003086 --- /dev/null +++ b/include/export/plat/mediatek/common/plat_params_exp.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H +#define ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H + +/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */ + +#include "../../../lib/bl_aux_params/bl_aux_params_exp.h" + +/* param type */ +enum bl_aux_mtk_param_type { + BL_AUX_PARAM_MTK_RESET_GPIO = BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST, +}; + +#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H */ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 09db12b6e..6fe67a9f3 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -73,4 +73,11 @@ ******************************************************************************/ #define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 +/******************************************************************************* + * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs + ******************************************************************************/ +#ifndef __ASSEMBLER__ +DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1) +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A53_H */ diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h new file mode 100644 index 000000000..0df34c9ce --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65_H +#define CORTEX_A65_H + +#include <lib/utils_def.h> + +#define CORTEX_A65_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65_H */ diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h new file mode 100644 index 000000000..bd4a881a3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65ae.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65AE_H +#define CORTEX_A65AE_H + +#include <lib/utils_def.h> + +#define CORTEX_A65AE_MIDR U(0x410FD430) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 4a444c67a..28b440e19 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -43,7 +43,14 @@ ******************************************************************************/ #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 +#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) +#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) +#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) +#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) +#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) +#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) +#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) /******************************************************************************* * L2 Control register specific definitions. @@ -51,8 +58,12 @@ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 1238c0ef4..271a33348 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -35,4 +35,11 @@ #define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 +/******************************************************************************* + * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs + ******************************************************************************/ +#ifndef __ASSEMBLER__ +DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A73_H */ diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h index b943e7a4d..d5ca85ed2 100644 --- a/include/lib/cpus/aarch64/cortex_hercules.h +++ b/include/lib/cpus/aarch64/cortex_hercules.h @@ -27,6 +27,9 @@ ******************************************************************************/ #define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30) +#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1) + /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. ******************************************************************************/ diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_hercules_ae.h new file mode 100644 index 000000000..795563bc3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_hercules_ae.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_HERCULES_AE_H +#define CORTEX_HERCULES_AE_H + +#include <cortex_hercules.h> + +#define CORTEX_HERCULES_AE_MIDR U(0x410FD420) + +#endif /* CORTEX_HERCULES_AE_H */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 044aacaf4..c83824d77 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -43,6 +43,7 @@ .equ CPU_MIDR_SIZE, CPU_WORD_SIZE .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE + .equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE @@ -83,7 +84,8 @@ .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE - .equ CPU_PWR_DWN_OPS, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE + .equ CPU_E_HANDLER_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE + .equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE @@ -139,6 +141,8 @@ * This is a placeholder for future per CPU operations. Currently * some CPUs use this entry to set a function to disable the * workaround for CVE-2018-3639. + * _e_handler: + * This is a placeholder for future per CPU exception handlers. * _power_down_ops: * Comma-separated list of functions to perform power-down * operatios on the CPU. At least one, and up to @@ -149,7 +153,7 @@ * used to handle power down at subsequent levels */ .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ - _extra1:req, _extra2:req, _power_down_ops:vararg + _extra1:req, _extra2:req, _e_handler:req, _power_down_ops:vararg .section cpu_ops, "a" .align 3 .type cpu_ops_\_name, %object @@ -159,6 +163,7 @@ #endif .quad \_extra1 .quad \_extra2 + .quad \_e_handler #ifdef IMAGE_BL31 /* Insert list of functions */ fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops @@ -203,15 +208,21 @@ .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ _power_down_ops:vararg - declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \ + declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, \ \_power_down_ops .endm + .macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \ + _e_handler:req, _power_down_ops:vararg + declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ + 0, 0, \_e_handler, \_power_down_ops + .endm + .macro declare_cpu_ops_wa _name:req, _midr:req, \ _resetfunc:req, _extra1:req, _extra2:req, \ _power_down_ops:vararg declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ - \_extra1, \_extra2, \_power_down_ops + \_extra1, \_extra2, 0, \_power_down_ops .endm #if REPORT_ERRATA diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index f90aa2ea4..b50befa8d 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ /* Neoverse N1 MIDR for revision 0 */ #define NEOVERSE_N1_MIDR U(0x410fd0c0) +/* Exception Syndrome register EC code for IC Trap */ +#define NEOVERSE_N1_EC_IC_TRAP U(0x1f) + /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ @@ -32,6 +35,7 @@ #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) +#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/include/lib/debugfs.h b/include/lib/debugfs.h new file mode 100644 index 000000000..8ed237ae2 --- /dev/null +++ b/include/lib/debugfs.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DEBUGFS_H +#define DEBUGFS_H + +#define NAMELEN 13 /* Maximum length of a file name */ +#define PATHLEN 41 /* Maximum length of a path */ +#define STATLEN 41 /* Size of static part of dir format */ +#define ROOTLEN (2 + 4) /* Size needed to encode root string */ +#define FILNAMLEN (2 + NAMELEN) /* Size needed to encode filename */ +#define DIRLEN (STATLEN + FILNAMLEN + 3*ROOTLEN) /* Size of dir entry */ + +#define KSEEK_SET 0 +#define KSEEK_CUR 1 +#define KSEEK_END 2 + +#define NELEM(tab) (sizeof(tab) / sizeof((tab)[0])) + +typedef unsigned short qid_t; /* FIXME: short type not recommended? */ + +/******************************************************************************* + * This structure contains the necessary information to represent a 9p + * directory. + ******************************************************************************/ +typedef struct { + char name[NAMELEN]; + long length; + unsigned char mode; + unsigned char index; + unsigned char dev; + qid_t qid; +} dir_t; + +/* Permission definitions used as flags */ +#define O_READ (1 << 0) +#define O_WRITE (1 << 1) +#define O_RDWR (1 << 2) +#define O_BIND (1 << 3) +#define O_DIR (1 << 4) +#define O_STAT (1 << 5) + +/* 9p interface */ +int mount(const char *srv, const char *mnt, const char *spec); +int create(const char *name, int flags); +int open(const char *name, int flags); +int close(int fd); +int read(int fd, void *buf, int n); +int write(int fd, void *buf, int n); +int seek(int fd, long off, int whence); +int bind(const char *path, const char *where); +int stat(const char *path, dir_t *dir); + +/* DebugFS initialization */ +void debugfs_init(void); +int debugfs_smc_setup(void); + +/* Debugfs version returned through SMC interface */ +#define DEBUGFS_VERSION (0x000000001U) + +/* Function ID for accessing the debugfs interface */ +#define DEBUGFS_FID_VALUE (0x30U) + +#define is_debugfs_fid(_fid) \ + (((_fid) & FUNCID_NUM_MASK) == DEBUGFS_FID_VALUE) + +/* Error code for debugfs SMC interface failures */ +#define DEBUGFS_E_INVALID_PARAMS (-2) +#define DEBUGFS_E_DENIED (-3) + +uintptr_t debugfs_smc_handler(unsigned int smc_fid, + u_register_t cmd, + u_register_t arg2, + u_register_t arg3, + u_register_t arg4, + void *cookie, + void *handle, + uintptr_t flags); + +#endif /* DEBUGFS_H */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index a76a59b78..7a1f3a3a8 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -59,7 +59,7 @@ #define CTX_RUNTIME_SP U(0x10) #define CTX_SPSR_EL3 U(0x18) #define CTX_ELR_EL3 U(0x20) -#define CTX_UNUSED U(0x28) +#define CTX_PMCR_EL0 U(0x28) #define CTX_EL3STATE_END U(0x30) /******************************************************************************* @@ -91,22 +91,21 @@ #define CTX_AFSR1_EL1 U(0x98) #define CTX_CONTEXTIDR_EL1 U(0xa0) #define CTX_VBAR_EL1 U(0xa8) -#define CTX_PMCR_EL0 U(0xb0) /* * If the platform is AArch64-only, there is no need to save and restore these * AArch32 registers. */ #if CTX_INCLUDE_AARCH32_REGS -#define CTX_SPSR_ABT U(0xc0) /* Align to the next 16 byte boundary */ -#define CTX_SPSR_UND U(0xc8) -#define CTX_SPSR_IRQ U(0xd0) -#define CTX_SPSR_FIQ U(0xd8) -#define CTX_DACR32_EL2 U(0xe0) -#define CTX_IFSR32_EL2 U(0xe8) -#define CTX_AARCH32_END U(0xf0) /* Align to the next 16 byte boundary */ +#define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ +#define CTX_SPSR_UND U(0xb8) +#define CTX_SPSR_IRQ U(0xc0) +#define CTX_SPSR_FIQ U(0xc8) +#define CTX_DACR32_EL2 U(0xd0) +#define CTX_IFSR32_EL2 U(0xd8) +#define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ #else -#define CTX_AARCH32_END U(0xc0) /* Align to the next 16 byte boundary */ +#define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ #endif /* CTX_INCLUDE_AARCH32_REGS */ /* @@ -124,10 +123,22 @@ #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END #endif /* NS_TIMER_SWITCH */ +#if CTX_INCLUDE_MTE_REGS +#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) +#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) +#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) +#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) + +/* Align to the next 16 byte boundary */ +#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) +#else +#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END +#endif /* CTX_INCLUDE_MTE_REGS */ + /* * End of system registers. */ -#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_END +#define CTX_SYSREGS_END CTX_MTE_REGS_END /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' @@ -201,8 +212,7 @@ #define CTX_PACDBKEY_HI U(0x38) #define CTX_PACGAKEY_LO U(0x40) #define CTX_PACGAKEY_HI U(0x48) -#define CTX_PACGAKEY_END U(0x50) -#define CTX_PAUTH_REGS_END U(0x60) /* Align to the next 16 byte boundary */ +#define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ #else #define CTX_PAUTH_REGS_END U(0) #endif /* CTX_INCLUDE_PAUTH_REGS */ diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 7c996d124..17955e3a8 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -45,7 +45,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, uint32_t bit_pos, uint32_t value); void cm_set_next_eret_context(uint32_t security_state); -uint32_t cm_get_scr_el3(uint32_t security_state); +u_register_t cm_get_scr_el3(uint32_t security_state); /* Inline definitions */ diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h index 55db4cff6..54261358e 100644 --- a/include/lib/el3_runtime/cpu_data.h +++ b/include/lib/el3_runtime/cpu_data.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,23 +11,37 @@ #include <bl31/ehf.h> +/* Size of psci_cpu_data structure */ +#define PSCI_CPU_DATA_SIZE 12 + #ifdef __aarch64__ -/* Offsets for the cpu_data structure */ -#define CPU_DATA_CRASH_BUF_OFFSET 0x18 +/* 8-bytes aligned size of psci_cpu_data structure */ +#define PSCI_CPU_DATA_SIZE_ALIGNED ((PSCI_CPU_DATA_SIZE + 7) & ~7) + +/* Offset of cpu_ops_ptr, size 8 bytes */ +#define CPU_DATA_CPU_OPS_PTR 0x10 + +#if ENABLE_PAUTH +/* 8-bytes aligned offset of apiakey[2], size 16 bytes */ +#define CPU_DATA_APIAKEY_OFFSET (0x18 + PSCI_CPU_DATA_SIZE_ALIGNED) +#define CPU_DATA_CRASH_BUF_OFFSET (CPU_DATA_APIAKEY_OFFSET + 0x10) +#else +#define CPU_DATA_CRASH_BUF_OFFSET (0x18 + PSCI_CPU_DATA_SIZE_ALIGNED) +#endif /* ENABLE_PAUTH */ + /* need enough space in crash buffer to save 8 registers */ #define CPU_DATA_CRASH_BUF_SIZE 64 -#define CPU_DATA_CPU_OPS_PTR 0x10 -#else /* __aarch64__ */ +#else /* !__aarch64__ */ #if CRASH_REPORTING #error "Crash reporting is not supported in AArch32" #endif #define CPU_DATA_CPU_OPS_PTR 0x0 -#define CPU_DATA_CRASH_BUF_OFFSET 0x4 +#define CPU_DATA_CRASH_BUF_OFFSET (0x4 + PSCI_CPU_DATA_SIZE) -#endif /* __aarch64__ */ +#endif /* __aarch64__ */ #if CRASH_REPORTING #define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \ @@ -88,13 +102,16 @@ typedef struct cpu_data { void *cpu_context[2]; #endif uintptr_t cpu_ops_ptr; + struct psci_cpu_data psci_svc_cpu_data; +#if ENABLE_PAUTH + uint64_t apiakey[2]; +#endif #if CRASH_REPORTING u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; #endif #if ENABLE_RUNTIME_INSTRUMENTATION uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT]; #endif - struct psci_cpu_data psci_svc_cpu_data; #if PLAT_PCPU_DATA_SIZE uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; #endif @@ -105,6 +122,12 @@ typedef struct cpu_data { extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; +#if ENABLE_PAUTH +CASSERT(CPU_DATA_APIAKEY_OFFSET == __builtin_offsetof + (cpu_data_t, apiakey), + assert_cpu_data_crash_stack_offset_mismatch); +#endif + #if CRASH_REPORTING /* verify assembler offsets match data structures */ CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h new file mode 100644 index 000000000..2e780dec2 --- /dev/null +++ b/include/lib/extensions/pauth.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PAUTH_H +#define PAUTH_H + +/******************************************************************************* + * ARMv8.3-PAuth support functions + ******************************************************************************/ + +/* Disable ARMv8.3 pointer authentication in EL1/EL3 */ +void pauth_disable_el1(void); +void pauth_disable_el3(void); + +#endif /* PAUTH_H */ diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h index 1babfade3..36dc20bd4 100644 --- a/include/lib/libc/aarch32/stddef_.h +++ b/include/lib/libc/aarch32/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,4 @@ typedef unsigned int size_t; #define SIZET_ #endif -#ifndef _PTRDIFF_T -typedef long ptrdiff_t; -#define _PTRDIFF_T -#endif - #endif /* STDDEF__H */ diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h deleted file mode 100644 index 4f494859f..000000000 --- a/include/lib/libc/aarch32/stdint_.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define INT8_MAX 0x7F -#define INT8_MIN (-INT8_MAX - 1) -#define UINT8_MAX 0xFFU - -#define INT16_MAX 0x7FFF -#define INT16_MIN (-INT16_MAX - 1) -#define UINT16_MAX 0xFFFFU - -#define INT32_MAX 0x7FFFFFFF -#define INT32_MIN (-INT32_MAX - 1) -#define UINT32_MAX 0xFFFFFFFFU - -#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -#define INT64_MIN (-INT64_MAX - 1LL) -#define UINT64_MAX 0xFFFFFFFFFFFFFFFFULL - -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define UINT_LEAST8_MAX UINT8_MAX - -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define UINT_LEAST16_MAX UINT16_MAX - -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define UINT_LEAST32_MAX UINT32_MAX - -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST8_MAX INT32_MAX -#define UINT_FAST8_MAX UINT32_MAX - -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST16_MAX INT32_MAX -#define UINT_FAST16_MAX UINT32_MAX - -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define UINT_FAST32_MAX UINT32_MAX - -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST64_MAX UINT64_MAX - -#define INTPTR_MIN INT32_MIN -#define INTPTR_MAX INT32_MAX -#define UINTPTR_MAX UINT32_MAX - -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -#define PTRDIFF_MIN INT32_MIN -#define PTRDIFF_MAX INT32_MAX - -#define SIZE_MAX UINT32_MAX - -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL - -#define INTMAX_C(x) x ## LL -#define UINTMAX_C(x) x ## ULL - -typedef signed char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - -typedef signed char int8_least_t; -typedef short int16_least_t; -typedef int int32_least_t; -typedef long long int64_least_t; - -typedef unsigned char uint8_least_t; -typedef unsigned short uint16_least_t; -typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; - -typedef int int8_fast_t; -typedef int int16_fast_t; -typedef int int32_fast_t; -typedef long long int64_fast_t; - -typedef unsigned int uint8_fast_t; -typedef unsigned int uint16_fast_t; -typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; - -typedef long intptr_t; -typedef unsigned long uintptr_t; - -typedef long long intmax_t; -typedef unsigned long long uintmax_t; - -typedef long register_t; -typedef unsigned long u_register_t; diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h index 50d3cc2ed..5e49425cb 100644 --- a/include/lib/libc/aarch32/stdio_.h +++ b/include/lib/libc/aarch32/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,6 @@ #ifndef STDIO__H #define STDIO__H -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - #ifndef SSIZET_ typedef int ssize_t; #define SSIZET_ diff --git a/include/lib/libc/aarch32/stdlib_.h b/include/lib/libc/aarch32/stdlib_.h deleted file mode 100644 index 9c07857a5..000000000 --- a/include/lib/libc/aarch32/stdlib_.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STDLIB__H -#define STDLIB__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#define EXIT_FAILURE 1 -#define EXIT_SUCCESS 0 - -#endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch32/string_.h b/include/lib/libc/aarch32/string_.h deleted file mode 100644 index 4e139b0db..000000000 --- a/include/lib/libc/aarch32/string_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STRING__H -#define STRING__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#endif /* STRING__H */ diff --git a/include/lib/libc/aarch32/time_.h b/include/lib/libc/aarch32/time_.h deleted file mode 100644 index a9169c293..000000000 --- a/include/lib/libc/aarch32/time_.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TIME__H -#define TIME__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -typedef long int time_t; - -#endif /* TIME__H */ diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h index b7d8209af..6ecc6067c 100644 --- a/include/lib/libc/aarch64/stddef_.h +++ b/include/lib/libc/aarch64/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,4 @@ typedef unsigned long size_t; #define SIZET_ #endif -#ifndef _PTRDIFF_T -typedef long ptrdiff_t; -#define _PTRDIFF_T -#endif - #endif /* STDDEF__H */ diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h deleted file mode 100644 index b17a435b0..000000000 --- a/include/lib/libc/aarch64/stdint_.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define INT8_MAX 0x7F -#define INT8_MIN (-INT8_MAX - 1) -#define UINT8_MAX 0xFFU - -#define INT16_MAX 0x7FFF -#define INT16_MIN (-INT16_MAX - 1) -#define UINT16_MAX 0xFFFFU - -#define INT32_MAX 0x7FFFFFFF -#define INT32_MIN (-INT32_MAX - 1) -#define UINT32_MAX 0xFFFFFFFFU - -#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -#define INT64_MIN (-INT64_MAX - 1LL) -#define UINT64_MAX 0xFFFFFFFFFFFFFFFFULL - -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define UINT_LEAST8_MAX UINT8_MAX - -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define UINT_LEAST16_MAX UINT16_MAX - -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define UINT_LEAST32_MAX UINT32_MAX - -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST8_MAX INT32_MAX -#define UINT_FAST8_MAX UINT32_MAX - -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST16_MAX INT32_MAX -#define UINT_FAST16_MAX UINT32_MAX - -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define UINT_FAST32_MAX UINT32_MAX - -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST64_MAX UINT64_MAX - -#define INTPTR_MIN INT64_MIN -#define INTPTR_MAX INT64_MAX -#define UINTPTR_MAX UINT64_MAX - -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -#define PTRDIFF_MIN INT64_MIN -#define PTRDIFF_MAX INT64_MAX - -#define SIZE_MAX UINT64_MAX - -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL - -#define INTMAX_C(x) x ## L -#define UINTMAX_C(x) x ## ULL - -typedef signed char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - -typedef signed char int8_least_t; -typedef short int16_least_t; -typedef int int32_least_t; -typedef long long int64_least_t; - -typedef unsigned char uint8_least_t; -typedef unsigned short uint16_least_t; -typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; - -typedef int int8_fast_t; -typedef int int16_fast_t; -typedef int int32_fast_t; -typedef long long int64_fast_t; - -typedef unsigned int uint8_fast_t; -typedef unsigned int uint16_fast_t; -typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; - -typedef long intptr_t; -typedef unsigned long uintptr_t; - -typedef long intmax_t; -typedef unsigned long uintmax_t; - -typedef long register_t; -typedef unsigned long u_register_t; - -typedef __int128 int128_t; -typedef unsigned __int128 uint128_t; diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h index 09b0172dd..afaeadc21 100644 --- a/include/lib/libc/aarch64/stdio_.h +++ b/include/lib/libc/aarch64/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,6 @@ #ifndef STDIO__H #define STDIO__H -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - #ifndef SSIZET_ typedef long ssize_t; #define SSIZET_ diff --git a/include/lib/libc/aarch64/stdlib_.h b/include/lib/libc/aarch64/stdlib_.h deleted file mode 100644 index 81a39d14a..000000000 --- a/include/lib/libc/aarch64/stdlib_.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STDLIB__H -#define STDLIB__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#define EXIT_FAILURE 1 -#define EXIT_SUCCESS 0 - -#endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch64/string_.h b/include/lib/libc/aarch64/string_.h deleted file mode 100644 index 71c51a6cd..000000000 --- a/include/lib/libc/aarch64/string_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STRING__H -#define STRING__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#endif /* STRING__H */ diff --git a/include/lib/libc/aarch64/time_.h b/include/lib/libc/aarch64/time_.h deleted file mode 100644 index 68ab1b8dd..000000000 --- a/include/lib/libc/aarch64/time_.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TIME__H -#define TIME__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -typedef long int time_t; - -#endif /* TIME__H */ diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h index d04f9dc04..486bbc290 100644 --- a/include/lib/libc/assert.h +++ b/include/lib/libc/assert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,12 +30,12 @@ #endif /* ENABLE_ASSERTIONS */ #if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -__dead2 void __assert(const char *file, unsigned int line, +void __dead2 __assert(const char *file, unsigned int line, const char *assertion); #elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO -__dead2 void __assert(const char *file, unsigned int line); +void __dead2 __assert(const char *file, unsigned int line); #else -__dead2 void __assert(void); +void __dead2 __assert(void); #endif #endif /* ASSERT_H */ diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h index c9957bdb1..58a519e52 100644 --- a/include/lib/libc/stddef.h +++ b/include/lib/libc/stddef.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -13,6 +13,11 @@ #include <stddef_.h> +#ifndef _PTRDIFF_T +typedef long ptrdiff_t; +#define _PTRDIFF_T +#endif + #ifndef NULL #define NULL ((void *) 0) #endif diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h index d44a973f1..818870e16 100644 --- a/include/lib/libc/stdint.h +++ b/include/lib/libc/stdint.h @@ -4,13 +4,135 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STDINT_H #define STDINT_H -#include <stdint_.h> +#include <limits.h> + +#define INT8_MAX CHAR_MAX +#define INT8_MIN CHAR_MIN +#define UINT8_MAX UCHAR_MAX + +#define INT16_MAX SHRT_MAX +#define INT16_MIN SHRT_MIN +#define UINT16_MAX USHRT_MAX + +#define INT32_MAX INT_MAX +#define INT32_MIN INT_MIN +#define UINT32_MAX UINT_MAX + +#define INT64_MAX LLONG_MAX +#define INT64_MIN LLONG_MIN +#define UINT64_MAX ULLONG_MAX + +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST8_MAX INT8_MAX +#define UINT_LEAST8_MAX UINT8_MAX + +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST16_MAX INT16_MAX +#define UINT_LEAST16_MAX UINT16_MAX + +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST32_MAX INT32_MAX +#define UINT_LEAST32_MAX UINT32_MAX + +#define INT_LEAST64_MIN INT64_MIN +#define INT_LEAST64_MAX INT64_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST8_MAX INT32_MAX +#define UINT_FAST8_MAX UINT32_MAX + +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST16_MAX INT32_MAX +#define UINT_FAST16_MAX UINT32_MAX + +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST32_MAX INT32_MAX +#define UINT_FAST32_MAX UINT32_MAX + +#define INT_FAST64_MIN INT64_MIN +#define INT_FAST64_MAX INT64_MAX +#define UINT_FAST64_MAX UINT64_MAX + +#define INTPTR_MIN LONG_MIN +#define INTPTR_MAX LONG_MAX +#define UINTPTR_MAX ULONG_MAX + +#define INTMAX_MIN LLONG_MIN +#define INTMAX_MAX LLONG_MAX +#define UINTMAX_MAX ULLONG_MAX + +#define PTRDIFF_MIN LONG_MIN +#define PTRDIFF_MAX LONG_MAX + +#define SIZE_MAX ULONG_MAX + +#define INT8_C(x) x +#define INT16_C(x) x +#define INT32_C(x) x +#define INT64_C(x) x ## LL + +#define UINT8_C(x) x +#define UINT16_C(x) x +#define UINT32_C(x) x ## U +#define UINT64_C(x) x ## ULL + +#define INTMAX_C(x) x ## LL +#define UINTMAX_C(x) x ## ULL + +typedef signed char int8_t; +typedef short int16_t; +typedef int int32_t; +typedef long long int64_t; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; + +typedef signed char int8_least_t; +typedef short int16_least_t; +typedef int int32_least_t; +typedef long long int64_least_t; + +typedef unsigned char uint8_least_t; +typedef unsigned short uint16_least_t; +typedef unsigned int uint32_least_t; +typedef unsigned long long uint64_least_t; + +typedef int int8_fast_t; +typedef int int16_fast_t; +typedef int int32_fast_t; +typedef long long int64_fast_t; + +typedef unsigned int uint8_fast_t; +typedef unsigned int uint16_fast_t; +typedef unsigned int uint32_fast_t; +typedef unsigned long long uint64_fast_t; + +typedef long intptr_t; +typedef unsigned long uintptr_t; + +/* +* Conceptually, these are supposed to be the largest integers representable in C, +* but GCC and Clang define them as long long for compatibility. +*/ +typedef long long intmax_t; +typedef unsigned long long uintmax_t; + +typedef long register_t; +typedef unsigned long u_register_t; + +#ifdef __aarch64__ +typedef __int128 int128_t; +typedef unsigned __int128 uint128_t; +#endif /* __aarch64__ */ #endif /* STDINT_H */ diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h index 3d9323efa..2d9e6557b 100644 --- a/include/lib/libc/stdio.h +++ b/include/lib/libc/stdio.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -12,12 +12,9 @@ #define STDIO_H #include <cdefs.h> +#include <stddef.h> #include <stdio_.h> -#ifndef NULL -#define NULL ((void *) 0) -#endif - #define EOF -1 int printf(const char *fmt, ...) __printflike(1, 2); diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index edd6265f5..24e7bae2f 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h @@ -4,18 +4,17 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STDLIB_H #define STDLIB_H -#include <stdlib_.h> +#include <stddef.h> -#ifndef NULL -#define NULL ((void *) 0) -#endif +#define EXIT_FAILURE 1 +#define EXIT_SUCCESS 0 #define _ATEXIT_MAX 1 diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index ee6eeacef..71774b0c8 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -4,18 +4,14 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STRING_H #define STRING_H -#include <string_.h> - -#ifndef NULL -#define NULL ((void *) 0) -#endif +#include <stddef.h> void *memcpy(void *dst, const void *src, size_t len); void *memmove(void *dst, const void *src, size_t len); @@ -23,6 +19,7 @@ int memcmp(const void *s1, const void *s2, size_t len); int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, size_t n); void *memchr(const void *src, int c, size_t len); +void *memrchr(const void *src, int c, size_t len); char *strchr(const char *s, int c); void *memset(void *dst, int val, size_t count); size_t strlen(const char *s); diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h index 71d3e7ec9..c1c95e586 100644 --- a/include/lib/libc/time.h +++ b/include/lib/libc/time.h @@ -4,17 +4,15 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef TIME_H #define TIME_H -#include <time_.h> +#include <stddef.h> -#ifndef NULL -#define NULL ((void *) 0) -#endif +typedef long int time_t; #endif /* TIME_H */ diff --git a/include/lib/pmf/aarch32/pmf_asm_macros.S b/include/lib/pmf/aarch32/pmf_asm_macros.S new file mode 100644 index 000000000..1dbb408ca --- /dev/null +++ b/include/lib/pmf/aarch32/pmf_asm_macros.S @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMF_ASM_MACROS_S +#define PMF_ASM_MACROS_S + +#define PMF_TS_SIZE 8 + + /* + * This macro calculates the address of the per-cpu timestamp + * for the given service name and local timestamp id. + * Clobbers: r0 - r4 + */ + .macro pmf_calc_timestamp_addr _name, _tid + mov r4, lr + bl plat_my_core_pos + mov lr, r4 + ldr r1, =__PERCPU_TIMESTAMP_SIZE__ + mov r2, #(\_tid * PMF_TS_SIZE) + mla r0, r0, r1, r2 + ldr r1, =pmf_ts_mem_\_name + add r0, r0, r1 + .endm + +#endif /* PMF_ASM_MACROS_S */ diff --git a/include/lib/pmf/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S index 5f3e6b7ec..5f3e6b7ec 100644 --- a/include/lib/pmf/pmf_asm_macros.S +++ b/include/lib/pmf/aarch64/pmf_asm_macros.S diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index df7c9ff31..3fc8e3863 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -54,108 +54,6 @@ #define PMF_PSCI_STAT_SVC_ID 0 #define PMF_RT_INSTR_SVC_ID 1 -#if ENABLE_PMF -/* - * Convenience macros for capturing time-stamp. - */ -#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \ - void pmf_capture_timestamp_with_cache_maint_ ## _name( \ - unsigned int tid, \ - unsigned long long ts); \ - void pmf_capture_timestamp_ ## _name( \ - unsigned int tid, \ - unsigned long long ts); - -#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \ - do { \ - unsigned long long ts = read_cntpct_el0(); \ - if (((_flags) & PMF_CACHE_MAINT) != 0U) \ - pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\ - else \ - pmf_capture_timestamp_ ## _name((_tid), ts); \ - } while (0) - -#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \ - do { \ - (_tsval) = read_cntpct_el0(); \ - CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\ - if (((_flags) & PMF_CACHE_MAINT) != 0U) \ - pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\ - else \ - pmf_capture_timestamp_ ## _name((_tid), (_tsval));\ - } while (0) - -#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \ - do { \ - CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\ - if (((_flags) & PMF_CACHE_MAINT) != 0U) \ - pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\ - else \ - pmf_capture_timestamp_ ## _name((_tid), (_wrval));\ - } while (0) - -/* - * Convenience macros for retrieving time-stamp. - */ -#define PMF_DECLARE_GET_TIMESTAMP(_name) \ - unsigned long long pmf_get_timestamp_by_index_ ## _name(\ - unsigned int tid, \ - unsigned int cpuid, \ - unsigned int flags); \ - unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\ - unsigned int tid, \ - u_register_t mpidr, \ - unsigned int flags); - -#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\ - _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags) - -#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\ - _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags) - -/* Convenience macros to register a PMF service.*/ -/* - * This macro is used to register a PMF Service. It allocates PMF memory - * and defines default service-specific PMF functions. - */ -#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ - PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \ - PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ - PMF_DEFINE_GET_TIMESTAMP(_name) - -/* - * This macro is used to register a PMF service, including an - * SMC interface to that service. - */ -#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\ - PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ - PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \ - _svcid, _totalid, NULL, \ - pmf_get_timestamp_by_mpidr_ ## _name) - -/* - * This macro is used to register a PMF service that has an SMC interface - * but provides its own service-specific PMF functions. - */ -#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ - _init, _getts) \ - PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ - _init, _getts) - -#else - -#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) -#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags) -#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ - _init, _getts) -#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) -#define PMF_DECLARE_GET_TIMESTAMP(_name) -#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) -#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval) -#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval) - -#endif /* ENABLE_PMF */ - /******************************************************************************* * Function & variable prototypes ******************************************************************************/ diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index e6798a7ce..db38e556a 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -43,6 +43,108 @@ typedef struct pmf_svc_desc { pmf_svc_get_ts_t get_ts; } pmf_svc_desc_t; +#if ENABLE_PMF +/* + * Convenience macros for capturing time-stamp. + */ +#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \ + void pmf_capture_timestamp_with_cache_maint_ ## _name( \ + unsigned int tid, \ + unsigned long long ts); \ + void pmf_capture_timestamp_ ## _name( \ + unsigned int tid, \ + unsigned long long ts); + +#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \ + do { \ + unsigned long long ts = read_cntpct_el0(); \ + if (((_flags) & PMF_CACHE_MAINT) != 0U) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\ + else \ + pmf_capture_timestamp_ ## _name((_tid), ts); \ + } while (0) + +#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \ + do { \ + (_tsval) = read_cntpct_el0(); \ + CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\ + if (((_flags) & PMF_CACHE_MAINT) != 0U) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\ + else \ + pmf_capture_timestamp_ ## _name((_tid), (_tsval));\ + } while (0) + +#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \ + do { \ + CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\ + if (((_flags) & PMF_CACHE_MAINT) != 0U) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\ + else \ + pmf_capture_timestamp_ ## _name((_tid), (_wrval));\ + } while (0) + +/* + * Convenience macros for retrieving time-stamp. + */ +#define PMF_DECLARE_GET_TIMESTAMP(_name) \ + unsigned long long pmf_get_timestamp_by_index_ ## _name(\ + unsigned int tid, \ + unsigned int cpuid, \ + unsigned int flags); \ + unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\ + unsigned int tid, \ + u_register_t mpidr, \ + unsigned int flags); + +#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\ + _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags) + +#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\ + _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags) + +/* Convenience macros to register a PMF service.*/ +/* + * This macro is used to register a PMF Service. It allocates PMF memory + * and defines default service-specific PMF functions. + */ +#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ + PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \ + PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ + PMF_DEFINE_GET_TIMESTAMP(_name) + +/* + * This macro is used to register a PMF service, including an + * SMC interface to that service. + */ +#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\ + PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ + PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \ + _svcid, _totalid, NULL, \ + pmf_get_timestamp_by_mpidr_ ## _name) + +/* + * This macro is used to register a PMF service that has an SMC interface + * but provides its own service-specific PMF functions. + */ +#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ + _init, _getts) \ + PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ + _init, _getts) + +#else + +#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) +#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags) +#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ + _init, _getts) +#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) +#define PMF_DECLARE_GET_TIMESTAMP(_name) +#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) +#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval) +#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval) + +#endif /* ENABLE_PMF */ + /* * Convenience macro to allocate memory for a PMF service. * @@ -69,9 +171,6 @@ typedef struct pmf_svc_desc { #define PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ void pmf_capture_timestamp_ ## _name( \ unsigned int tid, \ - unsigned long long ts); \ - void pmf_capture_timestamp_ ## _name( \ - unsigned int tid, \ unsigned long long ts) \ { \ CASSERT(_flags, select_proper_config); \ @@ -84,9 +183,6 @@ typedef struct pmf_svc_desc { } \ void pmf_capture_timestamp_with_cache_maint_ ## _name( \ unsigned int tid, \ - unsigned long long ts); \ - void pmf_capture_timestamp_with_cache_maint_ ## _name( \ - unsigned int tid, \ unsigned long long ts) \ { \ CASSERT(_flags, select_proper_config); \ @@ -105,8 +201,6 @@ typedef struct pmf_svc_desc { */ #define PMF_DEFINE_GET_TIMESTAMP(_name) \ unsigned long long pmf_get_timestamp_by_index_ ## _name( \ - unsigned int tid, unsigned int cpuid, unsigned int flags);\ - unsigned long long pmf_get_timestamp_by_index_ ## _name( \ unsigned int tid, unsigned int cpuid, unsigned int flags)\ { \ PMF_VALIDATE_TID(_name, tid); \ @@ -114,8 +208,6 @@ typedef struct pmf_svc_desc { return __pmf_get_timestamp(base_addr, tid, cpuid, flags);\ } \ unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \ - unsigned int tid, u_register_t mpidr, unsigned int flags);\ - unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \ unsigned int tid, u_register_t mpidr, unsigned int flags)\ { \ PMF_VALIDATE_TID(_name, tid); \ diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index 04e5e3d72..b56e98b5f 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ #ifdef PLAT_NUM_PWR_DOMAINS #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS #else -#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) +#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) #endif #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ @@ -301,6 +301,8 @@ typedef struct plat_psci_ops { const psci_power_state_t *target_state); void (*pwr_domain_suspend)(const psci_power_state_t *target_state); void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish_late)( + const psci_power_state_t *target_state); void (*pwr_domain_suspend_finish)( const psci_power_state_t *target_state); void __dead2 (*pwr_domain_pwr_down_wfi)( diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h index 006c7b750..24b030cfd 100644 --- a/include/lib/semihosting.h +++ b/include/lib/semihosting.h @@ -23,6 +23,7 @@ #define SEMIHOSTING_SYS_REMOVE 0x0E #define SEMIHOSTING_SYS_SYSTEM 0x12 #define SEMIHOSTING_SYS_ERRNO 0x13 +#define SEMIHOSTING_SYS_EXIT 0x18 #define FOPEN_MODE_R 0x0 #define FOPEN_MODE_RB 0x1 @@ -54,5 +55,6 @@ long semihosting_download_file(const char *file_name, void semihosting_write_char(char character); void semihosting_write_string(char *string); char semihosting_read_char(void); +void semihosting_exit(uint32_t reason, uint32_t subcode); #endif /* SEMIHOSTING_H */ diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 76e60231f..5e13e6f0a 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ SMCCC_VERSION_MINOR_SHIFT)) #define SMCCC_MAJOR_VERSION U(1) -#define SMCCC_MINOR_VERSION U(1) +#define SMCCC_MINOR_VERSION U(2) /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention @@ -41,6 +41,8 @@ #define FUNCID_NUM_MASK U(0xffff) #define FUNCID_NUM_WIDTH U(16) +#define GET_SMC_NUM(id) (((id) >> FUNCID_NUM_SHIFT) & \ + FUNCID_NUM_MASK) #define GET_SMC_TYPE(id) (((id) >> FUNCID_TYPE_SHIFT) & \ FUNCID_TYPE_MASK) #define GET_SMC_CC(id) (((id) >> FUNCID_CC_SHIFT) & \ @@ -83,6 +85,12 @@ #define SMC_UNK -1 #define SMC_PREEMPTED -2 /* Not defined by the SMCCC */ +/* Return codes for Arm Architecture Service SMC calls */ +#define SMC_ARCH_CALL_SUCCESS 0 +#define SMC_ARCH_CALL_NOT_SUPPORTED -1 +#define SMC_ARCH_CALL_NOT_REQUIRED -2 +#define SMC_ARCH_CALL_INVAL_PARAM -3 + /* Various flags passed to SMC handlers */ #define SMC_FROM_SECURE (U(0) << 0) #define SMC_FROM_NON_SECURE (U(1) << 0) diff --git a/include/lib/sprt/sprt_common.h b/include/lib/sprt/sprt_common.h deleted file mode 100644 index 27d502749..000000000 --- a/include/lib/sprt/sprt_common.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPRT_COMMON_H -#define SPRT_COMMON_H - -#define SPRT_MAX_MSG_ARGS 6 - -/* - * Message types supported. - */ -#define SPRT_MSG_TYPE_SERVICE_HANDLE_OPEN 1 -#define SPRT_MSG_TYPE_SERVICE_HANDLE_CLOSE 2 -/* TODO: Add other types of SPRT messages. */ -#define SPRT_MSG_TYPE_SERVICE_TUN_REQUEST 10 - -/* - * Struct that defines the layout of the fields corresponding to a request in - * shared memory. - */ -struct __attribute__((__packed__)) sprt_queue_entry_message { - uint32_t type; /* Type of message (result of an SPCI call). */ - uint16_t client_id; /* SPCI client ID */ - uint16_t service_handle;/* SPCI service handle */ - uint32_t session_id; /* Optional SPCI session ID */ - uint32_t token; /* SPCI request token */ - uint64_t args[SPRT_MAX_MSG_ARGS]; -}; - -#define SPRT_QUEUE_ENTRY_MSG_SIZE (sizeof(struct sprt_queue_entry_message)) - -#define SPRT_QUEUE_NUM_BLOCKING 0 -#define SPRT_QUEUE_NUM_NON_BLOCKING 1 - -#endif /* SPRT_COMMON_H */ diff --git a/include/lib/sprt/sprt_host.h b/include/lib/sprt/sprt_host.h deleted file mode 100644 index f888141dd..000000000 --- a/include/lib/sprt/sprt_host.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef SPRT_HOST_H -#define SPRT_HOST_H - -#include <stddef.h> - -#include "sprt_common.h" - -/* - * Initialize the specified buffer to be used by SPM. - */ -void sprt_initialize_queues(void *buffer_base, size_t buffer_size); - -/* - * Push a message to the queue number `queue_num` in a buffer that has been - * initialized by `sprt_initialize_queues`. - */ -int sprt_push_message(void *buffer_base, - const struct sprt_queue_entry_message *message, - int queue_num); - -#endif /* SPRT_HOST_H */ diff --git a/include/lib/utils.h b/include/lib/utils.h index cdb125cfa..17ee93694 100644 --- a/include/lib/utils.h +++ b/include/lib/utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,13 +79,11 @@ void zeromem(void *mem, u_register_t length); * which is constant and does not depend on the execute address of the binary. */ #define DEFINE_LOAD_SYM_ADDR(_name) \ -static inline u_register_t load_addr_## _name(void) \ -{ \ - u_register_t v; \ - /* Create a void reference to silence compiler */ \ - (void) _name; \ - __asm__ volatile ("ldr %0, =" #_name : "=r" (v)); \ - return v; \ +static inline u_register_t load_addr_## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("ldr %0, =" #_name : "=r" (v) : "X" (#_name));\ + return v; \ } /* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */ diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 35ae33a68..23f59bdc3 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -77,6 +77,15 @@ _x > _y ? _x : _y; \ }) +#define CLAMP(x, min, max) __extension__ ({ \ + __typeof__(x) _x = (x); \ + __typeof__(min) _min = (min); \ + __typeof__(max) _max = (max); \ + (void)(&_x == &_min); \ + (void)(&_x == &_max); \ + (_x > _max ? _max : (_x < _min ? _min : _x)); \ +}) + /* * The round_up() macro rounds up a value to the given boundary in a * type-agnostic yet type-safe manner. The boundary must be a power of two. diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 53bd13fc0..b419c853e 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -21,7 +21,7 @@ /* Special value used to verify platform parameters from BL2 to BL31 */ #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) -#define ARM_SYSTEM_COUNT 1 +#define ARM_SYSTEM_COUNT U(1) #define ARM_CACHE_WRITEBACK_SHIFT 6 @@ -403,21 +403,16 @@ #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) #elif (RESET_TO_BL31) - -# if ENABLE_PIE +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +# if !ENABLE_PIE +# error "BL31 must be a PIE if RESET_TO_BL31=1." +#endif /* * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely * used for building BL31 and not used for loading BL31. */ # define BL31_BASE 0x0 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE -# else -/* Put BL31_BASE in the middle of the Trusted SRAM.*/ -# define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ - (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) -# define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) -# endif /* ENABLE_PIE */ - #else /* Put BL31 below BL2 in the Trusted SRAM.*/ #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ @@ -462,7 +457,7 @@ * Trusted DRAM (if available) or the DRAM region secured by the TrustZone * controller. */ -# if ENABLE_SPM +# if SPM_MM # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) @@ -505,9 +500,9 @@ * SPD and no SPM, as they are the only ones that can be used as BL32. */ #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME -# if defined(SPD_none) && !ENABLE_SPM +# if defined(SPD_none) && !SPM_MM # undef BL32_BASE -# endif /* defined(SPD_none) && !ENABLE_SPM */ +# endif /* defined(SPD_none) && !SPM_MM*/ #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ /******************************************************************************* diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S index 8f22170fe..b5bf47365 100644 --- a/include/plat/arm/common/arm_reclaim_init.ld.S +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,10 +27,9 @@ SECTIONS "BL31 init has exceeded progbits limit.") #endif -#if RECLAIM_INIT_CODE ASSERT(__INIT_CODE_END__ <= __STACKS_END__, "Init code ends past the end of the stacks") -#endif + } #endif /* ARM_RECLAIM_INIT_LD_S */ diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h index 16573ce6a..85fdb289f 100644 --- a/include/plat/arm/common/arm_sip_svc.h +++ b/include/plat/arm/common/arm_sip_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,9 +16,15 @@ /* U(0x8200ff02) is reserved */ #define ARM_SIP_SVC_VERSION U(0x8200ff03) +/* PMF_SMC_GET_TIMESTAMP_32 0x82000010 */ +/* PMF_SMC_GET_TIMESTAMP_64 0xC2000010 */ + /* Function ID for requesting state switch of lower EL */ #define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020) +/* DEBUGFS_SMC_32 0x82000030U */ +/* DEBUGFS_SMC_64 0xC2000030U */ + /* ARM SiP Service Calls version numbers */ #define ARM_SIP_SVC_VERSION_MAJOR U(0x0) #define ARM_SIP_SVC_VERSION_MINOR U(0x2) diff --git a/include/plat/arm/common/arm_spm_def.h b/include/plat/arm/common/arm_spm_def.h index 16c806ba6..c43583de2 100644 --- a/include/plat/arm/common/arm_spm_def.h +++ b/include/plat/arm/common/arm_spm_def.h @@ -10,31 +10,6 @@ #include <lib/xlat_tables/xlat_tables_defs.h> /* - * Reserve 4 MiB for binaries of Secure Partitions and Resource Description - * blobs. - */ -#define PLAT_SP_PACKAGE_BASE BL32_BASE -#define PLAT_SP_PACKAGE_SIZE ULL(0x400000) - -#define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \ - PLAT_SP_PACKAGE_BASE, \ - PLAT_SP_PACKAGE_SIZE, \ - MT_MEMORY | MT_RO | MT_SECURE) -#define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \ - PLAT_SP_PACKAGE_BASE, \ - PLAT_SP_PACKAGE_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -/* - * The rest of the memory reserved for BL32 is free for SPM to use it as memory - * pool to allocate memory regions requested in the resource description. - */ -#define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE) -#define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE) - -#if SPM_MM - -/* * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition * at the base of DRAM. @@ -121,23 +96,8 @@ /* Total number of memory regions with distinct properties */ #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 -#endif /* SPM_MM */ - /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ #define PLAT_SPM_COOKIE_0 ULL(0) #define PLAT_SPM_COOKIE_1 ULL(0) -/* - * Max number of elements supported by SPM in this platform. The defines below - * are used to allocate memory at compile time for different arrays in SPM. - */ -#define PLAT_SPM_MAX_PARTITIONS U(2) - -#define PLAT_SPM_MEM_REGIONS_MAX U(80) -#define PLAT_SPM_NOTIFICATIONS_MAX U(30) -#define PLAT_SPM_SERVICES_MAX U(30) - -#define PLAT_SPCI_HANDLES_MAX_NUM U(20) -#define PLAT_SPM_RESPONSES_MAX U(30) - #endif /* ARM_SPM_DEF_H */ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 07a46c518..02feec708 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -38,7 +38,7 @@ typedef struct arm_tzc_regions_info { * - Region 1 with secure access only; * - the remaining DRAM regions access from the given Non-Secure masters. ******************************************************************************/ -#if ENABLE_SPM && SPM_MM +#if SPM_MM #define ARM_TZC_REGIONS_DEF \ {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ TZC_REGION_S_RDWR, 0}, \ @@ -254,6 +254,11 @@ void plat_arm_program_trusted_mailbox(uintptr_t address); int plat_arm_bl1_fwu_needed(void); __dead2 void plat_arm_error_handler(int err); +/* + * Optional function in ARM standard platforms + */ +void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); + #if ARM_PLAT_MT unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); #endif diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index b82ff47e7..93f86162e 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -27,6 +27,7 @@ static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) int css_pwr_domain_on(u_register_t mpidr); void css_pwr_domain_on_finish(const psci_power_state_t *target_state); +void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state); void css_pwr_domain_off(const psci_power_state_t *target_state); void css_pwr_domain_suspend(const psci_power_state_t *target_state); void css_pwr_domain_suspend_finish( diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 3f9ab1b66..332cfca8d 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -22,7 +22,7 @@ struct image_desc; struct bl_load_info; struct bl_params; struct mmap_region; -struct secure_partition_boot_info; +struct spm_mm_boot_info; struct sp_res_desc; /******************************************************************************* @@ -104,7 +104,6 @@ void plat_panic_handler(void) __dead2; const char *plat_log_get_prefix(unsigned int log_level); void bl2_plat_preload_setup(void); int plat_try_next_boot_source(void); -uint64_t *plat_init_apiakey(void); /******************************************************************************* * Mandatory BL1 functions @@ -238,7 +237,7 @@ void plat_psci_stat_accounting_start(const psci_power_state_t *state_info); void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info); u_register_t plat_psci_stat_get_residency(unsigned int lvl, const psci_power_state_t *state_info, - int last_cpu_idx); + unsigned int last_cpu_idx); plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, const plat_local_state_t *states, unsigned int ncpu); @@ -268,7 +267,7 @@ int get_mbedtls_heap_helper(void **heap_addr, size_t *heap_size); * Secure Partitions functions ******************************************************************************/ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie); -const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( void *cookie); int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size); int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size, diff --git a/include/plat/marvell/a8k/common/armada_common.h b/include/plat/marvell/a8k/common/armada_common.h index dd2a24abc..709d009c2 100644 --- a/include/plat/marvell/a8k/common/armada_common.h +++ b/include/plat/marvell/a8k/common/armada_common.h @@ -124,5 +124,6 @@ int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base); int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win, uint32_t *size); +int system_power_off(void); #endif /* ARMADA_COMMON_H */ diff --git a/include/services/mm_svc.h b/include/services/mm_svc.h deleted file mode 100644 index c11132696..000000000 --- a/include/services/mm_svc.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MM_SVC_H -#define MM_SVC_H - -#if SPM_MM - -#include <lib/utils_def.h> - -#define MM_VERSION_MAJOR U(1) -#define MM_VERSION_MAJOR_SHIFT 16 -#define MM_VERSION_MAJOR_MASK U(0x7FFF) -#define MM_VERSION_MINOR U(0) -#define MM_VERSION_MINOR_SHIFT 0 -#define MM_VERSION_MINOR_MASK U(0xFFFF) -#define MM_VERSION_FORM(major, minor) ((major << MM_VERSION_MAJOR_SHIFT) | (minor)) -#define MM_VERSION_COMPILED MM_VERSION_FORM(MM_VERSION_MAJOR, MM_VERSION_MINOR) - -/* - * SMC IDs defined in [1] for accessing MM services from the Non-secure world. - * These FIDs occupy the range 0x40 - 0x5f. - * [1] DEN0060A_ARM_MM_Interface_Specification.pdf - */ -#define MM_VERSION_AARCH32 U(0x84000040) - -#define MM_COMMUNICATE_AARCH64 U(0xC4000041) -#define MM_COMMUNICATE_AARCH32 U(0x84000041) - -#endif /* SPM_MM */ - -#endif /* MM_SVC_H */ diff --git a/include/services/sp_res_desc.h b/include/services/sp_res_desc.h deleted file mode 100644 index b8be72eeb..000000000 --- a/include/services/sp_res_desc.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_RES_DESC_H -#define SPM_RES_DESC_H - -#include <stdint.h> - -#include <services/sp_res_desc_def.h> - -/******************************************************************************* - * Attribute Section - ******************************************************************************/ - -struct sp_rd_sect_attribute { - /* - * Version of the resource description. - */ - uint16_t version; - - /* - * Type of the Secure Partition: - * - bit[0]: SP Type - * - b'0: UP SP - * - b'1: MP SP - * If UP SP: - * - bit[1]: Type of UP SP - * - b'0: Migratable UP SP - * - b'1: Pinned UP SP - */ - uint16_t sp_type; - - /* - * If this is a Pinned UP SP, PE on which the Pinned UP SP will run. - */ - uint32_t pe_mpidr; - - /* - * Run-Time Exception Level: - * - 0: SEL0 SP - * - 1: SEL1 SP - */ - uint8_t runtime_el; - - /* - * Type of Execution: - * - 0: Init-time only - * - 1: Run-time Execution - */ - uint8_t exec_type; - - /* - * Expected behavior upon failure: - * - 0: Restartable - * - 1: One-Shot - */ - uint8_t panic_policy; - - /* - * Translation Granule to use in the SP translation regime: - * - 0: 4KB - * - 1: 16KB - * - 2: 64KB - */ - uint8_t xlat_granule; - - /* - * Size of the SP binary in bytes. - */ - uint32_t binary_size; - - /* - * - If SP is NOT PIE: - * - VA Address where the SP expects to be loaded. - * - If SP is PIE: - * - Ignored. - */ - uint64_t load_address; - - /* - * Initial execution address. This is a VA as the SP sees it. - */ - uint64_t entrypoint; -}; - -/******************************************************************************* - * Memory Region Section - ******************************************************************************/ - -struct sp_rd_sect_mem_region { - /* - * Name of a Memory region, including null terminator. Reserved names: - * - "Client Shared Memory Region": - * Memory region where memory shared by clients shall be mapped. - * - "Queue Memory Region": - * Memory region shared with SPM for SP queue management. - */ - char name[RD_MEM_REGION_NAME_LEN]; - - /* - * Memory Attributes: - * - bits[3:0]: Type of memory - * - 0: Device - * - 1: Code - * - 2: Data - * - 3: BSS - * - 4: Read-only Data - * - 5: SPM-to-SP Shared Memory Region - * - 6: Client Shared Memory Region - * - 7: Miscellaneous - * - If memory is { SPM-to-SP shared Memory, Client Shared Memory, - * Miscellaneous } - * - bits[4]: Position Independent - * - b'0: Position Dependent - * - b'1: Position Independent - */ - uint32_t attr; - - /* - * Base address of the memory region. - */ - uint64_t base; - - /* - * Size of the memory region. - */ - uint64_t size; - - /* - * Pointer to next memory region (or NULL if this is the last one). - */ - struct sp_rd_sect_mem_region *next; -}; - -/******************************************************************************* - * Notification Section - ******************************************************************************/ - -struct sp_rd_sect_notification { - /* - * Notification attributes: - * - bit[31]: Notification Type - * - b'0: Platform Notification - * - b'1: Interrupt - * If Notification Type == Platform Notification - * - bits[15:0]: Implementation-defined Notification ID - * If Notification Type == Interrupt - * - bits[15:0]: IRQ number - * - bits[23:16]: Interrupt Priority - * - bit[24]: Trigger Type - * - b'0: Edge Triggered - * - b'1: Level Triggered - * - bit[25]: Trigger Level - * - b'0: Falling or Low - * - b'1: Rising or High - */ - uint32_t attr; - - /* - * Processing Element. - * If Notification Type == Interrupt && IRQ number is { SGI, LPI } - * - PE ID to which IRQ will be forwarded - */ - uint32_t pe; - - /* - * Pointer to next notification (or NULL if this is the last one). - */ - struct sp_rd_sect_notification *next; -}; - -/******************************************************************************* - * Service Description Section - ******************************************************************************/ - -struct sp_rd_sect_service { - /* - * Service identifier. - */ - uint32_t uuid[4]; - - /* - * Accessibility Options: - * - bit[0]: Accessibility by secure-world clients - * - b'0: Not Accessible - * - b'1: Accessible - * - bit[1]: Accessible by EL3 - * - b'0: Not Accessible - * - b'1: Accessible - * - bit[2]: Accessible by normal-world clients - * - b'0: Not Accessible - * - b'1: Accessible - */ - uint8_t accessibility; - - /* - * Request type supported: - * - bit[0]: Blocking request - * - b'0: Not Enable - * - b'1: Enable - * - bit[1]: Non-blocking request - * - b'0: Not Enable - * - b'1: Enable - */ - uint8_t request_type; - - /* - * Maximum number of client connections that the service can support. - */ - uint16_t connection_quota; - - /* - * If the service requires secure world memory to be shared with its - * clients: - * - Maximum amount of secure world memory in bytes to reserve from the - * secure world memory pool for the service. - */ - uint32_t secure_mem_size; - - /* - * Interrupt number used to notify the SP for the service. - * - Should also be enabled in the Notification Section. - */ - uint32_t interrupt_num; - - /* - * Pointer to next service (or NULL if this is the last one). - */ - struct sp_rd_sect_service *next; -}; - -/******************************************************************************* - * Complete resource description struct - ******************************************************************************/ - -struct sp_res_desc { - - /* Attribute Section */ - struct sp_rd_sect_attribute attribute; - - /* System Resource Section */ - struct sp_rd_sect_mem_region *mem_region; - - struct sp_rd_sect_notification *notification; - - /* Service Section */ - struct sp_rd_sect_service *service; -}; - -#endif /* SPM_RES_DESC_H */ diff --git a/include/services/sp_res_desc_def.h b/include/services/sp_res_desc_def.h deleted file mode 100644 index 5a3c50d7f..000000000 --- a/include/services/sp_res_desc_def.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_RES_DESC_DEFS_H -#define SPM_RES_DESC_DEFS_H - -#include <lib/utils_def.h> - -/******************************************************************************* - * Attribute Section - ******************************************************************************/ - -#define RD_ATTR_TYPE_UP_MIGRATABLE U(0) -#define RD_ATTR_TYPE_UP_PINNED U(2) -#define RD_ATTR_TYPE_MP U(1) - -#define RD_ATTR_RUNTIME_SEL0 U(0) -#define RD_ATTR_RUNTIME_SEL1 U(1) - -#define RD_ATTR_INIT_ONLY U(0) -#define RD_ATTR_RUNTIME U(1) - -#define RD_ATTR_PANIC_RESTART U(0) -#define RD_ATTR_PANIC_ONESHOT U(1) - -#define RD_ATTR_XLAT_GRANULE_4KB U(0) -#define RD_ATTR_XLAT_GRANULE_16KB U(1) -#define RD_ATTR_XLAT_GRANULE_64KB U(2) - -/******************************************************************************* - * Memory Region Section - ******************************************************************************/ - -#define RD_MEM_REGION_NAME_LEN U(32) - -#define RD_MEM_DEVICE U(0) -#define RD_MEM_NORMAL_CODE U(1) -#define RD_MEM_NORMAL_DATA U(2) -#define RD_MEM_NORMAL_BSS U(3) -#define RD_MEM_NORMAL_RODATA U(4) -#define RD_MEM_NORMAL_SPM_SP_SHARED_MEM U(5) -#define RD_MEM_NORMAL_CLIENT_SHARED_MEM U(6) -#define RD_MEM_NORMAL_MISCELLANEOUS U(7) - -#define RD_MEM_MASK U(15) - -#define RD_MEM_IS_PIE (U(1) << 4) - -/******************************************************************************* - * Notification Section - ******************************************************************************/ - -#define RD_NOTIF_TYPE_PLATFORM (U(0) << 31) -#define RD_NOTIF_TYPE_INTERRUPT (U(1) << 31) - -#define RD_NOTIF_PLAT_ID_MASK U(0xFFFF) -#define RD_NOTIF_PLAT_ID_SHIFT U(0) - -#define RD_NOTIF_PLATFORM(id) \ - (RD_NOTIF_TYPE_PLATFORM \ - | (((id) & RD_NOTIF_PLAT_ID_MASK) << RD_NOTIF_PLAT_ID_SHIFT)) - -#define RD_NOTIF_IRQ_NUM_MASK U(0xFFFF) -#define RD_NOTIF_IRQ_NUM_SHIFT U(0) -#define RD_NOTIF_IRQ_PRIO_MASK U(0xFF) -#define RD_NOTIF_IRQ_PRIO_SHIFT U(16) - -#define RD_NOTIF_IRQ_EDGE_FALLING U(0) -#define RD_NOTIF_IRQ_EDGE_RISING U(2) -#define RD_NOTIF_IRQ_LEVEL_LOW U(1) -#define RD_NOTIF_IRQ_LEVEL_HIGH U(3) -#define RD_NOTIF_IRQ_TRIGGER_SHIFT U(24) - -#define RD_NOTIF_IRQ(num, prio, trig) \ - (RD_NOTIF_TYPE_IRQ \ - | (((num) & RD_NOTIF_IRQ_NUM_MASK) << RD_NOTIF_IRQ_NUM_SHIFT) \ - | (((prio) & RD_NOTIF_IRQ_PRIO_MASK) << RD_NOTIF_IRQ_PRIO_SHIFT) \ - | (((trig) << RD_NOTIF_IRQ_TRIGGER_SHIFT))) - -/******************************************************************************* - * Service Description Section - ******************************************************************************/ - -#define RD_SERV_ACCESS_SECURE (U(1) << 0) -#define RD_SERV_ACCESS_EL3 (U(1) << 1) -#define RD_SERV_ACCESS_NORMAL (U(1) << 2) - -#define RD_SERV_SUPPORT_BLOCKING (U(1) << 0) -#define RD_SERV_SUPPORT_NON_BLOCKING (U(1) << 0) - -#endif /* SPM_RES_DESC_DEFS_H */ diff --git a/include/services/spci_svc.h b/include/services/spci_svc.h deleted file mode 100644 index 1d02bfa9c..000000000 --- a/include/services/spci_svc.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPCI_SVC_H -#define SPCI_SVC_H - -#include <lib/smccc.h> -#include <lib/utils_def.h> - -/* SPCI_VERSION helpers */ - -#define SPCI_VERSION_MAJOR U(0) -#define SPCI_VERSION_MAJOR_SHIFT 16 -#define SPCI_VERSION_MAJOR_MASK U(0x7FFF) -#define SPCI_VERSION_MINOR U(1) -#define SPCI_VERSION_MINOR_SHIFT 0 -#define SPCI_VERSION_MINOR_MASK U(0xFFFF) -#define SPCI_VERSION_FORM(major, minor) ((((major) & SPCI_VERSION_MAJOR_MASK) \ - << SPCI_VERSION_MAJOR_SHIFT) | \ - ((minor) & SPCI_VERSION_MINOR_MASK)) -#define SPCI_VERSION_COMPILED SPCI_VERSION_FORM(SPCI_VERSION_MAJOR, \ - SPCI_VERSION_MINOR) - -/* Definitions to build the complete SMC ID */ - -#define SPCI_FID_MISC_FLAG (U(0) << 27) -#define SPCI_FID_MISC_SHIFT U(20) -#define SPCI_FID_MISC_MASK U(0x7F) - -#define SPCI_FID_TUN_FLAG (U(1) << 27) -#define SPCI_FID_TUN_SHIFT U(24) -#define SPCI_FID_TUN_MASK U(0x7) - -#define OEN_SPCI_START U(0x30) -#define OEN_SPCI_END U(0x3F) - -#define SPCI_SMC(spci_fid) ((OEN_SPCI_START << FUNCID_OEN_SHIFT) | \ - (U(1) << 31) | (spci_fid)) -#define SPCI_MISC_32(misc_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \ - SPCI_FID_MISC_FLAG | \ - SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT)) -#define SPCI_MISC_64(misc_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \ - SPCI_FID_MISC_FLAG | \ - SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT)) -#define SPCI_TUN_32(tun_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \ - SPCI_FID_TUN_FLAG | \ - SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT)) -#define SPCI_TUN_64(tun_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \ - SPCI_FID_TUN_FLAG | \ - SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT)) - -/* SPCI miscellaneous functions */ - -#define SPCI_FID_VERSION U(0x0) -#define SPCI_FID_SERVICE_HANDLE_OPEN U(0x2) -#define SPCI_FID_SERVICE_HANDLE_CLOSE U(0x3) -#define SPCI_FID_SERVICE_MEM_REGISTER U(0x4) -#define SPCI_FID_SERVICE_MEM_UNREGISTER U(0x5) -#define SPCI_FID_SERVICE_MEM_PUBLISH U(0x6) -#define SPCI_FID_SERVICE_REQUEST_BLOCKING U(0x7) -#define SPCI_FID_SERVICE_REQUEST_START U(0x8) -#define SPCI_FID_SERVICE_GET_RESPONSE U(0x9) -#define SPCI_FID_SERVICE_RESET_CLIENT_STATE U(0xA) - -/* SPCI tunneling functions */ - -#define SPCI_FID_SERVICE_TUN_REQUEST_START U(0x0) -#define SPCI_FID_SERVICE_REQUEST_RESUME U(0x1) -#define SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING U(0x2) - -/* Complete SMC IDs and associated values */ - -#define SPCI_VERSION SPCI_MISC_32(SPCI_FID_VERSION) - -#define SPCI_SERVICE_HANDLE_OPEN SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_OPEN) -#define SPCI_SERVICE_HANDLE_OPEN_NOTIFY_BIT U(1) - -#define SPCI_SERVICE_HANDLE_CLOSE SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_CLOSE) - -#define SPCI_SERVICE_MEM_REGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_REGISTER) -#define SPCI_SERVICE_MEM_REGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_REGISTER) - -#define SPCI_SERVICE_MEM_UNREGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_UNREGISTER) -#define SPCI_SERVICE_MEM_UNREGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_UNREGISTER) - -#define SPCI_SERVICE_MEM_PUBLISH_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_PUBLISH) -#define SPCI_SERVICE_MEM_PUBLISH_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_PUBLISH) - -#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_BLOCKING) -#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_BLOCKING) - -#define SPCI_SERVICE_REQUEST_START_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_START) -#define SPCI_SERVICE_REQUEST_START_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_START) - -#define SPCI_SERVICE_GET_RESPONSE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_GET_RESPONSE) -#define SPCI_SERVICE_GET_RESPONSE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_GET_RESPONSE) - -#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_RESET_CLIENT_STATE) -#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_RESET_CLIENT_STATE) - -#define SPCI_SERVICE_TUN_REQUEST_START_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_START) -#define SPCI_SERVICE_TUN_REQUEST_START_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_START) - -#define SPCI_SERVICE_REQUEST_RESUME_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_REQUEST_RESUME) -#define SPCI_SERVICE_REQUEST_RESUME_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_REQUEST_RESUME) - -#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING) -#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING) - -/* SPCI error codes. */ - -#define SPCI_SUCCESS 0 -#define SPCI_NOT_SUPPORTED -1 -#define SPCI_INVALID_PARAMETER -2 -#define SPCI_NO_MEMORY -3 -#define SPCI_BUSY -4 -#define SPCI_QUEUED -5 -#define SPCI_DENIED -6 -#define SPCI_NOT_PRESENT -7 - -#endif /* SPCI_SVC_H */ diff --git a/include/services/secure_partition.h b/include/services/spm_mm_partition.h index 0510f80ec..ad5ceefbb 100644 --- a/include/services/secure_partition.h +++ b/include/services/spm_mm_partition.h @@ -4,17 +4,15 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef SECURE_PARTITION_H -#define SECURE_PARTITION_H - -#if SPM_MM +#ifndef SPM_MM_PARTITION_H +#define SPM_MM_PARTITION_H #include <stdint.h> #include <lib/utils_def.h> /* - * Flags used by the secure_partition_mp_info structure to describe the + * Flags used by the spm_mm_mp_info structure to describe the * characteristics of a cpu. Only a single flag is defined at the moment to * indicate the primary cpu. */ @@ -24,13 +22,13 @@ * This structure is used to provide information required to initialise a S-EL0 * partition. */ -typedef struct secure_partition_mp_info { +typedef struct spm_mm_mp_info { uint64_t mpidr; uint32_t linear_id; uint32_t flags; -} secure_partition_mp_info_t; +} spm_mm_mp_info_t; -typedef struct secure_partition_boot_info { +typedef struct spm_mm_boot_info { param_header_t h; uint64_t sp_mem_base; uint64_t sp_mem_limit; @@ -46,9 +44,7 @@ typedef struct secure_partition_boot_info { uint64_t sp_shared_buf_size; uint32_t num_sp_mem_regions; uint32_t num_cpus; - secure_partition_mp_info_t *mp_info; -} secure_partition_boot_info_t; - -#endif /* SPM_MM */ + spm_mm_mp_info_t *mp_info; +} spm_mm_boot_info_t; -#endif /* SECURE_PARTITION_H */ +#endif /* SPM_MM_PARTITION_H */ diff --git a/include/services/spm_mm_svc.h b/include/services/spm_mm_svc.h new file mode 100644 index 000000000..3148beb80 --- /dev/null +++ b/include/services/spm_mm_svc.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_MM_SVC_H +#define SPM_MM_SVC_H + +#include <lib/utils_def.h> + +/* + * The MM_VERSION_XXX definitions are used when responding to the + * MM_VERSION_AARCH32 service request. The version returned is different between + * this request and the SPM_MM_VERSION_AARCH32 request - both have been retained + * for compatibility. + */ +#define MM_VERSION_MAJOR U(1) +#define MM_VERSION_MAJOR_SHIFT 16 +#define MM_VERSION_MAJOR_MASK U(0x7FFF) +#define MM_VERSION_MINOR U(0) +#define MM_VERSION_MINOR_SHIFT 0 +#define MM_VERSION_MINOR_MASK U(0xFFFF) +#define MM_VERSION_FORM(major, minor) ((major << MM_VERSION_MAJOR_SHIFT) | \ + (minor)) +#define MM_VERSION_COMPILED MM_VERSION_FORM(MM_VERSION_MAJOR, \ + MM_VERSION_MINOR) + +#define SPM_MM_VERSION_MAJOR U(0) +#define SPM_MM_VERSION_MAJOR_SHIFT 16 +#define SPM_MM_VERSION_MAJOR_MASK U(0x7FFF) +#define SPM_MM_VERSION_MINOR U(1) +#define SPM_MM_VERSION_MINOR_SHIFT 0 +#define SPM_MM_VERSION_MINOR_MASK U(0xFFFF) +#define SPM_MM_VERSION_FORM(major, minor) ((major << \ + SPM_MM_VERSION_MAJOR_SHIFT) | \ + (minor)) +#define SPM_MM_VERSION_COMPILED SPM_MM_VERSION_FORM(SPM_MM_VERSION_MAJOR, \ + SPM_MM_VERSION_MINOR) + +/* These macros are used to identify SPM-MM calls using the SMC function ID */ +#define SPM_MM_FID_MASK U(0xffff) +#define SPM_MM_FID_MIN_VALUE U(0x40) +#define SPM_MM_FID_MAX_VALUE U(0x7f) +#define is_spm_mm_fid(_fid) \ + ((((_fid) & SPM_MM_FID_MASK) >= SPM_MM_FID_MIN_VALUE) && \ + (((_fid) & SPM_MM_FID_MASK) <= SPM_MM_FID_MAX_VALUE)) + +/* + * SMC IDs defined in [1] for accessing MM services from the Non-secure world. + * These FIDs occupy the range 0x40 - 0x5f. + * [1] DEN0060A_ARM_MM_Interface_Specification.pdf + */ +#define MM_VERSION_AARCH32 U(0x84000040) +#define MM_COMMUNICATE_AARCH64 U(0xC4000041) +#define MM_COMMUNICATE_AARCH32 U(0x84000041) + +/* + * SMC IDs defined for accessing services implemented by the Secure Partition + * Manager from the Secure Partition(s). These services enable a partition to + * handle delegated events and request privileged operations from the manager. + * They occupy the range 0x60-0x7f. + */ +#define SPM_MM_VERSION_AARCH32 U(0x84000060) +#define MM_SP_EVENT_COMPLETE_AARCH64 U(0xC4000061) +#define MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 U(0xC4000064) +#define MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065) + +/* + * Macros used by MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64. + */ + +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS U(0) +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW U(1) +/* Value U(2) is reserved. */ +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO U(3) +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK U(3) +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT 0 + +#define MM_SP_MEMORY_ATTRIBUTES_EXEC (U(0) << 2) +#define MM_SP_MEMORY_ATTRIBUTES_NON_EXEC (U(1) << 2) + + +/* SPM error codes. */ +#define SPM_MM_SUCCESS 0 +#define SPM_MM_NOT_SUPPORTED -1 +#define SPM_MM_INVALID_PARAMETER -2 +#define SPM_MM_DENIED -3 +#define SPM_MM_NO_MEMORY -5 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +int32_t spm_mm_setup(void); + +uint64_t spm_mm_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +/* Helper to enter a secure partition */ +uint64_t spm_mm_sp_call(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3); + +#endif /* __ASSEMBLER__ */ + +#endif /* SPM_MM_SVC_H */ diff --git a/include/services/spm_svc.h b/include/services/spm_svc.h deleted file mode 100644 index a3723a0f5..000000000 --- a/include/services/spm_svc.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_SVC_H -#define SPM_SVC_H - -#if SPM_MM - -#include <lib/utils_def.h> - -#define SPM_VERSION_MAJOR U(0) -#define SPM_VERSION_MAJOR_SHIFT 16 -#define SPM_VERSION_MAJOR_MASK U(0x7FFF) -#define SPM_VERSION_MINOR U(1) -#define SPM_VERSION_MINOR_SHIFT 0 -#define SPM_VERSION_MINOR_MASK U(0xFFFF) -#define SPM_VERSION_FORM(major, minor) ((major << SPM_VERSION_MAJOR_SHIFT) | (minor)) -#define SPM_VERSION_COMPILED SPM_VERSION_FORM(SPM_VERSION_MAJOR, SPM_VERSION_MINOR) - -/* The macros below are used to identify SPM calls from the SMC function ID */ -#define SPM_FID_MASK U(0xffff) -#define SPM_FID_MIN_VALUE U(0x40) -#define SPM_FID_MAX_VALUE U(0x7f) -#define is_spm_fid(_fid) \ - ((((_fid) & SPM_FID_MASK) >= SPM_FID_MIN_VALUE) && \ - (((_fid) & SPM_FID_MASK) <= SPM_FID_MAX_VALUE)) - -/* - * SMC IDs defined for accessing services implemented by the Secure Partition - * Manager from the Secure Partition(s). These services enable a partition to - * handle delegated events and request privileged operations from the manager. - * They occupy the range 0x60-0x7f. - */ -#define SPM_VERSION_AARCH32 U(0x84000060) -#define SP_EVENT_COMPLETE_AARCH64 U(0xC4000061) -#define SP_MEMORY_ATTRIBUTES_GET_AARCH64 U(0xC4000064) -#define SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065) - -/* - * Macros used by SP_MEMORY_ATTRIBUTES_SET_AARCH64. - */ - -#define SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS U(0) -#define SP_MEMORY_ATTRIBUTES_ACCESS_RW U(1) -/* Value U(2) is reserved. */ -#define SP_MEMORY_ATTRIBUTES_ACCESS_RO U(3) -#define SP_MEMORY_ATTRIBUTES_ACCESS_MASK U(3) -#define SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT 0 - -#define SP_MEMORY_ATTRIBUTES_EXEC (U(0) << 2) -#define SP_MEMORY_ATTRIBUTES_NON_EXEC (U(1) << 2) - - -/* SPM error codes. */ -#define SPM_SUCCESS 0 -#define SPM_NOT_SUPPORTED -1 -#define SPM_INVALID_PARAMETER -2 -#define SPM_DENIED -3 -#define SPM_NO_MEMORY -5 - -#endif /* SPM_MM */ - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - -int32_t spm_setup(void); - -#if SPM_MM - -uint64_t spm_smc_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags); - -/* Helper to enter a Secure Partition */ -uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3); - -#endif /* SPM_MM */ - -#endif /* __ASSEMBLER__ */ - -#endif /* SPM_SVC_H */ diff --git a/include/services/sprt_svc.h b/include/services/sprt_svc.h deleted file mode 100644 index 2421ea251..000000000 --- a/include/services/sprt_svc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPRT_SVC_H -#define SPRT_SVC_H - -#include <lib/smccc.h> -#include <lib/utils_def.h> - -/* SPRT_VERSION helpers */ - -#define SPRT_VERSION_MAJOR U(0) -#define SPRT_VERSION_MAJOR_SHIFT 16 -#define SPRT_VERSION_MAJOR_MASK U(0x7FFF) -#define SPRT_VERSION_MINOR U(1) -#define SPRT_VERSION_MINOR_SHIFT 0 -#define SPRT_VERSION_MINOR_MASK U(0xFFFF) -#define SPRT_VERSION_FORM(major, minor) ((((major) & SPRT_VERSION_MAJOR_MASK) \ - << SPRT_VERSION_MAJOR_SHIFT) | \ - ((minor) & SPRT_VERSION_MINOR_MASK)) -#define SPRT_VERSION_COMPILED SPRT_VERSION_FORM(SPRT_VERSION_MAJOR, \ - SPRT_VERSION_MINOR) - -/* SPRT function IDs */ - -#define SPRT_FID_VERSION U(0x0) -#define SPRT_FID_PUT_RESPONSE U(0x1) -#define SPRT_FID_YIELD U(0x5) -#define SPRT_FID_PANIC U(0x7) -#define SPRT_FID_MEMORY_PERM_ATTR_GET U(0xB) -#define SPRT_FID_MEMORY_PERM_ATTR_SET U(0xC) - -#define SPRT_FID_MASK U(0xFF) - -/* Definitions to build the complete SMC ID */ - -#define OEN_SPRT_START U(0x20) -#define OEN_SPRT_END U(0x2F) - -#define SPRT_SMC_64(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \ - (U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \ - (SMC_64 << FUNCID_CC_SHIFT)) -#define SPRT_SMC_32(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \ - (U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \ - (SMC_32 << FUNCID_CC_SHIFT)) - -/* Complete SMC IDs */ - -#define SPRT_VERSION SPRT_SMC_32(SPRT_FID_VERSION) -#define SPRT_PUT_RESPONSE_AARCH64 SPRT_SMC_64(SPRT_FID_PUT_RESPONSE) -#define SPRT_YIELD_AARCH64 SPRT_SMC_64(SPRT_FID_YIELD) -#define SPRT_PANIC_AARCH64 SPRT_SMC_64(SPRT_FID_PANIC) -#define SPRT_MEMORY_PERM_ATTR_GET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_GET) -#define SPRT_MEMORY_PERM_ATTR_SET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_SET) - -/* Defines used by SPRT_MEMORY_PERM_ATTR_{GET,SET}_AARCH64 */ - -#define SPRT_MEMORY_PERM_ATTR_RO U(0) -#define SPRT_MEMORY_PERM_ATTR_RW U(1) -#define SPRT_MEMORY_PERM_ATTR_RO_EXEC U(2) -/* U(3) is reserved */ -#define SPRT_MEMORY_PERM_ATTR_MASK U(3) -#define SPRT_MEMORY_PERM_ATTR_SHIFT 3 - -/* SPRT error codes. */ - -#define SPRT_SUCCESS 0 -#define SPRT_NOT_SUPPORTED -1 -#define SPRT_INVALID_PARAMETER -2 - -#endif /* SPRT_SVC_H */ |