diff options
Diffstat (limited to 'fdts/a5ds.dts')
| -rw-r--r-- | fdts/a5ds.dts | 56 |
1 files changed, 50 insertions, 6 deletions
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index 8bc4adf8a..31d635ac8 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,13 +12,40 @@ interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_on = <0x84000003>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "psci"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <1>; + next-level-cache = <&L2>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <2>; + next-level-cache = <&L2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <3>; + next-level-cache = <&L2>; }; }; @@ -27,10 +54,27 @@ reg = <0x80000000 0x7F000000>; }; - refclk100mhz: refclk100mhz { + L2: cache-controller@1C010000 { + compatible = "arm,pl310-cache"; + reg = <0x1C010000 0x1000>; + interrupts = <0 84 4>; + cache-level = <2>; + cache-unified; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + refclk7500khz: refclk7500khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7500000>; + clock-output-names = "apb_pclk"; + }; + + refclk24mhz: refclk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <24000000>; clock-output-names = "apb_pclk"; }; @@ -45,7 +89,7 @@ rtc@1a220000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x1a220000 0x1000>; - clocks = <&refclk100mhz>; + clocks = <&refclk24mhz>; interrupts = <0 6 0xf04>; clock-names = "apb_pclk"; }; @@ -65,7 +109,7 @@ reg = <0x1a200000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 8 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; @@ -74,7 +118,7 @@ reg = <0x1a210000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 9 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; |