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-rw-r--r--drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c150
-rw-r--r--drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c20
-rw-r--r--drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h6
-rw-r--r--drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h4
-rw-r--r--drivers/renesas/rcar/ddr/ddr_regs.h257
5 files changed, 111 insertions, 326 deletions
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 1d6e83a2c..ac83c9a10 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -510,6 +510,14 @@ static void send_dbcmd(uint32_t cmd)
dsb_sev();
}
+static void dbwait_loop(uint32_t wait_loop)
+{
+ uint32_t i;
+
+ for (i = 0; i < wait_loop; i++)
+ wait_dbcmd();
+}
+
/* DDRPHY register access (raw) */
static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
{
@@ -866,6 +874,7 @@ struct _jedec_spec1 {
uint8_t WL;
uint8_t nwr;
uint8_t nrtp;
+ uint8_t odtlon;
uint8_t MR1;
uint8_t MR2;
};
@@ -877,21 +886,21 @@ struct _jedec_spec1 {
#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
/* 533.333Mbps */
- { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 },
+ { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 },
/* 1066.666Mbps */
- { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 },
+ { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 },
/* 1600.000Mbps */
- { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 },
+ { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 },
/* 2133.333Mbps */
- { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) },
+ { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) },
/* 2666.666Mbps */
- { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },
+ { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) },
/* 3200.000Mbps */
- { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },
+ { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) },
/* 3733.333Mbps */
- { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) },
+ { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) },
/* 4266.666Mbps */
- { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) }
+ { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) }
};
struct _jedec_spec2 {
@@ -921,7 +930,8 @@ struct _jedec_spec2 {
#define js2_tzqcalns 19
#define js2_tzqlat 20
#define js2_tiedly 21
-#define JS2_TBLCNT 22
+#define js2_tODTon_min 22
+#define JS2_TBLCNT 23
#define js2_trcpb (JS2_TBLCNT)
#define js2_trcab (JS2_TBLCNT + 1)
@@ -954,7 +964,8 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
/*tMRD*/ {14000, 10},
/*tZQCALns*/ {1000 * 10, 0},
/*tZQLAT*/ {30000, 10},
-/*tIEdly*/ {12500, 0}
+/*tIEdly*/ {12500, 0},
+/*tODTon_min*/ {1500, 0}
}, {
/*tSR */ {15000, 3},
/*tXP */ {7500, 3},
@@ -977,7 +988,8 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
/*tMRD*/ {14000, 10},
/*tZQCALns*/ {1000 * 10, 0},
/*tZQLAT*/ {30000, 10},
-/*tIEdly*/ {12500, 0}
+/*tIEdly*/ {12500, 0},
+/*tODTon_min*/ {1500, 0}
}
};
@@ -1452,7 +1464,7 @@ static void ddrtbl_load(void)
if ((prr_product == PRR_PRODUCT_M3N) ||
(prr_product == PRR_PRODUCT_V3H)) {
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_RDDATA_EN_OE_DLY, dataS);
+ _reg_PHY_RDDATA_EN_OE_DLY, dataS - 2);
}
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
@@ -1498,9 +1510,10 @@ static void ddrtbl_load(void)
/* DDRPHY INT START */
if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- /* non */
+ /* non */
} else {
regif_pll_wa();
+ dbwait_loop(5);
}
/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
@@ -2067,12 +2080,18 @@ static void dbsc_regset(void)
/* DBTR9.TRDPR : tRTP */
mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
- /* DBTR10.TWR : nwr */
+ /* DBTR10.TWR : nWR */
mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
- /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
+ /*
+ * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
+ * odtlon + tDQSCK - tODTon,min +
+ * PCB delay (out+in) + tPHY_ODToff
+ */
mmio_write_32(DBSC_DBTR(11),
- RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2);
+ RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon +
+ js2[js2_tdqsck] - js2[js2_tODTon_min] +
+ _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
@@ -2338,10 +2357,23 @@ static void dbsc_regset_post(void)
}
}
if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
+#if RCAR_DRAM_SPLIT == 2
+ if (board_cnf->phyvalid == 0x05) {
+ mmio_write_32(DBSC_DBTR(24),
+ (rdlat_max << 24) + (rdlat_min << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+ } else {
+ mmio_write_32(DBSC_DBTR(24),
+ ((rdlat_max * 2 - rdlat_min + 4) << 24) +
+ ((rdlat_min + 2) << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+ }
+#else /*RCAR_DRAM_SPLIT == 2 */
mmio_write_32(DBSC_DBTR(24),
((rdlat_max * 2 - rdlat_min + 4) << 24) +
((rdlat_min + 2) << 16) +
mmio_read_32(DBSC_DBTR(24)));
+#endif /*RCAR_DRAM_SPLIT == 2 */
} else {
mmio_write_32(DBSC_DBTR(24),
((rdlat_max + 2) << 24) +
@@ -2383,37 +2415,6 @@ static void dbsc_regset_post(void)
mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
-#ifdef DDR_BACKUPMODE
- if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
-#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
- DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
- send_dbcmd(0x08040001);
- wait_dbcmd();
- send_dbcmd(0x0A040001);
- wait_dbcmd();
- send_dbcmd(0x04040010);
- wait_dbcmd();
-
- if (prr_product == PRR_PRODUCT_H3) {
- send_dbcmd(0x08140001);
- wait_dbcmd();
- send_dbcmd(0x0A140001);
- wait_dbcmd();
- send_dbcmd(0x04140010);
- wait_dbcmd();
- }
-#else /* DDR_BACKUPMODE_HALF //for All channels */
- send_dbcmd(0x08840001);
- wait_dbcmd();
- send_dbcmd(0x0A840001);
- wait_dbcmd();
-
- send_dbcmd(0x04840010);
- wait_dbcmd();
-#endif /* DDR_BACKUPMODE_HALF */
- }
-#endif /* DDR_BACKUPMODE */
-
#if RCAR_REWT_TRAINING != 0
/* Periodic-WriteDQ Training seeting */
if (((prr_product == PRR_PRODUCT_H3) &&
@@ -2422,12 +2423,7 @@ static void dbsc_regset_post(void)
(prr_cut == PRR_PRODUCT_10))) {
/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
} else {
- /*
- * H3 Ver.2.0 or later/M3-W Ver.1.1 or
- * later/M3-N/V3H -> Periodic-WriteDQ Training seeting
- */
-
- /* Periodic WriteDQ Training seeting */
+ /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
@@ -2440,7 +2436,6 @@ static void dbsc_regset_post(void)
_reg_PI_WDQLVL_CS_MAP));
ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
- ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
@@ -2458,8 +2453,10 @@ static void dbsc_regset_post(void)
mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
}
#endif /* RCAR_REWT_TRAINING */
- /* periodic dram zqcal and phy ctrl update enable */
+ /* periodic dram zqcal enable */
mmio_write_32(DBSC_DBCALCNF, 0x01000010);
+
+ /* periodic phy ctrl update enable */
if (((prr_product == PRR_PRODUCT_H3) &&
(prr_cut <= PRR_PRODUCT_11)) ||
((prr_product == PRR_PRODUCT_M3) &&
@@ -2477,7 +2474,36 @@ static void dbsc_regset_post(void)
#endif /* RCAR_DRAM_SPLIT == 2 */
}
+#ifdef DDR_BACKUPMODE
+ /* SRX */
+ if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
+#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
+ NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
+ send_dbcmd(0x0A040001);
+ if (Prr_Product == PRR_PRODUCT_H3)
+ send_dbcmd(0x0A140001);
+#else /* DDR_BACKUPMODE_HALF */ /* for All channels */
+ send_dbcmd(0x0A840001);
+#endif /* DDR_BACKUPMODE_HALF */
+ }
+#endif /* DDR_BACKUPMODE */
+
+ /* set Auto Refresh */
mmio_write_32(DBSC_DBRFEN, 0x00000001);
+
+#if RCAR_REWT_TRAINING != 0
+ /* Periodic WriteDQ Traning */
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
+ /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
+ } else {
+ /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
+ ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
+ }
+#endif /* RCAR_REWT_TRAINING */
+
/* dram access enable */
mmio_write_32(DBSC_DBACEN, 0x00000001);
@@ -3026,6 +3052,9 @@ static uint32_t init_ddr(void)
return INITDRAM_ERR_O;
MSG_LF(__func__ ":5\n");
+ /* Dummy PDE */
+ send_dbcmd(0x08840000);
+
/* PDX */
send_dbcmd(0x08840001);
@@ -3477,10 +3506,13 @@ static uint32_t wdqdm_man(void)
{
uint32_t err, retry_cnt;
const uint32_t retry_max = 0x10;
- uint32_t ch, ddr_csn, mr14_bkup[4][4];
+ uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
+
+ datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19;
+ if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal)
+ datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
- (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
(prr_product == PRR_PRODUCT_M3N) ||
(prr_product == PRR_PRODUCT_V3H)) {
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index f8caade27..de126de86 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -1571,8 +1571,13 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
{
uint32_t md;
- md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
- md = (md | (md >> 1)) & 0x3;
+ if (prr_product == PRR_PRODUCT_V3H) {
+ md = (mmio_read_32(RST_MODEMR) >> 19) & 0x1;
+ md = (md | (md << 1)) & 0x3; /* 0 or 3 */
+ } else {
+ md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
+ md = (md | (md >> 1)) & 0x3;
+ }
switch (md) {
case 0x0:
*mbps = 3200;
@@ -1722,8 +1727,13 @@ static uint32_t _board_judge(void)
#endif
}
} else if (prr_product == PRR_PRODUCT_M3) {
- /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
- brd = 3;
+ if (prr_cut >= PRR_PRODUCT_30) {
+ /* RENESAS Starter Kit (M3-W Ver.3.0/SIP) */
+ brd = 18;
+ } else {
+ /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
+ brd = 3;
+ }
} else {
/* RENESAS Starter Kit(M3-N/SIP) board */
brd = 11;
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index 5047e5cc2..56363eb99 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define RCAR_DDR_VERSION "rev.0.37"
+#define RCAR_DDR_VERSION "rev.0.40"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x04
#define CS_CNT 0x02
@@ -22,7 +22,7 @@
/* for ddr deisity setting */
#define DBMEMCONF_REG(d3, row, bank, col, dw) \
- ((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
+ (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) \
(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
index 8d80842fd..fb3032dee 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
+++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -116,7 +116,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
/*0859*/ 0x00000200,
/*085a*/ 0x00000004,
/*085b*/ 0x4041a151,
- /*085c*/ 0x0141c0a0,
+ /*085c*/ 0x0141a0a0,
/*085d*/ 0x0000c0c0,
/*085e*/ 0x0e0c000e,
/*085f*/ 0x10001000,
diff --git a/drivers/renesas/rcar/ddr/ddr_regs.h b/drivers/renesas/rcar/ddr/ddr_regs.h
deleted file mode 100644
index ba26c69c8..000000000
--- a/drivers/renesas/rcar/ddr/ddr_regs.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_H_
-#define BOOT_INIT_DRAM_REGDEF_H_
-
-/* DBSC registers */
-#define DBSC_DBSYSCONF0 0xE6790000U
-#define DBSC_DBSYSCONF1 0xE6790004U
-#define DBSC_DBPHYCONF0 0xE6790010U
-#define DBSC_DBKIND 0xE6790020U
-#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
-#define DBSC_DBMEMCONF_0_0 0xE6790030U
-#define DBSC_DBMEMCONF_0_1 0xE6790034U
-#define DBSC_DBMEMCONF_0_2 0xE6790038U
-#define DBSC_DBMEMCONF_0_3 0xE679003CU
-#define DBSC_DBMEMCONF_1_2 0xE6790048U
-#define DBSC_DBMEMCONF_1_3 0xE679004CU
-#define DBSC_DBMEMCONF_1_0 0xE6790040U
-#define DBSC_DBMEMCONF_1_1 0xE6790044U
-#define DBSC_DBMEMCONF_2_0 0xE6790050U
-#define DBSC_DBMEMCONF_2_1 0xE6790054U
-#define DBSC_DBMEMCONF_2_2 0xE6790058U
-#define DBSC_DBMEMCONF_2_3 0xE679005CU
-#define DBSC_DBMEMCONF_3_0 0xE6790060U
-#define DBSC_DBMEMCONF_3_1 0xE6790064U
-#define DBSC_DBMEMCONF_3_2 0xE6790068U
-#define DBSC_DBMEMCONF_3_3 0xE679006CU
-#define DBSC_DBSYSCNT0 0xE6790100U
-#define DBSC_DBSVCR1 0xE6790104U
-#define DBSC_DBSTATE0 0xE6790108U
-#define DBSC_DBSTATE1 0xE679010CU
-#define DBSC_DBINTEN 0xE6790180U
-#define DBSC_DBINTSTAT0 0xE6790184U
-#define DBSC_DBACEN 0xE6790200U
-#define DBSC_DBRFEN 0xE6790204U
-#define DBSC_DBCMD 0xE6790208U
-#define DBSC_DBWAIT 0xE6790210U
-#define DBSC_DBSYSCTRL0 0xE6790280U
-#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
-#define DBSC_DBTR0 0xE6790300U
-#define DBSC_DBTR1 0xE6790304U
-#define DBSC_DBTR2 0xE6790308U
-#define DBSC_DBTR3 0xE679030CU
-#define DBSC_DBTR4 0xE6790310U
-#define DBSC_DBTR5 0xE6790314U
-#define DBSC_DBTR6 0xE6790318U
-#define DBSC_DBTR7 0xE679031CU
-#define DBSC_DBTR8 0xE6790320U
-#define DBSC_DBTR9 0xE6790324U
-#define DBSC_DBTR10 0xE6790328U
-#define DBSC_DBTR11 0xE679032CU
-#define DBSC_DBTR12 0xE6790330U
-#define DBSC_DBTR13 0xE6790334U
-#define DBSC_DBTR14 0xE6790338U
-#define DBSC_DBTR15 0xE679033CU
-#define DBSC_DBTR16 0xE6790340U
-#define DBSC_DBTR17 0xE6790344U
-#define DBSC_DBTR18 0xE6790348U
-#define DBSC_DBTR19 0xE679034CU
-#define DBSC_DBTR20 0xE6790350U
-#define DBSC_DBTR21 0xE6790354U
-#define DBSC_DBTR22 0xE6790358U
-#define DBSC_DBTR23 0xE679035CU
-#define DBSC_DBTR24 0xE6790360U
-#define DBSC_DBTR25 0xE6790364U
-#define DBSC_DBTR26 0xE6790368U
-#define DBSC_DBBL 0xE6790400U
-#define DBSC_DBRFCNF1 0xE6790414U
-#define DBSC_DBRFCNF2 0xE6790418U
-#define DBSC_DBTSPCNF 0xE6790420U
-#define DBSC_DBCALCNF 0xE6790424U
-#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
-#define DBSC_DBRNK2 0xE6790438U
-#define DBSC_DBRNK3 0xE679043CU
-#define DBSC_DBRNK4 0xE6790440U
-#define DBSC_DBRNK5 0xE6790444U
-#define DBSC_DBPDNCNF 0xE6790450U
-#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
-#define DBSC_DBODT0 0xE6790460U
-#define DBSC_DBODT1 0xE6790464U
-#define DBSC_DBODT2 0xE6790468U
-#define DBSC_DBODT3 0xE679046CU
-#define DBSC_DBODT4 0xE6790470U
-#define DBSC_DBODT5 0xE6790474U
-#define DBSC_DBODT6 0xE6790478U
-#define DBSC_DBODT7 0xE679047CU
-#define DBSC_DBADJ0 0xE6790500U
-#define DBSC_DBDBICNT 0xE6790518U
-#define DBSC_DBDFIPMSTRCNF 0xE6790520U
-#define DBSC_DBDFICUPDCNF 0xE679052CU
-#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
-#define DBSC_DBDFISTAT_0 0xE6790600U
-#define DBSC_DBDFISTAT_1 0xE6790640U
-#define DBSC_DBDFISTAT_2 0xE6790680U
-#define DBSC_DBDFISTAT_3 0xE67906C0U
-#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
-#define DBSC_DBDFICNT_0 0xE6790604U
-#define DBSC_DBDFICNT_1 0xE6790644U
-#define DBSC_DBDFICNT_2 0xE6790684U
-#define DBSC_DBDFICNT_3 0xE67906C4U
-#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
-#define DBSC_DBPDCNT0_0 0xE6790610U
-#define DBSC_DBPDCNT0_1 0xE6790650U
-#define DBSC_DBPDCNT0_2 0xE6790690U
-#define DBSC_DBPDCNT0_3 0xE67906D0U
-#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
-#define DBSC_DBPDCNT1_0 0xE6790614U
-#define DBSC_DBPDCNT1_1 0xE6790654U
-#define DBSC_DBPDCNT1_2 0xE6790694U
-#define DBSC_DBPDCNT1_3 0xE67906D4U
-#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
-#define DBSC_DBPDCNT2_0 0xE6790618U
-#define DBSC_DBPDCNT2_1 0xE6790658U
-#define DBSC_DBPDCNT2_2 0xE6790698U
-#define DBSC_DBPDCNT2_3 0xE67906D8U
-#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
-#define DBSC_DBPDCNT3_0 0xE679061CU
-#define DBSC_DBPDCNT3_1 0xE679065CU
-#define DBSC_DBPDCNT3_2 0xE679069CU
-#define DBSC_DBPDCNT3_3 0xE67906DCU
-#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
-#define DBSC_DBPDLK_0 0xE6790620U
-#define DBSC_DBPDLK_1 0xE6790660U
-#define DBSC_DBPDLK_2 0xE67906a0U
-#define DBSC_DBPDLK_3 0xE67906e0U
-#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
-#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
-#define DBSC_DBPDRGA_0 0xE6790624U
-#define DBSC_DBPDRGD_0 0xE6790628U
-#define DBSC_DBPDRGA_1 0xE6790664U
-#define DBSC_DBPDRGD_1 0xE6790668U
-#define DBSC_DBPDRGA_2 0xE67906A4U
-#define DBSC_DBPDRGD_2 0xE67906A8U
-#define DBSC_DBPDRGA_3 0xE67906E4U
-#define DBSC_DBPDRGD_3 0xE67906E8U
-#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
-#define DBSC_DBPDSTAT_0 0xE6790630U
-#define DBSC_DBPDSTAT_1 0xE6790670U
-#define DBSC_DBPDSTAT_2 0xE67906B0U
-#define DBSC_DBPDSTAT_3 0xE67906F0U
-#define DBSC_DBBUS0CNF0 0xE6790800U
-#define DBSC_DBBUS0CNF1 0xE6790804U
-#define DBSC_DBCAM0CNF1 0xE6790904U
-#define DBSC_DBCAM0CNF2 0xE6790908U
-#define DBSC_DBCAM0CNF3 0xE679090CU
-#define DBSC_DBBSWAP 0xE67909F0U
-#define DBSC_DBBCAMDIS 0xE67909FCU
-#define DBSC_DBSCHCNT0 0xE6791000U
-#define DBSC_DBSCHCNT1 0xE6791004U
-#define DBSC_DBSCHSZ0 0xE6791010U
-#define DBSC_DBSCHRW0 0xE6791020U
-#define DBSC_DBSCHRW1 0xE6791024U
-#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x))
-#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x))
-#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x))
-#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x))
-#define DBSC_DBSCHQOS00 0xE6791030U
-#define DBSC_DBSCHQOS01 0xE6791034U
-#define DBSC_DBSCHQOS02 0xE6791038U
-#define DBSC_DBSCHQOS03 0xE679103CU
-#define DBSC_DBSCHQOS10 0xE6791040U
-#define DBSC_DBSCHQOS11 0xE6791044U
-#define DBSC_DBSCHQOS12 0xE6791048U
-#define DBSC_DBSCHQOS13 0xE679104CU
-#define DBSC_DBSCHQOS20 0xE6791050U
-#define DBSC_DBSCHQOS21 0xE6791054U
-#define DBSC_DBSCHQOS22 0xE6791058U
-#define DBSC_DBSCHQOS23 0xE679105CU
-#define DBSC_DBSCHQOS30 0xE6791060U
-#define DBSC_DBSCHQOS31 0xE6791064U
-#define DBSC_DBSCHQOS32 0xE6791068U
-#define DBSC_DBSCHQOS33 0xE679106CU
-#define DBSC_DBSCHQOS40 0xE6791070U
-#define DBSC_DBSCHQOS41 0xE6791074U
-#define DBSC_DBSCHQOS42 0xE6791078U
-#define DBSC_DBSCHQOS43 0xE679107CU
-#define DBSC_DBSCHQOS50 0xE6791080U
-#define DBSC_DBSCHQOS51 0xE6791084U
-#define DBSC_DBSCHQOS52 0xE6791088U
-#define DBSC_DBSCHQOS53 0xE679108CU
-#define DBSC_DBSCHQOS60 0xE6791090U
-#define DBSC_DBSCHQOS61 0xE6791094U
-#define DBSC_DBSCHQOS62 0xE6791098U
-#define DBSC_DBSCHQOS63 0xE679109CU
-#define DBSC_DBSCHQOS70 0xE67910A0U
-#define DBSC_DBSCHQOS71 0xE67910A4U
-#define DBSC_DBSCHQOS72 0xE67910A8U
-#define DBSC_DBSCHQOS73 0xE67910ACU
-#define DBSC_DBSCHQOS80 0xE67910B0U
-#define DBSC_DBSCHQOS81 0xE67910B4U
-#define DBSC_DBSCHQOS82 0xE67910B8U
-#define DBSC_DBSCHQOS83 0xE67910BCU
-#define DBSC_DBSCHQOS90 0xE67910C0U
-#define DBSC_DBSCHQOS91 0xE67910C4U
-#define DBSC_DBSCHQOS92 0xE67910C8U
-#define DBSC_DBSCHQOS93 0xE67910CCU
-#define DBSC_DBSCHQOS100 0xE67910D0U
-#define DBSC_DBSCHQOS101 0xE67910D4U
-#define DBSC_DBSCHQOS102 0xE67910D8U
-#define DBSC_DBSCHQOS103 0xE67910DCU
-#define DBSC_DBSCHQOS110 0xE67910E0U
-#define DBSC_DBSCHQOS111 0xE67910E4U
-#define DBSC_DBSCHQOS112 0xE67910E8U
-#define DBSC_DBSCHQOS113 0xE67910ECU
-#define DBSC_DBSCHQOS120 0xE67910F0U
-#define DBSC_DBSCHQOS121 0xE67910F4U
-#define DBSC_DBSCHQOS122 0xE67910F8U
-#define DBSC_DBSCHQOS123 0xE67910FCU
-#define DBSC_DBSCHQOS130 0xE6791100U
-#define DBSC_DBSCHQOS131 0xE6791104U
-#define DBSC_DBSCHQOS132 0xE6791108U
-#define DBSC_DBSCHQOS133 0xE679110CU
-#define DBSC_DBSCHQOS140 0xE6791110U
-#define DBSC_DBSCHQOS141 0xE6791114U
-#define DBSC_DBSCHQOS142 0xE6791118U
-#define DBSC_DBSCHQOS143 0xE679111CU
-#define DBSC_DBSCHQOS150 0xE6791120U
-#define DBSC_DBSCHQOS151 0xE6791124U
-#define DBSC_DBSCHQOS152 0xE6791128U
-#define DBSC_DBSCHQOS153 0xE679112CU
-#define DBSC_DBSCTR0 0xE6791700U
-#define DBSC_DBSCTR1 0xE6791708U
-#define DBSC_DBSCHRW2 0xE679170CU
-#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
-#define DBSC_SCFCTST0 0xE6791700U
-#define DBSC_SCFCTST1 0xE6791708U
-#define DBSC_SCFCTST2 0xE679170CU
-#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
-#define DBSC_DBMRRDR_0 0xE6791800U
-#define DBSC_DBMRRDR_1 0xE6791804U
-#define DBSC_DBMRRDR_2 0xE6791808U
-#define DBSC_DBMRRDR_3 0xE679180CU
-#define DBSC_DBMRRDR_4 0xE6791810U
-#define DBSC_DBMRRDR_5 0xE6791814U
-#define DBSC_DBMRRDR_6 0xE6791818U
-#define DBSC_DBMRRDR_7 0xE679181CU
-#define DBSC_DBMEMSWAPCONF0 0xE6792000U
-
-/* CPG registers */
-#define CPG_BASE 0xE6150000U
-#define CPG_FRQCRB (CPG_BASE + 0x0004U)
-#define CPG_PLLECR (CPG_BASE + 0x00D0U)
-#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
-#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
-#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
-#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
-#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
-#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
-#define CPG_CPGWPR (CPG_BASE + 0x0900U)
-#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
-
-#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-16 11:04:19 +0000