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-rw-r--r--docs/design/auth-framework.rst2
-rw-r--r--docs/design/cpu-specific-build-macros.rst5
-rw-r--r--docs/design/firmware-design.rst2
-rw-r--r--docs/design/interrupt-framework-design.rst2
-rw-r--r--docs/design/psci-pd-tree.rst4
-rw-r--r--docs/design/reset-design.rst5
-rw-r--r--docs/design/trusted-board-boot.rst5
7 files changed, 0 insertions, 25 deletions
diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst
index dc45127f8..49f0def5e 100644
--- a/docs/design/auth-framework.rst
+++ b/docs/design/auth-framework.rst
@@ -1,8 +1,6 @@
Authentication Framework & Chain of Trust
=========================================
-.. contents::
-
The aim of this document is to describe the authentication framework
implemented in Trusted Firmware-A (TF-A). This framework fulfills the
following requirements:
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index d099ebe26..e49c73e7b 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -1,11 +1,6 @@
Arm CPU Specific Build Macros
=============================
-
-
-
-.. contents::
-
This document describes the various build options present in the CPU specific
operations framework to enable errata workarounds and to enable optimizations
for a specific CPU on a platform.
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index d6d7b1530..27d09480a 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1,8 +1,6 @@
Firmware Design
===============
-.. contents::
-
Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
Requirements (TBBR) Platform Design Document (PDD) [1]_ for Arm reference
platforms. The TBB sequence starts when the platform is powered on and runs up
diff --git a/docs/design/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst
index 2a641b128..6f692b2f1 100644
--- a/docs/design/interrupt-framework-design.rst
+++ b/docs/design/interrupt-framework-design.rst
@@ -1,8 +1,6 @@
Interrupt Management Framework
==============================
-.. contents::
-
This framework is responsible for managing interrupts routed to EL3. It also
allows EL3 software to configure the interrupt routing behavior. Its main
objective is to implement the following two requirements.
diff --git a/docs/design/psci-pd-tree.rst b/docs/design/psci-pd-tree.rst
index 23c985b6e..e52da77c6 100644
--- a/docs/design/psci-pd-tree.rst
+++ b/docs/design/psci-pd-tree.rst
@@ -1,10 +1,6 @@
PSCI Power Domain Tree Structure
================================
-.. contents::
-
---------------
-
Requirements
------------
diff --git a/docs/design/reset-design.rst b/docs/design/reset-design.rst
index 405b4920d..c38f62748 100644
--- a/docs/design/reset-design.rst
+++ b/docs/design/reset-design.rst
@@ -1,11 +1,6 @@
CPU Reset
=========
-
-
-
-.. contents::
-
This document describes the high-level design of the framework to handle CPU
resets in Trusted Firmware-A (TF-A). It also describes how the platform
integrator can tailor this code to the system configuration to some extent,
diff --git a/docs/design/trusted-board-boot.rst b/docs/design/trusted-board-boot.rst
index 76badb623..dbe2f2aa4 100644
--- a/docs/design/trusted-board-boot.rst
+++ b/docs/design/trusted-board-boot.rst
@@ -1,11 +1,6 @@
Trusted Board Boot
==================
-
-
-
-.. contents::
-
The Trusted Board Boot (TBB) feature prevents malicious firmware from running on
the platform by authenticating all firmware images up to and including the
normal world bootloader. It does this by establishing a Chain of Trust using