diff options
Diffstat (limited to 'docs/design/cpu-specific-build-macros.rst')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index d3fe89d62..f3096b418 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -29,6 +29,8 @@ vulnerability workarounds should be applied at runtime. platform contains at least 1 CPU that requires dynamic mitigation. Defaults to 0. +.. _arm_cpu_macros_errata_workarounds: + CPU Errata Workarounds ---------------------- @@ -47,9 +49,8 @@ errata notice document. The format of the define used to enable/disable the errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` is for example ``A57`` for the ``Cortex_A57`` CPU. -Refer to the section *CPU errata status reporting* in -`Firmware Design guide`_ for information on how to write errata workaround -functions. +Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to +write errata workaround functions. All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the @@ -226,6 +227,12 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +For Hercules, the following errata build flags are defined : + +- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to + Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of + the CPU. + For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 @@ -258,6 +265,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. + DSU Errata Workarounds ---------------------- @@ -314,6 +324,11 @@ architecture that can be enabled by the platform as desired. as recommended in section "4.7 Non-Temporal Loads/Stores" of the `Cortex-A57 Software Optimization Guide`_. +- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last + level cache(LLC) is present in the system, and that the DataSource field + on the master CHI interface indicates when data is returned from the LLC. + This is used to control how the LL_CACHE* PMU events count. + -------------- *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* @@ -323,6 +338,5 @@ architecture that can be enabled by the platform as desired. .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html -.. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf .. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html |