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| -rw-r--r-- | docs/about/acknowledgements.rst | 22 | ||||
| -rw-r--r-- | docs/about/contact.rst | 47 | ||||
| -rw-r--r-- | docs/about/features.rst | 127 | ||||
| -rw-r--r-- | docs/about/index.rst | 13 | ||||
| -rw-r--r-- | docs/about/maintainers.rst | 328 | ||||
| -rw-r--r-- | docs/about/release-information.rst | 68 |
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diff --git a/docs/about/acknowledgements.rst b/docs/about/acknowledgements.rst new file mode 100644 index 000000000..dfc66c8f7 --- /dev/null +++ b/docs/about/acknowledgements.rst @@ -0,0 +1,22 @@ +Contributor Acknowledgements +============================ + +.. note:: + This file is only relevant for legacy contributions, to acknowledge the + specific contributors referred to in "Arm Limited and Contributors" copyright + notices. As contributors are now encouraged to put their name or company name + directly into the copyright notices, this file is not relevant for new + contributions. See the :ref:`License` document for the correct template to + use for new contributions. + +- Linaro Limited +- Marvell International Ltd. +- NVIDIA Corporation +- NXP Semiconductors +- Socionext Inc. +- STMicroelectronics +- Xilinx, Inc. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/about/contact.rst b/docs/about/contact.rst new file mode 100644 index 000000000..9cb25ef47 --- /dev/null +++ b/docs/about/contact.rst @@ -0,0 +1,47 @@ +Support & Contact +----------------- + +We welcome any feedback on |TF-A| and there are several methods for providing +it or for obtaining support. + +.. warning:: + If you think you have found a security vulnerability, please report this using + the process defined in the :ref:`Security Handling` document. + +Mailing Lists +^^^^^^^^^^^^^ + +Public mailing lists for TF-A and the wider Trusted Firmware project are +hosted on TrustedFirmware.org. The mailing lists can be used for general +enquiries, enhancement requests and issue reports, or to follow and participate +in technical or organizational discussions around the project. These discussions +include design proposals, advance notice of changes and upcoming events. + +The relevant lists for the TF-A project are: + +- `TF-A development`_ +- `TF-A-Tests development`_ + +You can see a `summary of all the lists`_ on the TrustedFirmware.org website. + +Issue Tracker +^^^^^^^^^^^^^ + +Specific issues may be raised using the `issue tracker`_ on the +TrustedFirmware.org website. Using this tracker makes it easy for the +maintainers to prioritise and respond to your ticket. + +Arm Licensees +^^^^^^^^^^^^^ + +Arm licensees have an additional support conduit - they may contact Arm directly +via their partner managers. + +.. _`issue tracker`: https://developer.trustedfirmware.org +.. _`TF-A development`: https://lists.trustedfirmware.org/pipermail/tf-a/ +.. _`TF-A-Tests development`: https://lists.trustedfirmware.org/pipermail/tf-a-tests/ +.. _`summary of all the lists`: https://lists.trustedfirmware.org + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/about/features.rst b/docs/about/features.rst new file mode 100644 index 000000000..3441c5ebe --- /dev/null +++ b/docs/about/features.rst @@ -0,0 +1,127 @@ +Feature Overview +================ + +This page provides an overview of the current |TF-A| feature set. For a full +description of these features and their implementation details, please see +the documents that are part of the *Components* and *System Design* chapters. + +The :ref:`Change Log & Release Notes` provides details of changes made since the +last release. + +Current features +---------------- + +- Initialization of the secure world, for example exception vectors, control + registers and interrupts for the platform. + +- Library support for CPU specific reset and power down sequences. This + includes support for errata workarounds and the latest Arm DynamIQ CPUs. + +- Drivers to enable standard initialization of Arm System IP, for example + Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), + Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone + Controller (TZC). + +- A generic |SCMI| driver to interface with conforming power controllers, for + example the Arm System Control Processor (SCP). + +- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling + Convention`_ using an EL3 runtime services framework. + +- |PSCI| library support for CPU, cluster and system power management + use-cases. + This library is pre-integrated with the AArch64 EL3 Runtime Software, and + is also suitable for integration with other AArch32 EL3 Runtime Software, + for example an AArch32 Secure OS. + +- A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library + integration with AArch32 EL3 Runtime Software. + +- Secure Monitor library code such as world switching, EL1 context management + and interrupt routing. + When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the + AArch64 EL3 Runtime Software must be integrated with a Secure Payload + Dispatcher (SPD) component to customize the interaction with the SP. + +- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP + interaction with PSCI. + +- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_ + and `Trusty Secure OS`_. + +- A Trusted Board Boot implementation, conforming to all mandatory TBBR + requirements. This includes image authentication, Firmware Update (or + recovery mode), and packaging of the various firmware images into a + Firmware Image Package (FIP). + +- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of + its hardware Root of Trust and crypto acceleration services. + +- Reliability, Availability, and Serviceability (RAS) functionality, including + + - A Secure Partition Manager (SPM) to manage Secure Partitions in + Secure-EL0, which can be used to implement simple management and + security services. + + - An |SDEI| dispatcher to route interrupt-based |SDEI| events. + + - An Exception Handling Framework (EHF) that allows dispatching of EL3 + interrupts to their registered handlers, to facilitate firmware-first + error handling. + +- A dynamic configuration framework that enables each of the firmware images + to be configured at runtime if required by the platform. It also enables + loading of a hardware configuration (for example, a kernel device tree) + as part of the FIP, to be passed through the firmware stages. + +- Support for alternative boot flows, for example to support platforms where + the EL3 Runtime Software is loaded using other firmware or a separate + secure system processor, or where a non-TF-A ROM expects BL2 to be loaded + at EL3. + +- Support for the GCC, LLVM and Arm Compiler 6 toolchains. + +- Support for combining several libraries into a "romlib" image that may be + shared across images to reduce memory footprint. The romlib image is stored + in ROM but is accessed through a jump-table that may be stored + in read-write memory, allowing for the library code to be patched. + +- A prototype implementation of a Secure Partition Manager (SPM) that is based + on the SPCI Alpha 1 and SPRT draft specifications. + +- Support for ARMv8.3 pointer authentication in the normal and secure worlds. + The use of pointer authentication in the normal world is enabled whenever + architectural support is available, without the need for additional build + flags. Use of pointer authentication in the secure world remains an + experimental configuration at this time and requires the + ``BRANCH_PROTECTION`` option to be set to non-zero. + +- Position-Independent Executable (PIE) support. Initially for BL31 only, with + further support to be added in a future release. + +Still to come +------------- + +- Support for additional platforms. + +- Refinements to Position Independent Executable (PIE) support. + +- Continued support for the draft SPCI specification, to enable the use of + secure partition management in the secure world. + +- Documentation enhancements. + +- Ongoing support for new architectural features, CPUs and System IP. + +- Ongoing support for new Arm system architecture specifications. + +- Ongoing security hardening, optimization and quality improvements. + +.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf +.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os +.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary +.. _Trusty Secure OS: https://source.android.com/security/trusty + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/about/index.rst b/docs/about/index.rst new file mode 100644 index 000000000..3a102668c --- /dev/null +++ b/docs/about/index.rst @@ -0,0 +1,13 @@ +About +===== + +.. toctree:: + :maxdepth: 1 + :caption: Contents + :numbered: + + features + release-information + maintainers + contact + acknowledgements diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst new file mode 100644 index 000000000..d9d7f84fd --- /dev/null +++ b/docs/about/maintainers.rst @@ -0,0 +1,328 @@ +Maintainers +=========== + +Trusted Firmware-A (TF-A) is an Arm maintained project. All contributions are +ultimately merged by the maintainers listed below. Technical ownership of some +parts of the codebase is delegated to the sub-maintainers listed below. An +acknowledgement from these sub-maintainers may be required before the +maintainers merge a contribution. + +Main maintainers +---------------- +:M: Dan Handley <dan.handley@arm.com> +:G: `danh-arm`_ +:M: Soby Mathew <soby.mathew@arm.com> +:G: `soby-mathew`_ +:M: Sandrine Bailleux <sandrine.bailleux@arm.com> +:G: `sandrine-bailleux-arm`_ +:M: Alexei Fedorov <alexei.fedorov@arm.com> +:G: `AlexeiFedorov`_ +:M: György Szing <gyorgy.szing@arm.com> +:G: `gyuri-szing`_ +:M: Manish Pandey <manish.pandey2@arm.com> +:G: `manish-pandey-arm`_ +:M: Mark Dykes <mark.dykes@arm.com> +:G: `mardyk01`_ +:M: Olivier Deprez <olivier.deprez@arm.com> +:G: `odeprez`_ +:M: Bipin Ravi <bipin.ravi@arm.com> +:G: `bipinravi-arm`_ +:M: Joanna Farley <joanna.farley@arm.com> +:G: `joannafarley-arm`_ + +Allwinner ARMv8 platform port +----------------------------- +:M: Andre Przywara <andre.przywara@arm.com> +:G: `Andre-ARM`_ +:M: Samuel Holland <samuel@sholland.org> +:G: `smaeul`_ +:F: docs/plat/allwinner.rst +:F: plat/allwinner/ +:F: drivers/allwinner/ + +Amlogic Meson S905 (GXBB) platform port +--------------------------------------- +:M: Andre Przywara <andre.przywara@arm.com> +:G: `Andre-ARM`_ +:F: docs/plat/meson-gxbb.rst +:F: drivers/amlogic/ +:F: plat/amlogic/gxbb/ + +Amlogic Meson S905x (GXL) platform port +--------------------------------------- +:M: Remi Pommarel <repk@triplefau.lt> +:G: `remi-triplefault`_ +:F: docs/plat/meson-gxl.rst +:F: drivers/amlogic/gxl +:F: plat/amlogic/gxl/ + +Amlogic Meson S905X2 (G12A) platform port +----------------------------------------- +:M: Carlo Caione <ccaione@baylibre.com> +:G: `carlocaione`_ +:F: docs/plat/meson-g12a.rst +:F: drivers/amlogic/g12a +:F: plat/amlogic/g12a/ + +Armv7-A architecture port +------------------------- +:M: Etienne Carriere <etienne.carriere@linaro.org> +:G: `etienne-lms`_ + +Arm System Guidance for Infrastructure / Mobile FVP platforms +------------------------------------------------------------- +:M: Nariman Poushin <nariman.poushin@linaro.org> +:G: `npoushin`_ +:M: Thomas Abraham <thomas.abraham@arm.com> +:G: `thomas-arm`_ +:F: plat/arm/css/sgi/ +:F: plat/arm/css/sgm/ +:F: plat/arm/board/sgi575/ +:F: plat/arm/board/sgm775/ + +Console API framework +--------------------- +:M: Julius Werner <jwerner@chromium.org> +:G: `jwerner-chromium`_ +:F: drivers/console/ +:F: include/drivers/console.h +:F: plat/common/aarch64/crash_console_helpers.S + +coreboot support libraries +-------------------------- +:M: Julius Werner <jwerner@chromium.org> +:G: `jwerner-chromium`_ +:F: drivers/coreboot/ +:F: include/drivers/coreboot/ +:F: include/lib/coreboot.h +:F: lib/coreboot/ + +eMMC/UFS drivers +---------------- +:M: Haojian Zhuang <haojian.zhuang@linaro.org> +:G: `hzhuang1`_ +:F: drivers/partition/ +:F: drivers/synopsys/emmc/ +:F: drivers/synopsys/ufs/ +:F: drivers/ufs/ +:F: include/drivers/dw_ufs.h +:F: include/drivers/ufs.h +:F: include/drivers/synopsys/dw_mmc.h + +HiSilicon HiKey and HiKey960 platform ports +------------------------------------------- +:M: Haojian Zhuang <haojian.zhuang@linaro.org> +:G: `hzhuang1`_ +:F: docs/plat/hikey.rst +:F: docs/plat/hikey960.rst +:F: plat/hisilicon/hikey/ +:F: plat/hisilicon/hikey960/ + +HiSilicon Poplar platform port +------------------------------ +:M: Shawn Guo <shawn.guo@linaro.org> +:G: `shawnguo2`_ +:F: docs/plat/poplar.rst +:F: plat/hisilicon/poplar/ + +Intel SocFPGA platform ports +---------------------------- +:M: Tien Hock Loh <tien.hock.loh@intel.com> +:G: `thloh85-intel`_ +:M: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> +:G: mabdulha +:F: plat/intel/soc +:F: drivers/intel/soc/ + +MediaTek platform ports +----------------------- +:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com> +:G: `mtk09422`_ +:F: plat/mediatek/ + +Marvell platform ports and SoC drivers +-------------------------------------- +:M: Konstantin Porotchkin <kostap@marvell.com> +:G: `kostapr`_ +:F: docs/marvell/ +:F: plat/marvell/ +:F: drivers/marvell/ +:F: tools/marvell/ + +NVidia platform ports +--------------------- +:M: Varun Wadekar <vwadekar@nvidia.com> +:G: `vwadekar`_ +:F: docs/plat/nvidia-tegra.rst +:F: include/lib/cpus/aarch64/denver.h +:F: lib/cpus/aarch64/denver.S +:F: plat/nvidia/ + +NXP QorIQ Layerscape platform ports +----------------------------------- +:M: Jiafei Pan <jiafei.pan@nxp.com> +:G: `qoriq-open-source`_ +:F: docs/plat/ls1043a.rst +:F: plat/layerscape/ + +NXP i.MX 7 WaRP7 platform port and SoC drivers +---------------------------------------------- +:M: Bryan O'Donoghue <bryan.odonoghue@linaro.org> +:G: `bryanodonoghue`_ +:M: Jun Nie <jun.nie@linaro.org> +:G: `niej`_ +:F: docs/plat/warp7.rst +:F: plat/imx/common/ +:F: plat/imx/imx7/ +:F: drivers/imx/timer/ +:F: drivers/imx/uart/ +:F: drivers/imx/usdhc/ + +NXP i.MX 8 platform port +------------------------ +:M: Anson Huang <Anson.Huang@nxp.com> +:G: `Anson-Huang`_ +:F: docs/plat/imx8.rst +:F: plat/imx/ + +NXP i.MX8M platform port +------------------------ +:M: Jacky Bai <ping.bai@nxp.com> +:G: `JackyBai`_ +:F: doc/plat/imx8m.rst +:F: plat/imx/imx8m/ + +OP-TEE dispatcher +----------------- +:M: Jens Wiklander <jens.wiklander@linaro.org> +:G: `jenswi-linaro`_ +:F: docs/spd/optee-dispatcher.rst +:F: services/spd/opteed/ + +QEMU platform port +------------------ +:M: Jens Wiklander <jens.wiklander@linaro.org> +:G: `jenswi-linaro`_ +:F: docs/plat/qemu.rst +:F: plat/qemu/ + +Raspberry Pi 3 platform port +---------------------------- +:M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> +:G: `grandpaul`_ +:F: docs/plat/rpi3.rst +:F: plat/rpi3/ +:F: drivers/rpi3/ +:F: include/drivers/rpi3/ + +Renesas rcar-gen3 platform port +------------------------------- +:M: Jorge Ramirez-Ortiz <jramirez@baylibre.com> +:G: `ldts`_ +:M: Marek Vasut <marek.vasut@gmail.com> +:G: `marex`_ +:F: docs/plat/rcar-gen3.rst +:F: plat/renesas/rcar +:F: drivers/renesas/rcar +:F: tools/renesas/rcar_layout_create + +RockChip platform port +---------------------- +:M: Tony Xie <tony.xie@rock-chips.com> +:G: `TonyXie06`_ +:G: `rockchip-linux`_ +:M: Heiko Stuebner <heiko@sntech.de> +:G: `mmind`_ +:F: plat/rockchip/ + +STM32MP1 platform port +---------------------- +:M: Yann Gautier <yann.gautier@st.com> +:G: `Yann-lms`_ +:F: docs/plat/stm32mp1.rst +:F: drivers/st/ +:F: fdts/stm32\* +:F: include/drivers/st/ +:F: include/dt-bindings/\*/stm32\* +:F: plat/st/ +:F: tools/stm32image/ + +Synquacer platform port +----------------------- +:M: Sumit Garg <sumit.garg@linaro.org> +:G: `b49020`_ +:F: docs/plat/synquacer.rst +:F: plat/socionext/synquacer/ + +Texas Instruments platform port +------------------------------- +:M: Andrew F. Davis <afd@ti.com> +:G: `glneo`_ +:F: docs/plat/ti-k3.rst +:F: plat/ti/ + +TLK/Trusty secure payloads +-------------------------- +:M: Varun Wadekar <vwadekar@nvidia.com> +:G: `vwadekar`_ +:F: docs/spd/tlk-dispatcher.rst +:F: docs/spd/trusty-dispatcher.rst +:F: include/bl32/payloads/tlk.h +:F: services/spd/tlkd/ +:F: services/spd/trusty/ + +UniPhier platform port +---------------------- +:M: Masahiro Yamada <yamada.masahiro@socionext.com> +:G: `masahir0y`_ +:F: docs/plat/socionext-uniphier.rst +:F: plat/socionext/uniphier/ + +Xilinx platform port +-------------------- +:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> +:G: `sivadur`_ +:F: docs/plat/xilinx-zynqmp.rst +:F: plat/xilinx/ + +.. _AlexeiFedorov: https://github.com/AlexeiFedorov +.. _Andre-ARM: https://github.com/Andre-ARM +.. _Anson-Huang: https://github.com/Anson-Huang +.. _bryanodonoghue: https://github.com/bryanodonoghue +.. _b49020: https://github.com/b49020 +.. _carlocaione: https://github.com/carlocaione +.. _danh-arm: https://github.com/danh-arm +.. _etienne-lms: https://github.com/etienne-lms +.. _glneo: https://github.com/glneo +.. _grandpaul: https://github.com/grandpaul +.. _gyuri-szing: https://github.com/gyuri-szing +.. _hzhuang1: https://github.com/hzhuang1 +.. _JackyBai: https://github.com/JackyBai +.. _jenswi-linaro: https://github.com/jenswi-linaro +.. _jwerner-chromium: https://github.com/jwerner-chromium +.. _kostapr: https://github.com/kostapr +.. _ldts: https://github.com/ldts +.. _marex: https://github.com/marex +.. _masahir0y: https://github.com/masahir0y +.. _mmind: https://github.com/mmind +.. _mtk09422: https://github.com/mtk09422 +.. _niej: https://github.com/niej +.. _npoushin: https://github.com/npoushin +.. _qoriq-open-source: https://github.com/qoriq-open-source +.. _remi-triplefault: https://github.com/repk +.. _rockchip-linux: https://github.com/rockchip-linux +.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm +.. _shawnguo2: https://github.com/shawnguo2 +.. _sivadur: https://github.com/sivadur +.. _smaeul: https://github.com/smaeul +.. _soby-mathew: https://github.com/soby-mathew +.. _thloh85-intel: https://github.com/thloh85-intel +.. _thomas-arm: https://github.com/thomas-arm +.. _TonyXie06: https://github.com/TonyXie06 +.. _vwadekar: https://github.com/vwadekar +.. _Yann-lms: https://github.com/Yann-lms +.. _manish-pandey-arm: https://github.com/manish-pandey-arm +.. _mardyk01: https://github.com/mardyk01 +.. _odeprez: https://github.com/odeprez +.. _bipinravi-arm: https://github.com/bipinravi-arm +.. _joannafarley-arm: https://github.com/joannafarley-arm diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst new file mode 100644 index 000000000..c230e605d --- /dev/null +++ b/docs/about/release-information.rst @@ -0,0 +1,68 @@ +Release Processes +================= + +Project Release Cadence +----------------------- + +The project currently aims to do a release once every 6 months which will be +tagged on the master branch. There will be a code freeze (stop merging +non-essential changes) up to 4 weeks prior to the target release date. The release +candidates will start appearing after this and only bug fixes or updates +required for the release will be merged. The maintainers are free to use their +judgement on what changes are essential for the release. A release branch may be +created after code freeze if there are significant changes that need merging onto +the integration branch during the merge window. + +The release testing will be performed on release candidates and depending on +issues found, additional release candidates may be created to fix the issues. + +:: + + |<----------6 months---------->| + |<---4 weeks--->| |<---4 weeks--->| + +-----------------------------------------------------------> time + | | | | + code freeze ver w.x code freeze ver y.z + + +Upcoming Releases +~~~~~~~~~~~~~~~~~ + +These are the estimated dates for the upcoming release. These may change +depending on project requirement and partner feedback. + ++-----------------+---------------------------+------------------------------+ +| Release Version | Target Date | Expected Code Freeze | ++=================+===========================+==============================+ +| v2.0 | 1st week of Oct '18 | 1st week of Sep '18 | ++-----------------+---------------------------+------------------------------+ +| v2.1 | 5th week of Mar '19 | 1st week of Mar '19 | ++-----------------+---------------------------+------------------------------+ +| v2.2 | 4th week of Oct '19 | 1st week of Oct '19 | ++-----------------+---------------------------+------------------------------+ +| v2.3 | 4th week of Mar '20 | 1st week of Mar '20 | ++-----------------+---------------------------+------------------------------+ + +Removal of Deprecated Interfaces +-------------------------------- + +As mentioned in the :ref:`Platform Compatibility Policy`, this is a live +document cataloging all the deprecated interfaces in TF-A project and the +Release version after which it will be removed. + ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Interface | Deprecation | Removed | Comments | +| | Date | after | | +| | | Release | | ++================================+=============+=========+=========================================================+ +| ``AARCH32``/``AARCH64`` macros | Oct '19 | v2.3 | Deprecated in favor of ``__aarch64__`` | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| ``__ASSEMBLY__`` macro | Oct '19 | v2.3 | Deprecated in favor of ``__ASSEMBLER__`` | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Prototype SPCI-based SPM | Oct '19 | v2.2 | Based on outdated Alpha 1 spec. Will be replaced with | +| (services/std_svc/spm) | | | alternative methods of secure partitioning support. | ++--------------------------------+-------------+---------+---------------------------------------------------------+ + +-------------- + +*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* |