diff options
Diffstat (limited to 'bl32/sp_min')
| -rw-r--r-- | bl32/sp_min/sp_min.ld.S | 141 | ||||
| -rw-r--r-- | bl32/sp_min/sp_min.mk | 11 |
2 files changed, 29 insertions, 123 deletions
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index 6997a7fdb..f202c7ada 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -1,11 +1,10 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <platform_def.h> - +#include <common/bl_common.ld.h> #include <lib/xlat_tables/xlat_tables_defs.h> OUTPUT_FORMAT(elf32-littlearm) @@ -23,14 +22,14 @@ MEMORY { SECTIONS { . = BL32_BASE; - ASSERT(. == ALIGN(PAGE_SIZE), - "BL32_BASE address is not aligned on a page boundary.") + ASSERT(. == ALIGN(PAGE_SIZE), + "BL32_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA .text . : { __TEXT_START__ = .; *entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -47,30 +46,9 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) - - /* Ensure 4-byte alignment for descriptors and ensure inclusion */ - . = ALIGN(4); - __RT_SVC_DESCS_START__ = .; - KEEP(*(rt_svc_descs)) - __RT_SVC_DESCS_END__ = .; - -#if ENABLE_PMF - /* Ensure 4-byte alignment for descriptors and ensure inclusion */ - . = ALIGN(4); - __PMF_SVC_DESCS_START__ = .; - KEEP(*(pmf_svc_descs)) - __PMF_SVC_DESCS_END__ = .; -#endif /* ENABLE_PMF */ + *(SORT_BY_ALIGNMENT(.rodata*)) - /* - * Ensure 4-byte alignment for cpu_ops so that its fields are also - * aligned. Also ensure cpu_ops inclusion. - */ - . = ALIGN(4); - __CPU_OPS_START__ = .; - KEEP(*(cpu_ops)) - __CPU_OPS_END__ = .; + RODATA_COMMON /* Place pubsub sections for events */ . = ALIGN(8); @@ -83,23 +61,10 @@ SECTIONS ro . : { __RO_START__ = .; *entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) - /* Ensure 4-byte alignment for descriptors and ensure inclusion */ - . = ALIGN(4); - __RT_SVC_DESCS_START__ = .; - KEEP(*(rt_svc_descs)) - __RT_SVC_DESCS_END__ = .; - - /* - * Ensure 4-byte alignment for cpu_ops so that its fields are also - * aligned. Also ensure cpu_ops inclusion. - */ - . = ALIGN(4); - __CPU_OPS_START__ = .; - KEEP(*(cpu_ops)) - __CPU_OPS_END__ = .; + RODATA_COMMON /* Place pubsub sections for events */ . = ALIGN(8); @@ -111,7 +76,7 @@ SECTIONS /* * Memory page(s) mapped to this section will be marked as * read-only, executable. No RW data from the next section must - * creep in. Ensure the rest of the current memory block is unused. + * creep in. Ensure the rest of the current memory page is unused. */ . = ALIGN(PAGE_SIZE); __RO_END__ = .; @@ -126,85 +91,15 @@ SECTIONS */ __RW_START__ = . ; - .data . : { - __DATA_START__ = .; - *(.data*) - __DATA_END__ = .; - } >RAM + DATA_SECTION >RAM #ifdef BL32_PROGBITS_LIMIT ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") #endif - stacks (NOLOAD) : { - __STACKS_START__ = .; - *(tzfw_normal_stacks) - __STACKS_END__ = .; - } >RAM - - /* - * The .bss section gets initialised to 0 at runtime. - * Its base address should be 8-byte aligned for better performance of the - * zero-initialization code. - */ - .bss (NOLOAD) : ALIGN(8) { - __BSS_START__ = .; - *(.bss*) - *(COMMON) -#if !USE_COHERENT_MEM - /* - * Bakery locks are stored in normal .bss memory - * - * Each lock's data is spread across multiple cache lines, one per CPU, - * but multiple locks can share the same cache line. - * The compiler will allocate enough memory for one CPU's bakery locks, - * the remaining cache lines are allocated by the linker script - */ - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __BAKERY_LOCK_START__ = .; - __PERCPU_BAKERY_LOCK_START__ = .; - *(bakery_lock) - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __PERCPU_BAKERY_LOCK_END__ = .; - __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); - . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); - __BAKERY_LOCK_END__ = .; -#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE - ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, - "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); -#endif -#endif - -#if ENABLE_PMF - /* - * Time-stamps are stored in normal .bss memory - * - * The compiler will allocate enough memory for one CPU's time-stamps, - * the remaining memory for other CPUs is allocated by the - * linker script - */ - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __PMF_TIMESTAMP_START__ = .; - KEEP(*(pmf_timestamp_array)) - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __PMF_PERCPU_TIMESTAMP_END__ = .; - __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); - . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); - __PMF_TIMESTAMP_END__ = .; -#endif /* ENABLE_PMF */ - - __BSS_END__ = .; - } >RAM - - /* - * The xlat_table section is for full, aligned page tables (4K). - * Removing them from .bss avoids forcing 4K alignment on - * the .bss section. The tables are initialized to zero by the translation - * tables library. - */ - xlat_table (NOLOAD) : { - *(xlat_table) - } >RAM + STACK_SECTION >RAM + BSS_SECTION >RAM + XLAT_TABLE_SECTION >RAM __BSS_SIZE__ = SIZEOF(.bss); @@ -239,10 +134,12 @@ SECTIONS #endif /* - * Define a linker symbol to mark end of the RW memory area for this + * Define a linker symbol to mark the end of the RW memory area for this * image. */ __RW_END__ = .; - __BL32_END__ = .; + __BL32_END__ = .; + + ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") } diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk index 6233299d7..8b5eddd66 100644 --- a/bl32/sp_min/sp_min.mk +++ b/bl32/sp_min/sp_min.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,6 +19,10 @@ BL32_SOURCES += bl32/sp_min/sp_min_main.c \ services/std_svc/std_svc_setup.c \ ${PSCI_LIB_SOURCES} +ifeq (${DISABLE_MTPMU},1) +BL32_SOURCES += lib/extensions/mtpmu/aarch32/mtpmu.S +endif + ifeq (${ENABLE_PMF}, 1) BL32_SOURCES += lib/pmf/pmf_main.c endif @@ -33,6 +37,11 @@ BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_bpiall.S \ bl32/sp_min/wa_cve_2017_5715_icache_inv.S endif +ifeq (${TRNG_SUPPORT},1) +BL32_SOURCES += services/std_svc/trng/trng_main.c \ + services/std_svc/trng/trng_entropy_pool.c +endif + BL32_LINKERFILE := bl32/sp_min/sp_min.ld.S # Include the platform-specific SP_MIN Makefile |