diff options
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 54 | ||||
| -rw-r--r-- | bl31/aarch64/crash_reporting.S | 12 | ||||
| -rw-r--r-- | bl31/aarch64/ea_delegate.S | 86 | ||||
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 108 | ||||
| -rw-r--r-- | bl31/bl31.ld.S | 58 | ||||
| -rw-r--r-- | bl31/bl31.mk | 22 | ||||
| -rw-r--r-- | bl31/bl31_main.c | 17 | ||||
| -rw-r--r-- | bl31/interrupt_mgmt.c | 20 |
8 files changed, 239 insertions, 138 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index e7ad5a897..665a05e88 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -9,7 +9,7 @@ #include <arch.h> #include <common/bl_common.h> #include <el3_common_macros.S> -#include <lib/pmf/pmf_asm_macros.S> +#include <lib/pmf/aarch64/pmf_asm_macros.S> #include <lib/runtime_instr.h> #include <lib/xlat_tables/xlat_mmu_helpers.h> @@ -32,17 +32,6 @@ func bl31_entrypoint mov x22, x2 mov x23, x3 - /* -------------------------------------------------------------------- - * If PIE is enabled, fixup the Global descriptor Table and dynamic - * relocations - * -------------------------------------------------------------------- - */ -#if ENABLE_PIE - mov_imm x0, BL31_BASE - mov_imm x1, BL31_LIMIT - bl fixup_gdt_reloc -#endif /* ENABLE_PIE */ - #if !RESET_TO_BL31 /* --------------------------------------------------------------------- * For !RESET_TO_BL31 systems, only the primary CPU ever reaches @@ -59,7 +48,8 @@ func bl31_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=1 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE #else /* --------------------------------------------------------------------- @@ -74,7 +64,8 @@ func bl31_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE /* --------------------------------------------------------------------- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so @@ -98,26 +89,16 @@ func bl31_entrypoint mov x3, x23 bl bl31_setup - /* -------------------------------------------------------------------- - * Enable pointer authentication - * -------------------------------------------------------------------- - */ #if ENABLE_PAUTH - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* -------------------------------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 and enable pointer authentication * -------------------------------------------------------------------- */ - bic x0, x0, #SCTLR_BT_BIT -#endif /* ENABLE_BTI */ - msr sctlr_el3, x0 - isb + bl pauth_init_enable_el3 #endif /* ENABLE_PAUTH */ /* -------------------------------------------------------------------- - * Jump to main function. + * Jump to main function * -------------------------------------------------------------------- */ bl bl31_main @@ -184,7 +165,8 @@ func bl31_warm_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=0 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=0 /* * We're about to enable MMU and participate in PSCI state coordination. @@ -209,24 +191,12 @@ func bl31_warm_entrypoint #endif bl bl31_plat_enable_mmu - /* -------------------------------------------------------------------- - * Enable pointer authentication - * -------------------------------------------------------------------- - */ #if ENABLE_PAUTH - bl pauth_load_bl_apiakey - - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* -------------------------------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 and enable pointer authentication * -------------------------------------------------------------------- */ - bic x0, x0, #SCTLR_BT_BIT -#endif /* ENABLE_BTI */ - msr sctlr_el3, x0 - isb + bl pauth_init_enable_el3 #endif /* ENABLE_PAUTH */ bl psci_warmboot_entrypoint diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index 2c4102981..f2c12961d 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -62,14 +62,6 @@ intr_excpt_msg: .asciz "Unhandled Interrupt Exception in EL3.\nx30" /* - * Helper function to print newline to console. - */ -func print_newline - mov x0, '\n' - b plat_crash_console_putc -endfunc print_newline - - /* * Helper function to print from crash buf. * The print loop is controlled by the buf size and * ascii reg name list which is passed in x6. The @@ -101,7 +93,7 @@ test_size_list: bl print_alignment ldr x4, [x7], #REGSZ bl asm_print_hex - bl print_newline + bl asm_print_newline b test_size_list exit_size_print: mov x30, sp @@ -253,7 +245,7 @@ func do_crash_reporting /* report x30 first from the crash buf */ ldr x4, [x0, #REGSZ * 7] bl asm_print_hex - bl print_newline + bl asm_print_newline /* Load the crash buf address */ mrs x0, tpidr_el3 /* Now mov x7 into crash buf */ diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 40c3191ac..1d28d5e0f 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -11,7 +11,8 @@ #include <bl31/ea_handle.h> #include <context.h> #include <lib/extensions/ras_arch.h> - +#include <cpu_macros.S> +#include <context.h> .globl handle_lower_el_ea_esb .globl enter_lower_el_sync_ea @@ -35,9 +36,9 @@ endfunc handle_lower_el_ea_esb /* * This function forms the tail end of Synchronous Exception entry from lower - * EL, and expects to handle only Synchronous External Aborts from lower EL. If - * any other kind of exception is detected, then this function reports unhandled - * exception. + * EL, and expects to handle Synchronous External Aborts from lower EL and CPU + * Implementation Defined Exceptions. If any other kind of exception is detected, + * then this function reports unhandled exception. * * Since it's part of exception vector, this function doesn't expect any GP * registers to have been saved. It delegates the handling of the EA to platform @@ -58,31 +59,60 @@ func enter_lower_el_sync_ea b.eq 1f cmp x30, #EC_DABORT_LOWER_EL - b.ne 2f + b.eq 1f + + /* Save GP registers */ + stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + + /* Get the cpu_ops pointer */ + bl get_cpu_ops_ptr + + /* Get the cpu_ops exception handler */ + ldr x0, [x0, #CPU_E_HANDLER_FUNC] + + /* + * If the reserved function pointer is NULL, this CPU does not have an + * implementation defined exception handler function + */ + cbz x0, 2f + mrs x1, esr_el3 + ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH + blr x0 + b 2f 1: /* Test for EA bit in the instruction syndrome */ mrs x30, esr_el3 - tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f + tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f - /* Save GP registers */ - bl save_gp_registers + /* + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + */ + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* Setup exception class and syndrome arguments for platform handler */ mov x0, #ERROR_EA_SYNC mrs x1, esr_el3 - adr x30, el3_exit - b delegate_sync_ea + bl delegate_sync_ea + /* el3_exit assumes SP_EL0 on entry */ + msr spsel, #MODE_SP_EL0 + b el3_exit 2: + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + +3: /* Synchronous exceptions other than the above are assumed to be EA */ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] no_ret report_unhandled_exception @@ -103,22 +133,26 @@ func enter_lower_el_async_ea */ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - /* Save GP registers */ - bl save_gp_registers + /* + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + */ + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* Setup exception class and syndrome arguments for platform handler */ mov x0, #ERROR_EA_ASYNC mrs x1, esr_el3 - adr x30, el3_exit - b delegate_async_ea + bl delegate_async_ea + + /* el3_exit assumes SP_EL0 on entry */ + msr spsel, #MODE_SP_EL0 + b el3_exit endfunc enter_lower_el_async_ea @@ -233,7 +267,7 @@ func ea_proceed /* Switch to runtime stack */ ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] - msr spsel, #0 + msr spsel, #MODE_SP_EL0 mov sp, x5 mov x29, x30 @@ -255,7 +289,7 @@ func ea_proceed #endif /* Make SP point to context */ - msr spsel, #1 + msr spsel, #MODE_SP_ELX /* Restore EL3 state and ESR */ ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 6ffd99555..7f739a9aa 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -65,11 +65,17 @@ mrs x30, DISR_EL1 tbz x30, #DISR_A_BIT, 1f - /* Save GP registers and restore them afterwards */ - bl save_gp_registers + /* + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + */ + bl save_gp_pmcr_pauth_regs + bl handle_lower_el_ea_esb - bl restore_gp_registers + /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ + bl restore_gp_pmcr_pauth_regs 1: #else /* Unmask the SError interrupt */ @@ -121,14 +127,16 @@ */ .macro handle_interrupt_exception label - bl save_gp_registers + /* + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + */ + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* Save the EL3 system registers needed to return from this exception */ @@ -139,7 +147,7 @@ /* Switch to the runtime stack i.e. SP_EL0 */ ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] mov x20, sp - msr spsel, #0 + msr spsel, #MODE_SP_EL0 mov sp, x2 /* @@ -205,6 +213,19 @@ vector_base runtime_exceptions * --------------------------------------------------------------------- */ vector_entry sync_exception_sp_el0 +#ifdef MONITOR_TRAPS + stp x29, x30, [sp, #-16]! + + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + /* Check for BRK */ + cmp x30, #EC_BRK + b.eq brk_handler + + ldp x29, x30, [sp], #16 +#endif /* MONITOR_TRAPS */ + /* We don't expect any synchronous exceptions from EL3 */ b report_unhandled_exception end_vector_entry sync_exception_sp_el0 @@ -313,6 +334,14 @@ vector_entry serror_aarch32 b enter_lower_el_async_ea end_vector_entry serror_aarch32 +#ifdef MONITOR_TRAPS + .section .rodata.brk_string, "aS" +brk_location: + .asciz "Error at instruction 0x" +brk_message: + .asciz "Unexpected BRK instruction with value 0x" +#endif /* MONITOR_TRAPS */ + /* --------------------------------------------------------------------- * The following code handles secure monitor calls. * Depending upon the execution state from where the SMC has been @@ -332,15 +361,16 @@ smc_handler32: smc_handler64: /* NOTE: The code below must preserve x0-x4 */ - /* Save general purpose registers */ - bl save_gp_registers + /* + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + */ + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* @@ -360,7 +390,7 @@ smc_handler64: ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] /* Switch to SP_EL0 */ - msr spsel, #0 + msr spsel, #MODE_SP_EL0 /* * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world @@ -426,10 +456,48 @@ smc_unknown: smc_prohibited: ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mov x0, #SMC_UNK - eret + exception_return +#if DEBUG rt_svc_fw_critical_error: /* Switch to SP_ELx */ - msr spsel, #1 + msr spsel, #MODE_SP_ELX no_ret report_unhandled_exception +#endif endfunc smc_handler + + /* --------------------------------------------------------------------- + * The following code handles exceptions caused by BRK instructions. + * Following a BRK instruction, the only real valid cause of action is + * to print some information and panic, as the code that caused it is + * likely in an inconsistent internal state. + * + * This is initially intended to be used in conjunction with + * __builtin_trap. + * --------------------------------------------------------------------- + */ +#ifdef MONITOR_TRAPS +func brk_handler + /* Extract the ISS */ + mrs x10, esr_el3 + ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH + + /* Ensure the console is initialized */ + bl plat_crash_console_init + + adr x4, brk_location + bl asm_print_str + mrs x4, elr_el3 + bl asm_print_hex + bl asm_print_newline + + adr x4, brk_message + bl asm_print_str + mov x4, x10 + mov x5, #28 + bl asm_print_hex_bits + bl asm_print_newline + + no_ret plat_panic_handler +endfunc brk_handler +#endif /* MONITOR_TRAPS */ diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index c7d587cb0..c7185a893 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -15,6 +15,11 @@ ENTRY(bl31_entrypoint) MEMORY { RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE +#if SEPARATE_NOBITS_REGION + NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE +#else +#define NOBITS RAM +#endif } #ifdef PLAT_EXTRA_LD_SCRIPT @@ -33,7 +38,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -41,7 +46,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -87,8 +92,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -142,7 +147,7 @@ SECTIONS ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") -#if ENABLE_SPM +#if SPM_MM #ifndef SPM_SHIM_EXCEPTIONS_VMA #define SPM_SHIM_EXCEPTIONS_VMA RAM #endif @@ -179,7 +184,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM @@ -198,11 +203,28 @@ SECTIONS ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") #endif +#if SEPARATE_NOBITS_REGION + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL31_END__ = .; + + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") + + . = BL31_NOBITS_BASE; + ASSERT(. == ALIGN(PAGE_SIZE), + "BL31 NOBITS base address is not aligned on a page boundary.") + + __NOBITS_START__ = .; +#endif + stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) __STACKS_END__ = .; - } >RAM + } >NOBITS /* * The .bss section gets initialised to 0 at runtime. @@ -211,7 +233,7 @@ SECTIONS */ .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) #if !USE_COHERENT_MEM /* @@ -262,7 +284,7 @@ SECTIONS __PMF_TIMESTAMP_END__ = .; #endif /* ENABLE_PMF */ __BSS_END__ = .; - } >RAM + } >NOBITS /* * The xlat_table section is for full, aligned page tables (4K). @@ -272,7 +294,7 @@ SECTIONS */ xlat_table (NOLOAD) : { *(xlat_table) - } >RAM + } >NOBITS #if USE_COHERENT_MEM /* @@ -298,9 +320,18 @@ SECTIONS */ . = ALIGN(PAGE_SIZE); __COHERENT_RAM_END__ = .; - } >RAM + } >NOBITS #endif +#if SEPARATE_NOBITS_REGION + /* + * Define a linker symbol to mark end of the NOBITS memory area for this + * image. + */ + __NOBITS_END__ = .; + + ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.") +#else /* * Define a linker symbol to mark end of the RW memory area for this * image. @@ -308,5 +339,10 @@ SECTIONS __RW_END__ = .; __BL31_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") +#endif } diff --git a/bl31/bl31.mk b/bl31/bl31.mk index c9ba926c5..58909e84a 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -5,22 +5,17 @@ # ################################################################################ -# Include SPM Makefile +# Include Makefile for the SPM-MM implementation ################################################################################ -ifeq (${ENABLE_SPM},1) - ifeq (${SPM_MM},1) - ifeq (${EL3_EXCEPTION_HANDLING},0) - $(error EL3_EXCEPTION_HANDLING must be 1 for SPM support) - endif - $(info Including makefile of SPM based on MM) - include services/std_svc/spm_mm/spm.mk +ifeq (${SPM_MM},1) + ifeq (${EL3_EXCEPTION_HANDLING},0) + $(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support) else - $(info Including SPM makefile) - include services/std_svc/spm/spm.mk + $(info Including SPM Management Mode (MM) makefile) + include services/std_svc/spm_mm/spm_mm.mk endif endif - include lib/psci/psci_lib.mk BL31_SOURCES += bl31/bl31_main.c \ @@ -43,6 +38,11 @@ ifeq (${ENABLE_PMF}, 1) BL31_SOURCES += lib/pmf/pmf_main.c endif +include lib/debugfs/debugfs.mk +ifeq (${USE_DEBUGFS},1) + BL31_SOURCES += $(DEBUGFS_SRCS) +endif + ifeq (${EL3_EXCEPTION_HANDLING},1) BL31_SOURCES += bl31/ehf.c endif diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index 856ea9f62..92a2027dd 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -8,6 +8,7 @@ #include <string.h> #include <arch.h> +#include <arch_features.h> #include <arch_helpers.h> #include <bl31/bl31.h> #include <bl31/ehf.h> @@ -72,16 +73,16 @@ void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, /* Perform early platform-specific setup */ bl31_early_platform_setup2(arg0, arg1, arg2, arg3); - /* - * Update pointer authentication key before the MMU is enabled. It is - * saved in the rodata section, that can be writen before enabling the - * MMU. This function must be called after the console is initialized - * in the early platform setup. - */ - bl_handle_pauth(); - /* Perform late platform-specific setup */ bl31_plat_arch_setup(); + +#if CTX_INCLUDE_PAUTH_REGS + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* CTX_INCLUDE_PAUTH_REGS */ } /******************************************************************************* diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c index e6efad3e0..b8cc3de08 100644 --- a/bl31/interrupt_mgmt.c +++ b/bl31/interrupt_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,11 @@ * registered interrupt handlers for each interrupt type. * The field descriptions are: * + * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the + * value of the SCR_EL3.IRQ or FIQ bit for each security state. + * There are two instances of this field corresponding to the + * two security states. + * * 'flags' : Bit[0], Routing model for this interrupt type when execution is * not in EL3 in the secure state. '1' implies that this * interrupt will be routed to EL3. '0' implies that this @@ -28,16 +33,11 @@ * interrupt will be routed to the current exception level. * * All other bits are reserved and SBZ. - * - * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the - * value of the SCR_EL3.IRQ or FIQ bit for each security state. - * There are two instances of this field corresponding to the - * two security states. ******************************************************************************/ typedef struct intr_type_desc { interrupt_type_handler_t handler; + u_register_t scr_el3[2]; uint32_t flags; - uint32_t scr_el3[2]; } intr_type_desc_t; static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; @@ -78,9 +78,9 @@ static int32_t validate_routing_model(uint32_t type, uint32_t flags) * routing model (expressed through the IRQ and FIQ bits) for a security state * which was stored through a call to 'set_routing_model()' earlier. ******************************************************************************/ -uint32_t get_scr_el3_from_routing_model(uint32_t security_state) +u_register_t get_scr_el3_from_routing_model(uint32_t security_state) { - uint32_t scr_el3; + u_register_t scr_el3; assert(sec_state_is_valid(security_state)); scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; @@ -103,7 +103,7 @@ static void set_scr_el3_from_rm(uint32_t type, flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); bit_pos = plat_interrupt_type_to_line(type, security_state); - intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; + intr_type_descs[type].scr_el3[security_state] = (u_register_t)flag << bit_pos; /* * Update scr_el3 only if there is a context available. If not, it |