diff options
| -rw-r--r-- | plat/imx/common/plat_imx8_gic.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/plat/imx/common/plat_imx8_gic.c b/plat/imx/common/plat_imx8_gic.c index 27c525b72..3a7dcfec6 100644 --- a/plat/imx/common/plat_imx8_gic.c +++ b/plat/imx/common/plat_imx8_gic.c @@ -9,6 +9,8 @@ #include <common/bl_common.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv3.h> +#include <drivers/arm/arm_gicv3_common.h> +#include <lib/mmio.h> #include <lib/utils.h> #include <plat/common/platform.h> @@ -52,8 +54,27 @@ void plat_gic_driver_init(void) #endif } +static __inline void plat_gicr_exit_sleep(void) +{ + unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER); + + /* + * ProcessorSleep bit can ONLY be set to zero when + * Quiescent bit and Sleep bit are both zero, so + * need to make sure Quiescent bit and Sleep bit + * are zero before clearing ProcessorSleep bit. + */ + if (val & WAKER_QSC_BIT) { + mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT); + /* Wait till the WAKER_QSC_BIT changes to 0 */ + while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U) + ; + } +} + void plat_gic_init(void) { + plat_gicr_exit_sleep(); gicv3_distif_init(); gicv3_rdistif_init(plat_my_core_pos()); gicv3_cpuif_enable(plat_my_core_pos()); |