diff options
| -rw-r--r-- | include/drivers/arm/css/css_mhu_doorbell.h | 2 | ||||
| -rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/arm/board/n1sdp/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/arm/board/rde1edge/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/arm/board/rdn1edge/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/arm/board/sgi575/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/arm/css/sgm/include/sgm_base_platform_def.h | 1 | ||||
| -rw-r--r-- | plat/socionext/synquacer/include/platform_def.h | 2 |
8 files changed, 8 insertions, 2 deletions
diff --git a/include/drivers/arm/css/css_mhu_doorbell.h b/include/drivers/arm/css/css_mhu_doorbell.h index ecee56361..e6f7a1bd1 100644 --- a/include/drivers/arm/css/css_mhu_doorbell.h +++ b/include/drivers/arm/css/css_mhu_doorbell.h @@ -12,7 +12,7 @@ #include <lib/mmio.h> /* MHUv2 Base Address */ -#define MHUV2_BASE_ADDR PLAT_CSS_MHU_BASE +#define MHUV2_BASE_ADDR PLAT_MHUV2_BASE /* MHUv2 Control Registers Offsets */ #define MHU_V2_MSG_NO_CAP_OFFSET 0xF80 diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index ddbc9b7f5..e096e33e3 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -222,6 +222,7 @@ /* MHU related constants */ #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) +#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE /* * Base address of the first memory region used for communication between AP diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index 83b9f52d2..03bd3803a 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -61,6 +61,7 @@ #define PLAT_ARM_NSTIMER_FRAME_ID 0 #define PLAT_CSS_MHU_BASE 0x45000000 +#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE #define PLAT_MAX_PWR_LVL 1 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index 954a1cd48..3b3ade0cb 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -16,6 +16,7 @@ #define CSS_SGI_MAX_PE_PER_CPU 2 #define PLAT_CSS_MHU_BASE UL(0x45400000) +#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE /* Base address of DMC-620 instances */ #define RDE1EDGE_DMC620_BASE0 UL(0x4e000000) diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index 2ca0dd4ec..8480c08fe 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -16,6 +16,7 @@ #define CSS_SGI_MAX_PE_PER_CPU 1 #define PLAT_CSS_MHU_BASE UL(0x45400000) +#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE /* Base address of DMC-620 instances */ #define RDN1EDGE_DMC620_BASE0 UL(0x4e000000) diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index 6aea522f0..ec51c9e07 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -16,6 +16,7 @@ #define CSS_SGI_MAX_PE_PER_CPU 1 #define PLAT_CSS_MHU_BASE UL(0x45000000) +#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE /* Base address of DMC-620 instances */ #define SGI575_DMC620_BASE0 UL(0x4e000000) diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h index 4647e742f..85818446e 100644 --- a/plat/arm/css/sgm/include/sgm_base_platform_def.h +++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h @@ -86,6 +86,7 @@ /* MHU related constants */ #define PLAT_CSS_MHU_BASE 0x2b1f0000 +#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h index 263b215f2..7e54b39d8 100644 --- a/plat/socionext/synquacer/include/platform_def.h +++ b/plat/socionext/synquacer/include/platform_def.h @@ -80,7 +80,7 @@ #define DRAMINFO_BASE 0x2E00FFC0 #define PLAT_SQ_MHU_BASE 0x45000000 -#define PLAT_CSS_MHU_BASE PLAT_SQ_MHU_BASE +#define PLAT_MHUV2_BASE 0xFFFFFFFF /* MHUV2 is not supported */ #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 #define SCPI_CMD_GET_DRAMINFO 0x1 |