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-rw-r--r--plat/mediatek/common/drivers/uart/uart.c (renamed from plat/mediatek/mt8183/drivers/uart/uart.c)11
-rw-r--r--plat/mediatek/mt8183/drivers/uart/uart.h2
-rw-r--r--plat/mediatek/mt8183/platform.mk2
-rw-r--r--plat/mediatek/mt8192/drivers/uart/uart.h100
-rw-r--r--plat/mediatek/mt8192/include/platform_def.h1
-rw-r--r--plat/mediatek/mt8192/platform.mk4
6 files changed, 112 insertions, 8 deletions
diff --git a/plat/mediatek/mt8183/drivers/uart/uart.c b/plat/mediatek/common/drivers/uart/uart.c
index 3c6a98036..b940eb339 100644
--- a/plat/mediatek/mt8183/drivers/uart/uart.c
+++ b/plat/mediatek/common/drivers/uart/uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,7 @@
static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS];
-static const unsigned int uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
+static const uint32_t uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
UART0_BASE,
UART1_BASE
};
@@ -99,13 +99,14 @@ void mt_uart_save(void)
void mt_console_uart_cg(int on)
{
- if (on)
+ if (on == 1) {
mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT);
- else
+ } else {
mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT);
+ }
}
-int mt_console_uart_cg_status(void)
+uint32_t mt_console_uart_cg_status(void)
{
return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT;
}
diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h
index be04c3509..062ce3adc 100644
--- a/plat/mediatek/mt8183/drivers/uart/uart.h
+++ b/plat/mediatek/mt8183/drivers/uart/uart.h
@@ -95,6 +95,6 @@ struct mt_uart {
void mt_uart_save(void);
void mt_uart_restore(void);
void mt_console_uart_cg(int on);
-int mt_console_uart_cg_status(void);
+uint32_t mt_console_uart_cg_status(void);
#endif /* __UART_H__ */
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index f290a4e6d..07da1afac 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -45,6 +45,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/params_setup.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
@@ -58,7 +59,6 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \
${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
- ${MTK_PLAT_SOC}/drivers/uart/uart.c \
${MTK_PLAT_SOC}/drivers/timer/mt_timer.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/plat_pm.c \
diff --git a/plat/mediatek/mt8192/drivers/uart/uart.h b/plat/mediatek/mt8192/drivers/uart/uart.h
new file mode 100644
index 000000000..ac8b94dd1
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/uart/uart.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UART_H
+#define UART_H
+
+#include <platform_def.h>
+
+/* UART HW information */
+#define HW_SUPPORT_UART_PORTS 2
+#define DRV_SUPPORT_UART_PORTS 2
+
+/* console UART clock cg */
+#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80)
+#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84)
+#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90)
+#define UART0_CLOCK_GATE_BIT (1U<<22)
+#define UART1_CLOCK_GATE_BIT (1U<<23)
+
+/* UART registers */
+#define UART_RBR(_baseaddr) (_baseaddr + 0x0)
+#define UART_THR(_baseaddr) (_baseaddr + 0x0)
+#define UART_IER(_baseaddr) (_baseaddr + 0x4)
+#define UART_IIR(_baseaddr) (_baseaddr + 0x8)
+#define UART_FCR(_baseaddr) (_baseaddr + 0x8)
+#define UART_LCR(_baseaddr) (_baseaddr + 0xc)
+#define UART_MCR(_baseaddr) (_baseaddr + 0x10)
+#define UART_LSR(_baseaddr) (_baseaddr + 0x14)
+#define UART_MSR(_baseaddr) (_baseaddr + 0x18)
+#define UART_SCR(_baseaddr) (_baseaddr + 0x1c)
+#define UART_DLL(_baseaddr) (_baseaddr + 0x0)
+#define UART_DLH(_baseaddr) (_baseaddr + 0x4)
+#define UART_EFR(_baseaddr) (_baseaddr + 0x8)
+#define UART_XON1(_baseaddr) (_baseaddr + 0x10)
+#define UART_XON2(_baseaddr) (_baseaddr + 0x14)
+#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18)
+#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c)
+#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20)
+#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24)
+#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28)
+#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c)
+#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30)
+#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34)
+#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38)
+#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c)
+#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40)
+#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44)
+#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48)
+#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c)
+#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50)
+#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54)
+#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58)
+#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C)
+#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0)
+#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4)
+#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8)
+#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC)
+#define UART_LCR_DLAB 0x0080
+#define UART_LCR_MODE_B 0x00bf
+
+enum uart_port_ID {
+ UART_PORT0 = 0,
+ UART_PORT1
+};
+
+struct mt_uart_register {
+ uint32_t dll;
+ uint32_t dlh;
+ uint32_t ier;
+ uint32_t lcr;
+ uint32_t mcr;
+ uint32_t fcr;
+ uint32_t lsr;
+ uint32_t scr;
+ uint32_t efr;
+ uint32_t highspeed;
+ uint32_t sample_count;
+ uint32_t sample_point;
+ uint32_t fracdiv_l;
+ uint32_t fracdiv_m;
+ uint32_t escape_en;
+ uint32_t guard;
+ uint32_t rx_sel;
+};
+
+struct mt_uart {
+ unsigned long base;
+ struct mt_uart_register registers;
+};
+
+/* external API */
+void mt_uart_save(void);
+void mt_uart_restore(void);
+void mt_console_uart_cg(int on);
+uint32_t mt_console_uart_cg_status(void);
+
+#endif /* __UART_H__ */
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index a3ab1a0ca..51cf36136 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -26,6 +26,7 @@
#define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
+#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define GPIO_BASE (IO_PHYS + 0x00005000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 01851effc..3e23e05cd 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -14,7 +14,8 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \
- -I${MTK_PLAT_SOC}/drivers/timer/
+ -I${MTK_PLAT_SOC}/drivers/timer/ \
+ -I${MTK_PLAT_SOC}/drivers/uart/
GICV3_SUPPORT_GIC600 := 1
include drivers/arm/gic/v3/gicv3.mk
@@ -35,6 +36,7 @@ BL31_SOURCES += common/desc_image_load.c \
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_gicv3.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
+ ${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/params_setup.c \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 16:40:49 +0000