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-rw-r--r--bl1/bl1.ld.S13
-rw-r--r--bl2/bl2.ld.S13
-rw-r--r--bl2/bl2_el3.ld.S13
-rw-r--r--bl2u/bl2u.ld.S13
-rw-r--r--bl31/bl31.ld.S15
-rw-r--r--bl32/sp_min/sp_min.ld.S15
-rw-r--r--bl32/tsp/tsp.ld.S13
-rw-r--r--include/common/bl_common.ld.h18
-rw-r--r--plat/mediatek/mt6795/bl31.ld.S15
9 files changed, 27 insertions, 101 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index e706ce286..75355ebff 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -109,18 +109,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss : ALIGN(16) {
- __BSS_START__ = .;
- *(SORT_BY_ALIGNMENT(.bss*))
- *(COMMON)
- __BSS_END__ = .;
- } >RAM
-
+ BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index dc5165280..15df5dd03 100644
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -94,18 +94,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss : ALIGN(16) {
- __BSS_START__ = .;
- *(SORT_BY_ALIGNMENT(.bss*))
- *(COMMON)
- __BSS_END__ = .;
- } >RAM
-
+ BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM
diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S
index 3c2744369..d04f226e9 100644
--- a/bl2/bl2_el3.ld.S
+++ b/bl2/bl2_el3.ld.S
@@ -129,18 +129,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss : ALIGN(16) {
- __BSS_START__ = .;
- *(SORT_BY_ALIGNMENT(.bss*))
- *(COMMON)
- __BSS_END__ = .;
- } >RAM
-
+ BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM
diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S
index 37e658ad3..8c0bbbdd0 100644
--- a/bl2u/bl2u.ld.S
+++ b/bl2u/bl2u.ld.S
@@ -96,18 +96,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss : ALIGN(16) {
- __BSS_START__ = .;
- *(SORT_BY_ALIGNMENT(.bss*))
- *(COMMON)
- __BSS_END__ = .;
- } >RAM
-
+ BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index ac99a7de4..1cdf7c943 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -164,20 +164,7 @@ SECTIONS
__STACKS_END__ = .;
} >NOBITS
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss (NOLOAD) : ALIGN(16) {
- __BSS_START__ = .;
- *(SORT_BY_ALIGNMENT(.bss*))
- *(COMMON)
- BAKERY_LOCK_NORMAL
- PMF_TIMESTAMP
- __BSS_END__ = .;
- } >NOBITS
-
+ BSS_SECTION >NOBITS
XLAT_TABLE_SECTION >NOBITS
#if USE_COHERENT_MEM
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index f652f17e2..da005db64 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -107,20 +107,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 8-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss (NOLOAD) : ALIGN(8) {
- __BSS_START__ = .;
- *(.bss*)
- *(COMMON)
- BAKERY_LOCK_NORMAL
- PMF_TIMESTAMP
- __BSS_END__ = .;
- } >RAM
-
+ BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
__BSS_SIZE__ = SIZEOF(.bss);
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S
index b071e82fd..bf77c9234 100644
--- a/bl32/tsp/tsp.ld.S
+++ b/bl32/tsp/tsp.ld.S
@@ -97,18 +97,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss : ALIGN(16) {
- __BSS_START__ = .;
- *(SORT_BY_ALIGNMENT(.bss*))
- *(COMMON)
- __BSS_END__ = .;
- } >RAM
-
+ BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h
index 5c5fe5b15..3fc8e970d 100644
--- a/include/common/bl_common.ld.h
+++ b/include/common/bl_common.ld.h
@@ -11,8 +11,10 @@
#ifdef __aarch64__
#define STRUCT_ALIGN 8
+#define BSS_ALIGN 16
#else
#define STRUCT_ALIGN 4
+#define BSS_ALIGN 8
#endif
#define CPU_OPS \
@@ -127,6 +129,22 @@
. = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \
__PMF_TIMESTAMP_END__ = .;
+
+/*
+ * The .bss section gets initialised to 0 at runtime.
+ * Its base address has bigger alignment for better performance of the
+ * zero-initialization code.
+ */
+#define BSS_SECTION \
+ .bss (NOLOAD) : ALIGN(BSS_ALIGN) { \
+ __BSS_START__ = .; \
+ *(SORT_BY_ALIGNMENT(.bss*)) \
+ *(COMMON) \
+ BAKERY_LOCK_NORMAL \
+ PMF_TIMESTAMP \
+ __BSS_END__ = .; \
+ }
+
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
diff --git a/plat/mediatek/mt6795/bl31.ld.S b/plat/mediatek/mt6795/bl31.ld.S
index 02d79af38..b061b91ce 100644
--- a/plat/mediatek/mt6795/bl31.ld.S
+++ b/plat/mediatek/mt6795/bl31.ld.S
@@ -80,19 +80,8 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
- /*
- * The .bss section gets initialised to 0 at runtime.
- * Its base address should be 16-byte aligned for better performance of the
- * zero-initialization code.
- */
- .bss (NOLOAD) : ALIGN(16) {
- __BSS_START__ = .;
- *(.bss*)
- *(COMMON)
- BAKERY_LOCK_NORMAL
- __BSS_END__ = .;
- __RW_END__ = .;
- } >RAM
+ BSS_SECTION >RAM
+ __RW_END__ = __BSS_END__;
ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 02:50:16 +0000