diff options
| -rw-r--r-- | fdts/a5ds.dts | 19 | ||||
| -rw-r--r-- | plat/arm/board/a5ds/include/platform_def.h | 12 |
2 files changed, 19 insertions, 12 deletions
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index fc8783dd8..31d635ac8 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,10 +64,17 @@ arm,tag-latency = <1 1 1>; }; - refclk100mhz: refclk100mhz { + refclk7500khz: refclk7500khz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <7500000>; + clock-output-names = "apb_pclk"; + }; + + refclk24mhz: refclk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; clock-output-names = "apb_pclk"; }; @@ -82,7 +89,7 @@ rtc@1a220000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x1a220000 0x1000>; - clocks = <&refclk100mhz>; + clocks = <&refclk24mhz>; interrupts = <0 6 0xf04>; clock-names = "apb_pclk"; }; @@ -102,7 +109,7 @@ reg = <0x1a200000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 8 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; @@ -111,7 +118,7 @@ reg = <0x1a210000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 9 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index e9e4b9aef..649cb8b1e 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,7 +47,7 @@ #define A5_PERIPHERALS_BASE 0x1c000000 #define A5_PERIPHERALS_SIZE 0x10000 -#define ARM_CACHE_WRITEBACK_SHIFT 6 +#define ARM_CACHE_WRITEBACK_SHIFT 5 #define ARM_IRQ_SEC_PHY_TIMER 29 @@ -162,7 +162,7 @@ ARM_BL_REGIONS) /* Memory mapped Generic timer interfaces */ -#define A5DS_TIMER_BASE_FREQUENCY UL(24000000) +#define A5DS_TIMER_BASE_FREQUENCY UL(7500000) #define ARM_CONSOLE_BAUDRATE 115200 @@ -310,15 +310,15 @@ * PL011 related constants */ #define PLAT_ARM_BOOT_UART_BASE 0x1A200000 -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000) #define PLAT_ARM_RUN_UART_BASE 0x1A210000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000) #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ -#define A5DS_TIMER_BASE_FREQUENCY UL(24000000) +#define A5DS_TIMER_BASE_FREQUENCY UL(7500000) /* System timer related constants */ #define PLAT_ARM_NSTIMER_FRAME_ID 1 |