diff options
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 3 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 1 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a55.S | 34 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
4 files changed, 46 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 77e12d1e3..65e1c84af 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -105,6 +105,9 @@ For Cortex-A55, the following errata build flags are defined : - ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU. +- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + For Cortex-A57, the following errata build flags are defined : - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 13f209994..feac1d2f0 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -27,6 +27,7 @@ #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) /******************************************************************************* * CPU Identification register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index 20d5fe4cd..b0d5d4d52 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -82,6 +82,34 @@ func check_errata_778703 ret x16 endfunc check_errata_778703 + /* -------------------------------------------------- + * Errata Workaround for Cortex A55 Errata #798797. + * This applies only to revision r0p0 of Cortex A55. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a55_798797_wa + /* + * Compare x0 against revision r0p0 + */ + mov x17, x30 + bl check_errata_798797 + cbz x0, 1f + mrs x1, CORTEX_A55_CPUACTLR_EL1 + orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS + msr CORTEX_A55_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a55_798797_wa + +func check_errata_798797 + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_798797 + func cortex_a55_reset_func mov x19, x30 @@ -102,6 +130,11 @@ func cortex_a55_reset_func bl errata_a55_778703_wa #endif +#if ERRATA_A55_798797 + mov x0, x18 + bl errata_a55_798797_wa +#endif + ret x19 endfunc cortex_a55_reset_func @@ -137,6 +170,7 @@ func cortex_a55_errata_report report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 report_errata ERRATA_A55_768277, cortex_a55, 768277 report_errata ERRATA_A55_778703, cortex_a55, 778703 + report_errata ERRATA_A55_798797, cortex_a55, 798797 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ee316b7e2..dc1540d8a 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -87,6 +87,10 @@ ERRATA_A55_768277 ?=0 # only to revision r0p0 of the Cortex A55 cpu. ERRATA_A55_778703 ?=0 +# Flag to apply erratum 798797 workaround during reset. This erratum applies +# only to revision r0p0 of the Cortex A55 cpu. +ERRATA_A55_798797 ?=0 + # Flag to apply erratum 806969 workaround during reset. This erratum applies # only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_806969 ?=0 @@ -164,6 +168,10 @@ $(eval $(call add_define,ERRATA_A55_768277)) $(eval $(call assert_boolean,ERRATA_A55_778703)) $(eval $(call add_define,ERRATA_A55_778703)) +# Process ERRATA_A55_798797 flag +$(eval $(call assert_boolean,ERRATA_A55_798797)) +$(eval $(call add_define,ERRATA_A55_798797)) + # Process ERRATA_A57_806969 flag $(eval $(call assert_boolean,ERRATA_A57_806969)) $(eval $(call add_define,ERRATA_A57_806969)) |