diff options
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_bl31_setup.c | 6 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_pm.c | 5 | ||||
| -rw-r--r-- | plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c | 15 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/drivers/memctrl.h | 2 |
4 files changed, 2 insertions, 26 deletions
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 40713b2c7..e56909dcd 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -248,12 +248,6 @@ void bl31_platform_setup(void) tegra_memctrl_setup(); /* - * Set up the TZRAM memory aperture to allow only secure world - * access - */ - tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); - - /* * Late setup handler to allow platforms to performs additional * functionality. * This handler gets called with MMU enabled. diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 0430048e2..78e96cf3e 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -180,11 +180,6 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) tegra_memctrl_tzdram_setup(plat_params->tzdram_base, (uint32_t)plat_params->tzdram_size); - /* - * Set up the TZRAM memory aperture to allow only secure world - * access - */ - tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); } else { /* * Initialize the GIC cpu and distributor interfaces diff --git a/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c index c3f95db4d..b3dcd2a4b 100644 --- a/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,20 +93,6 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); } -/* - * Secure the BL31 TZRAM aperture. - * - * phys_base = physical base of TZRAM aperture - * size_in_bytes = size of aperture in bytes - */ -void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) -{ - /* - * The v1 hardware controller does not have any registers - * for setting up the on-chip TZRAM. - */ -} - static void tegra_clear_videomem(uintptr_t non_overlap_area_start, unsigned long long non_overlap_area_size) { diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index d5ef60d0c..cc8509526 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +11,6 @@ void tegra_memctrl_setup(void); void tegra_memctrl_restore_settings(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); -void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_disable_ahb_redirection(void); void tegra_memctrl_clear_pending_interrupts(void); |