diff options
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76ae.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_deimos.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_e1.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_zeus.S | 5 | ||||
| -rw-r--r-- | plat/arm/board/fvp/platform.mk | 25 |
7 files changed, 45 insertions, 10 deletions
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index b48283cbb..868667ebc 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -18,6 +18,11 @@ #error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex-A76 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + #define ESR_EL3_A64_SMC0 0x5e000000 #define ESR_EL3_A32_SMC0 0x4e000000 diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 46e9450f2..888f98b50 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -13,6 +13,11 @@ #error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S index e73e89f73..df4c12853 100644 --- a/lib/cpus/aarch64/cortex_deimos.S +++ b/lib/cpus/aarch64/cortex_deimos.S @@ -16,6 +16,11 @@ #error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex-Deimos supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index 71e7b5171..d840da84b 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -16,6 +16,11 @@ #error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + func neoverse_e1_cpu_pwr_dwn mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index a0babb0ef..dadaf98b4 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -15,6 +15,11 @@ #error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Errata * This applies to revision r0p0 and r1p0 of Neoverse N1. diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S index c5241afab..3d850137c 100644 --- a/lib/cpus/aarch64/neoverse_zeus.S +++ b/lib/cpus/aarch64/neoverse_zeus.S @@ -16,6 +16,11 @@ #error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index dbc5c21ba..3cbdfbc46 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -96,8 +96,8 @@ FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S ifeq (${ARCH}, aarch64) -# select a different set of CPU files, depending on whether we compile with -# hardware assisted coherency configurations or not +# select a different set of CPU files, depending on whether we compile for +# hardware assisted coherency cores or not ifeq (${HW_ASSISTED_COHERENCY}, 0) FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a53.S \ @@ -105,14 +105,19 @@ ifeq (${HW_ASSISTED_COHERENCY}, 0) lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a73.S else - FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ - lib/cpus/aarch64/cortex_a75.S \ - lib/cpus/aarch64/cortex_a76.S \ - lib/cpus/aarch64/cortex_a76ae.S \ - lib/cpus/aarch64/neoverse_n1.S \ - lib/cpus/aarch64/neoverse_e1.S \ - lib/cpus/aarch64/cortex_deimos.S \ - lib/cpus/aarch64/neoverse_zeus.S + # AArch64-only cores + ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) + FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ + lib/cpus/aarch64/cortex_a76ae.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/neoverse_e1.S \ + lib/cpus/aarch64/cortex_deimos.S \ + lib/cpus/aarch64/neoverse_zeus.S + # AArch64/AArch32 + else + FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a75.S + endif endif else |