diff options
| -rw-r--r-- | docs/user-guide.rst | 6 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 2 |
2 files changed, 5 insertions, 3 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 3f8170fd0..2b80531ce 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -457,8 +457,10 @@ Common build options .. __: `platform-interrupt-controller-API.rst` .. __: `interrupt-framework-design.rst` -- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts - will be always trapped in EL3 i.e. in BL31 at runtime. +- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError + Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to + ``0`` (default), these exceptions will be trapped in the current exception + level (or in EL1 if the current exception level is EL0). - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 2812bdaab..ee5fe4f9d 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -105,7 +105,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) if (EP_GET_ST(ep->h.attr)) scr_el3 |= SCR_ST_BIT; -#ifndef HANDLE_EA_EL3_FIRST +#if !HANDLE_EA_EL3_FIRST /* * SCR_EL3.EA: Do not route External Abort and SError Interrupt External * to EL3 when executing at a lower EL. When executing at EL3, External |