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-rw-r--r--docs/user-guide.rst7
-rw-r--r--include/plat/arm/css/common/css_def.h35
-rw-r--r--plat/arm/board/common/board_css_common.c9
-rw-r--r--plat/arm/board/fvp/platform.mk3
-rw-r--r--plat/arm/board/juno/include/platform_def.h10
-rw-r--r--plat/arm/board/juno/juno_bl2_setup.c7
-rw-r--r--plat/arm/common/arm_bl2_setup.c2
-rw-r--r--plat/arm/common/arm_common.mk8
-rw-r--r--plat/arm/css/common/aarch32/css_helpers.S21
-rw-r--r--plat/arm/css/common/aarch64/css_helpers.S20
-rw-r--r--plat/arm/css/common/css_bl2_setup.c13
-rw-r--r--plat/arm/css/common/css_common.mk51
-rw-r--r--plat/arm/css/common/sp_min/css_sp_min.mk2
-rw-r--r--plat/arm/css/drivers/scp/css_bom_bootloader.c10
-rw-r--r--plat/arm/css/drivers/scp/css_pm_scmi.c4
-rw-r--r--plat/arm/css/drivers/scp/css_scp.h23
-rw-r--r--plat/arm/css/drivers/scp/css_sds.c93
17 files changed, 248 insertions, 70 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 043af63ed..6031dd98d 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -669,9 +669,10 @@ ARM CSS platform specific build options
SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
during boot. Default is 1.
-- ``CSS_USE_SCMI_DRIVER``: Boolean flag which selects SCMI driver instead of
- SCPI driver for communicating with the SCP during power management operations.
- If this option is set to 1, then SCMI driver will be used. Default is 0.
+- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
+ instead of SCPI/BOM driver for communicating with the SCP during power
+ management operations and for SCP RAM Firmware transfer. If this option
+ is set to 1, then SCMI/SDS drivers will be used. Default is 0.
ARM FVP platform specific build options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 9d025f66b..ac0769c37 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -37,6 +37,9 @@
#define CSS_IRQ_TZ_WDOG 86
#define CSS_IRQ_SEC_SYS_TIMER 91
+/* MHU register offsets */
+#define MHU_CPU_INTR_S_SET_OFFSET 0x308
+
/*
* Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a
* GICv2 system or mode, the interrupts will be treated as Group 0 interrupts.
@@ -47,17 +50,24 @@
CSS_IRQ_TZ_WDOG, \
CSS_IRQ_SEC_SYS_TIMER
+#if CSS_USE_SCMI_SDS_DRIVER
+/* Memory region for shared data storage */
+#define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE
+#define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */
/*
- * The lower Non-secure MHU channel is being used for SCMI for ARM Trusted
- * Firmware.
- * TODO: Move SCMI to Secure channel once the migration to SCMI in SCP is
- * complete.
+ * The SCMI Channel is placed right after the SDS region
*/
-#define MHU_CPU_INTR_L_SET_OFFSET 0x108
-#define MHU_CPU_INTR_H_SET_OFFSET 0x128
-#define CSS_SCMI_PAYLOAD_BASE (NSRAM_BASE + 0x500)
-#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_L_SET_OFFSET
+#define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX)
+#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET
+
+/* Trusted mailbox base address common to all CSS */
+/* If SDS is present, then mailbox is at top of SRAM */
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8)
+/* Number of retries for SCP_RAM_READY flag */
+#define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */
+
+#else
/*
* SCP <=> AP boot configuration
*
@@ -69,6 +79,12 @@
*/
#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
+/* Trusted mailbox base address common to all CSS */
+/* If SDS is not present, then the mailbox is at the bottom of SRAM */
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
+
+#endif /* CSS_USE_SCMI_SDS_DRIVER */
+
#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
CSS_DEVICE_BASE, \
CSS_DEVICE_SIZE, \
@@ -152,9 +168,6 @@
/* TZC related constants */
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
-/* Trusted mailbox base address common to all CSS */
-#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
-
/*
* Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
* command
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c
index 68f70a781..159bf86f4 100644
--- a/plat/arm/board/common/board_css_common.c
+++ b/plat/arm/board/common/board_css_common.c
@@ -56,15 +56,6 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
CSS_MAP_DEVICE,
-#if CSS_USE_SCMI_DRIVER
- /*
- * The SCMI payload area is currently in the Non Secure SRAM. This is
- * a potential security risk but this will be resolved once SCP
- * completely replaces SCPI with SCMI as the only communication
- * protocol.
- */
- CSS_MAP_NSRAM,
-#endif
SOC_CSS_MAP_DEVICE,
{0}
};
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 0b6e1da54..6d8aa5fb7 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -117,7 +117,6 @@ BL1_SOURCES += drivers/io/io_semihosting.c \
BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/delay_timer/delay_timer.c \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/arm/board/fvp/fvp_bl2_setup.c \
@@ -128,8 +127,6 @@ BL2_SOURCES += drivers/io/io_semihosting.c \
ifeq (${FVP_USE_SP804_TIMER},1)
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
-else
-BL2_SOURCES += drivers/delay_timer/generic_delay_timer.c
endif
BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 873c56987..f1714e137 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -82,13 +82,8 @@
#endif
#ifdef IMAGE_BL31
-# if CSS_USE_SCMI_DRIVER
-# define PLAT_ARM_MMAP_ENTRIES 6
-# define MAX_XLAT_TABLES 3
-# else
# define PLAT_ARM_MMAP_ENTRIES 5
# define MAX_XLAT_TABLES 2
-# endif
#endif
#ifdef IMAGE_BL32
@@ -168,7 +163,9 @@
/*
* Base address of the first memory region used for communication between AP
* and SCP. Used by the BOM and SCPI protocols.
- *
+ */
+#if !CSS_USE_SCMI_SDS_DRIVER
+/*
* Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
* means the SCP/AP configuration data gets overwritten when the AP initiates
* communication with the SCP. The configuration data is expected to be a
@@ -178,6 +175,7 @@
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4
+#endif
/*
* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c
index abceb0f5e..2771e0f37 100644
--- a/plat/arm/board/juno/juno_bl2_setup.c
+++ b/plat/arm/board/juno/juno_bl2_setup.c
@@ -30,9 +30,12 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
return err;
}
+#if !CSS_USE_SCMI_SDS_DRIVER
/*
* We need to override some of the platform functions when booting SP_MIN
- * on Juno AArch32.
+ * on Juno AArch32. These needs to be done only for SCPI/BOM SCP systems as
+ * in case of SDS, the structures remain in memory and doesn't need to be
+ * overwritten.
*/
static unsigned int scp_boot_config;
@@ -53,4 +56,6 @@ void bl2_platform_setup(void)
mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config);
}
+#endif
+
#endif /* JUNO_AARCH32_EL3_RUNTIME */
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 9182bd128..cab6113e9 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -11,6 +11,7 @@
#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
+#include <generic_delay_timer.h>
#ifdef SPD_opteed
#include <optee_utils.h>
#endif
@@ -182,6 +183,7 @@ void arm_bl2_early_platform_setup(meminfo_t *mem_layout)
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
arm_bl2_early_platform_setup(mem_layout);
+ generic_delay_timer_init();
}
/*
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 20372c203..0e14806ab 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -139,7 +139,9 @@ ifdef EL3_PAYLOAD_BASE
BL1_SOURCES += plat/arm/common/arm_pm.c
endif
-BL2_SOURCES += drivers/io/io_fip.c \
+BL2_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
plat/arm/common/arm_bl2_setup.c \
@@ -159,7 +161,9 @@ BL2_SOURCES += lib/optee/optee_utils.c
endif
endif
-BL2U_SOURCES += plat/arm/common/arm_bl2u_setup.c
+BL2U_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ plat/arm/common/arm_bl2u_setup.c
BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
plat/arm/common/arm_pm.c \
diff --git a/plat/arm/css/common/aarch32/css_helpers.S b/plat/arm/css/common/aarch32/css_helpers.S
index f131e67a3..80aa24c62 100644
--- a/plat/arm/css/common/aarch32/css_helpers.S
+++ b/plat/arm/css/common/aarch32/css_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,6 +68,24 @@ endfunc css_calc_core_pos_swap_cluster
* cpu (applicable ony after a cold boot)
* -----------------------------------------------------
*/
+#if CSS_USE_SCMI_SDS_DRIVER
+func plat_is_my_cpu_primary
+ mov r10, lr
+ bl plat_my_core_pos
+ mov r4, r0
+ bl sds_get_primary_cpu_id
+ /* Check for error */
+ mov r1, #0xffffffff
+ cmp r0, r1
+ beq 1f
+ cmp r0, r4
+ moveq r0, #1
+ movne r0, #0
+ bx r10
+1:
+ no_ret plat_panic_handler
+endfunc plat_is_my_cpu_primary
+#else
func plat_is_my_cpu_primary
mov r10, lr
bl plat_my_core_pos
@@ -80,3 +98,4 @@ func plat_is_my_cpu_primary
movne r0, #0
bx r10
endfunc plat_is_my_cpu_primary
+#endif
diff --git a/plat/arm/css/common/aarch64/css_helpers.S b/plat/arm/css/common/aarch64/css_helpers.S
index 0cf8f86bb..59d920650 100644
--- a/plat/arm/css/common/aarch64/css_helpers.S
+++ b/plat/arm/css/common/aarch64/css_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,23 @@ endfunc css_calc_core_pos_swap_cluster
* cpu (applicable ony after a cold boot)
* -----------------------------------------------------
*/
+#if CSS_USE_SCMI_SDS_DRIVER
+func plat_is_my_cpu_primary
+ mov x9, x30
+ bl plat_my_core_pos
+ mov x4, x0
+ bl sds_get_primary_cpu_id
+ /* Check for error */
+ mov x1, #0xffffffff
+ cmp x0, x1
+ b.eq 1f
+ cmp x0, x4
+ cset w0, eq
+ ret x9
+1:
+ no_ret plat_panic_handler
+endfunc plat_is_my_cpu_primary
+#else
func plat_is_my_cpu_primary
mov x9, x30
bl plat_my_core_pos
@@ -99,3 +116,4 @@ func plat_is_my_cpu_primary
cset w0, eq
ret x9
endfunc plat_is_my_cpu_primary
+#endif
diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c
index c98b2fff3..9b4800e34 100644
--- a/plat/arm/css/common/css_bl2_setup.c
+++ b/plat/arm/css/common/css_bl2_setup.c
@@ -48,10 +48,14 @@ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
return ret;
}
-#ifdef EL3_PAYLOAD_BASE
+#if !CSS_USE_SCMI_SDS_DRIVER
+# ifdef EL3_PAYLOAD_BASE
+
/*
* We need to override some of the platform functions when booting an EL3
- * payload.
+ * payload. These needs to be done only for SCPI/BOM SCP systems as
+ * in case of SDS, the structures remain in memory and doesn't need to be
+ * overwritten.
*/
static unsigned int scp_boot_config;
@@ -82,4 +86,7 @@ void bl2_platform_setup(void)
zeromem((void *) ARM_SHARED_RAM_BASE, 128);
mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
}
-#endif /* EL3_PAYLOAD_BASE */
+
+# endif /* EL3_PAYLOAD_BASE */
+
+#endif /* CSS_USE_SCMI_SDS_DRIVER */
diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk
index 9381e4cd2..63e305916 100644
--- a/plat/arm/css/common/css_common.mk
+++ b/plat/arm/css/common/css_common.mk
@@ -9,7 +9,7 @@
CSS_LOAD_SCP_IMAGES ?= 1
# By default, SCMI driver is disabled for CSS platforms
-CSS_USE_SCMI_DRIVER ?= 0
+CSS_USE_SCMI_SDS_DRIVER ?= 0
PLAT_INCLUDES += -Iinclude/plat/arm/css/common \
-Iinclude/plat/arm/css/common/aarch64
@@ -19,18 +19,14 @@ PLAT_BL_COMMON_SOURCES += plat/arm/css/common/${ARCH}/css_helpers.S
BL1_SOURCES += plat/arm/css/common/css_bl1_setup.c
-BL2_SOURCES += plat/arm/css/common/css_bl2_setup.c \
- plat/arm/css/drivers/scpi/css_mhu.c \
- plat/arm/css/drivers/scpi/css_scpi.c
+BL2_SOURCES += plat/arm/css/common/css_bl2_setup.c
-BL2U_SOURCES += plat/arm/css/common/css_bl2u_setup.c \
- plat/arm/css/drivers/scpi/css_mhu.c \
- plat/arm/css/drivers/scpi/css_scpi.c
+BL2U_SOURCES += plat/arm/css/common/css_bl2u_setup.c
BL31_SOURCES += plat/arm/css/common/css_pm.c \
plat/arm/css/common/css_topology.c
-ifeq (${CSS_USE_SCMI_DRIVER},0)
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},0)
BL31_SOURCES += plat/arm/css/drivers/scp/css_pm_scpi.c \
plat/arm/css/drivers/scpi/css_mhu.c \
plat/arm/css/drivers/scpi/css_scpi.c
@@ -56,19 +52,34 @@ ifeq (${CSS_LOAD_SCP_IMAGES},1)
$(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp-fwu-cfg))
endif
- BL2U_SOURCES += plat/arm/css/drivers/scp/css_bom_bootloader.c
- BL2_SOURCES += plat/arm/css/drivers/scp/css_bom_bootloader.c
-endif
+ ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
+ BL2U_SOURCES += plat/arm/css/drivers/scp/css_sds.c \
+ plat/arm/css/drivers/sds/sds.c
-# Enable option to detect whether the SCP ROM firmware in use predates version
-# 1.7.0 and therefore, is incompatible.
-CSS_DETECT_PRE_1_7_0_SCP := 1
+ BL2_SOURCES += plat/arm/css/drivers/scp/css_sds.c \
+ plat/arm/css/drivers/sds/sds.c
+ else
+ BL2U_SOURCES += plat/arm/css/drivers/scp/css_bom_bootloader.c \
+ plat/arm/css/drivers/scpi/css_mhu.c \
+ plat/arm/css/drivers/scpi/css_scpi.c
-# Process CSS_DETECT_PRE_1_7_0_SCP flag
-$(eval $(call assert_boolean,CSS_DETECT_PRE_1_7_0_SCP))
-$(eval $(call add_define,CSS_DETECT_PRE_1_7_0_SCP))
+ BL2_SOURCES += plat/arm/css/drivers/scp/css_bom_bootloader.c \
+ plat/arm/css/drivers/scpi/css_mhu.c \
+ plat/arm/css/drivers/scpi/css_scpi.c
+ # Enable option to detect whether the SCP ROM firmware in use predates version
+ # 1.7.0 and therefore, is incompatible.
+ CSS_DETECT_PRE_1_7_0_SCP := 1
+
+ # Process CSS_DETECT_PRE_1_7_0_SCP flag
+ $(eval $(call assert_boolean,CSS_DETECT_PRE_1_7_0_SCP))
+ $(eval $(call add_define,CSS_DETECT_PRE_1_7_0_SCP))
+ endif
+endif
-# Process CSS_USE_SCMI_DRIVER flag
-$(eval $(call assert_boolean,CSS_USE_SCMI_DRIVER))
-$(eval $(call add_define,CSS_USE_SCMI_DRIVER))
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
+ PLAT_BL_COMMON_SOURCES += plat/arm/css/drivers/sds/${ARCH}/sds_helpers.S
+endif
+# Process CSS_USE_SCMI_SDS_DRIVER flag
+$(eval $(call assert_boolean,CSS_USE_SCMI_SDS_DRIVER))
+$(eval $(call add_define,CSS_USE_SCMI_SDS_DRIVER))
diff --git a/plat/arm/css/common/sp_min/css_sp_min.mk b/plat/arm/css/common/sp_min/css_sp_min.mk
index 7423d781b..28eb2dbda 100644
--- a/plat/arm/css/common/sp_min/css_sp_min.mk
+++ b/plat/arm/css/common/sp_min/css_sp_min.mk
@@ -8,7 +8,7 @@
BL32_SOURCES += plat/arm/css/common/css_pm.c \
plat/arm/css/common/css_topology.c
-ifeq (${CSS_USE_SCMI_DRIVER},0)
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},0)
BL32_SOURCES += plat/arm/css/drivers/scp/css_pm_scpi.c \
plat/arm/css/drivers/scpi/css_mhu.c \
plat/arm/css/drivers/scpi/css_scpi.c
diff --git a/plat/arm/css/drivers/scp/css_bom_bootloader.c b/plat/arm/css/drivers/scp/css_bom_bootloader.c
index 047e0696a..a92ce6b4f 100644
--- a/plat/arm/css/drivers/scp/css_bom_bootloader.c
+++ b/plat/arm/css/drivers/scp/css_bom_bootloader.c
@@ -6,12 +6,12 @@
#include <arch_helpers.h>
#include <assert.h>
-#include <cassert.h>
#include <css_def.h>
#include <debug.h>
#include <platform.h>
#include <stdint.h>
#include "../scpi/css_mhu.h"
+#include "../scpi/css_scpi.h"
/* ID of the MHU slot used for the BOM protocol */
#define BOM_MHU_SLOT_ID 0
@@ -183,3 +183,11 @@ int css_scp_boot_image_xfer(void *image, unsigned int image_size)
return 0;
}
+
+int css_scp_boot_ready(void)
+{
+ VERBOSE("Waiting for SCP to signal it is ready to go on\n");
+
+ /* Wait for SCP to signal it's ready */
+ return scpi_wait_ready();
+}
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index 9098d3fa9..c39bc4ba7 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -324,8 +324,8 @@ void __dead2 css_scp_sys_reboot(void)
scmi_channel_plat_info_t plat_css_scmi_plat_info = {
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
- .db_preserve_mask = 0xfffffffd,
- .db_modify_mask = 0x2,
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
};
void plat_arm_pwrc_setup(void)
diff --git a/plat/arm/css/drivers/scp/css_scp.h b/plat/arm/css/drivers/scp/css_scp.h
index 097a9f587..223e372a2 100644
--- a/plat/arm/css/drivers/scp/css_scp.h
+++ b/plat/arm/css/drivers/scp/css_scp.h
@@ -7,8 +7,9 @@
#ifndef __CSS_SCP_H__
#define __CSS_SCP_H__
+#include <cassert.h>
+#include <platform_def.h>
#include <types.h>
-#include "../scpi/css_scpi.h"
/* Forward declarations */
struct psci_power_state;
@@ -28,10 +29,20 @@ int css_scp_boot_image_xfer(void *image, unsigned int image_size);
* API to wait for SCP to signal till it's ready after booting the transferred
* image.
*/
-static inline int css_scp_boot_ready(void)
-{
- VERBOSE("Waiting for SCP to signal it is ready to go on\n");
- return scpi_wait_ready();
-}
+int css_scp_boot_ready(void);
+
+#if CSS_LOAD_SCP_IMAGES
+/*
+ * All CSS platforms load SCP_BL2/SCP_BL2U just below BL rw-data and above
+ * BL2/BL2U (this is where BL31 usually resides except when ARM_BL31_IN_DRAM is
+ * set. Ensure that SCP_BL2/SCP_BL2U do not overflow into BL1 rw-data nor
+ * BL2/BL2U.
+ */
+CASSERT(SCP_BL2_LIMIT <= BL1_RW_BASE, assert_scp_bl2_limit_overwrite_bl1);
+CASSERT(SCP_BL2U_LIMIT <= BL1_RW_BASE, assert_scp_bl2u_limit_overwrite_bl1);
+
+CASSERT(SCP_BL2_BASE >= BL2_LIMIT, assert_scp_bl2_overwrite_bl2);
+CASSERT(SCP_BL2U_BASE >= BL2U_LIMIT, assert_scp_bl2u_overwrite_bl2u);
+#endif
#endif /* __CSS_SCP_H__ */
diff --git a/plat/arm/css/drivers/scp/css_sds.c b/plat/arm/css/drivers/scp/css_sds.c
new file mode 100644
index 000000000..a7a51ba2d
--- /dev/null
+++ b/plat/arm/css/drivers/scp/css_sds.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <css_def.h>
+#include <debug.h>
+#include <delay_timer.h>
+#include <platform.h>
+#include <stdint.h>
+#include "../sds/sds.h"
+
+int css_scp_boot_image_xfer(void *image, unsigned int image_size)
+{
+ int ret;
+ unsigned int image_offset, image_flags;
+
+ ret = sds_init();
+ if (ret != SDS_OK) {
+ ERROR("SCP SDS initialization failed\n");
+ panic();
+ }
+
+ VERBOSE("Writing SCP image metadata\n");
+ image_offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE;
+ ret = sds_struct_write(SDS_SCP_IMG_STRUCT_ID, SDS_SCP_IMG_ADDR_OFFSET,
+ &image_offset, SDS_SCP_IMG_ADDR_SIZE,
+ SDS_ACCESS_MODE_NON_CACHED);
+ if (ret != SDS_OK)
+ goto sds_fail;
+
+ ret = sds_struct_write(SDS_SCP_IMG_STRUCT_ID, SDS_SCP_IMG_SIZE_OFFSET,
+ &image_size, SDS_SCP_IMG_SIZE_SIZE,
+ SDS_ACCESS_MODE_NON_CACHED);
+ if (ret != SDS_OK)
+ goto sds_fail;
+
+ VERBOSE("Marking SCP image metadata as valid\n");
+ image_flags = SDS_SCP_IMG_VALID_FLAG_BIT;
+ ret = sds_struct_write(SDS_SCP_IMG_STRUCT_ID, SDS_SCP_IMG_FLAG_OFFSET,
+ &image_flags, SDS_SCP_IMG_FLAG_SIZE,
+ SDS_ACCESS_MODE_NON_CACHED);
+ if (ret != SDS_OK)
+ goto sds_fail;
+
+ return 0;
+sds_fail:
+ ERROR("SCP SDS write to SCP IMG struct failed\n");
+ panic();
+}
+
+/*
+ * API to wait for SCP to signal till it's ready after booting the transferred
+ * image.
+ */
+int css_scp_boot_ready(void)
+{
+ uint32_t scp_feature_availability_flags;
+ int ret, retry = CSS_SCP_READY_10US_RETRIES;
+
+
+ VERBOSE("Waiting for SCP RAM to complete its initialization process\n");
+
+ /* Wait for the SCP RAM Firmware to complete its initialization process */
+ while (retry > 0) {
+ ret = sds_struct_read(SDS_FEATURE_AVAIL_STRUCT_ID, 0,
+ &scp_feature_availability_flags,
+ SDS_FEATURE_AVAIL_SIZE,
+ SDS_ACCESS_MODE_NON_CACHED);
+ if (ret == SDS_ERR_STRUCT_NOT_FINALIZED)
+ continue;
+
+ if (ret != SDS_OK) {
+ ERROR(" sds_struct_read failed\n");
+ panic();
+ }
+
+ if (scp_feature_availability_flags &
+ SDS_FEATURE_AVAIL_SCP_RAM_READY_BIT)
+ return 0;
+
+ udelay(10);
+ retry--;
+ }
+
+ ERROR("Timeout of %d ms expired waiting for SCP RAM Ready flag\n",
+ CSS_SCP_READY_10US_RETRIES/100);
+
+ plat_panic_handler();
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-06 01:59:25 +0000