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| author | Dehui Sun <dehui.sun@mediatek.com> | 2020-07-06 18:01:42 +0800 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2020-12-07 23:28:05 +0000 |
| commit | f3fbacaa9ae9e47dee75272f80408c6dec2e0e2c (patch) | |
| tree | 0eb3039446851aba0dcd98a1c9ed57d26c101ca7 /plat | |
| parent | 82c00c2ff5a6e0484f0c78c9677bf7e8dfaa287c (diff) | |
| download | platform_external_arm-trusted-firmware-f3fbacaa9ae9e47dee75272f80408c6dec2e0e2c.tar.gz platform_external_arm-trusted-firmware-f3fbacaa9ae9e47dee75272f80408c6dec2e0e2c.tar.bz2 platform_external_arm-trusted-firmware-f3fbacaa9ae9e47dee75272f80408c6dec2e0e2c.zip | |
mediatek: mt8192: enable NS access for systimer
Enable NS access for all systimers.
Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/mediatek/mt8192/bl31_plat_setup.c | 3 | ||||
| -rw-r--r-- | plat/mediatek/mt8192/drivers/timer/mt_timer.c | 8 | ||||
| -rw-r--r-- | plat/mediatek/mt8192/drivers/timer/mt_timer.h | 5 |
3 files changed, 16 insertions, 0 deletions
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c index 9a01bef65..4d2f5d24c 100644 --- a/plat/mediatek/mt8192/bl31_plat_setup.c +++ b/plat/mediatek/mt8192/bl31_plat_setup.c @@ -17,6 +17,7 @@ /* Platform Includes */ #include <gpio/mtgpio.h> #include <mt_gic_v3.h> +#include <mt_timer.h> #include <plat_params.h> #include <plat_private.h> @@ -84,7 +85,9 @@ void bl31_platform_setup(void) /* Initialize the GIC driver, CPU and distributor interfaces */ mt_gic_driver_init(); mt_gic_init(); + plat_mt8192_gpio_init(); + mt_systimer_init(); } /******************************************************************************* diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.c b/plat/mediatek/mt8192/drivers/timer/mt_timer.c index 781f940b6..08608854a 100644 --- a/plat/mediatek/mt8192/drivers/timer/mt_timer.c +++ b/plat/mediatek/mt8192/drivers/timer/mt_timer.c @@ -5,6 +5,7 @@ */ #include <arch_helpers.h> +#include <lib/mmio.h> #include <mt_timer.h> #include <platform_def.h> @@ -28,3 +29,10 @@ uint64_t sched_clock(void) - normal_time_base; return cval; } + +void mt_systimer_init(void) +{ + /* Enable access in NS mode */ + mmio_write_32(CNTWACR_REG, CNT_WRITE_ACCESS_CTL_MASK); + mmio_write_32(CNTRACR_REG, CNT_READ_ACCESS_CTL_MASK); +} diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.h b/plat/mediatek/mt8192/drivers/timer/mt_timer.h index 7aca4a3bf..b35317715 100644 --- a/plat/mediatek/mt8192/drivers/timer/mt_timer.h +++ b/plat/mediatek/mt8192/drivers/timer/mt_timer.h @@ -12,6 +12,8 @@ #define CNTSR_REG (SYSTIMER_BASE + 0x4) #define CNTSYS_L_REG (SYSTIMER_BASE + 0x8) #define CNTSYS_H_REG (SYSTIMER_BASE + 0xc) +#define CNTWACR_REG (SYSTIMER_BASE + 0x10) +#define CNTRACR_REG (SYSTIMER_BASE + 0x14) #define TIEO_EN (1 << 3) #define COMP_15_EN (1 << 10) @@ -23,8 +25,11 @@ #define COMP_20_MASK (COMP_20_EN | TIEO_EN) #define COMP_25_MASK (COMP_20_EN | COMP_25_EN) +#define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U) +#define CNT_READ_ACCESS_CTL_MASK (0x3FFFFFFU) void sched_clock_init(uint64_t normal_base, uint64_t atf_base); uint64_t sched_clock(void); +void mt_systimer_init(void); #endif /* MT_TIMER_H */ |