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authorYann Gautier <yann.gautier@st.com>2018-07-16 14:34:50 +0200
committerYann Gautier <yann.gautier@st.com>2018-07-24 17:18:41 +0200
commitf74cbc93a8cccb7b556a7d80bc274bcb280e8a9a (patch)
tree4fbf37ce533fa023d59d42c255d3014a209acf74 /plat/st/stm32mp1/stm32mp1.ld.S
parent5fbcdd056b51f2ccffee4a0e824df70fb3497323 (diff)
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stm32mp1: Link BL2, BL32 and DTB in one binary
platform.mk is updated to have compilation rules for DTB, stm32image tool, and the concatenation of the 3 binaries. A new linker script and an assembly file are added to manage this. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Diffstat (limited to 'plat/st/stm32mp1/stm32mp1.ld.S')
-rw-r--r--plat/st/stm32mp1/stm32mp1.ld.S76
1 files changed, 76 insertions, 0 deletions
diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
new file mode 100644
index 000000000..0d7a8bb7c
--- /dev/null
+++ b/plat/st/stm32mp1/stm32mp1.ld.S
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __STM32MP1_LD_S__
+#define __STM32MP1_LD_S__
+#include <platform_def.h>
+#include <xlat_tables_defs.h>
+
+OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
+OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
+
+ENTRY(__BL2_IMAGE_START__)
+
+MEMORY {
+ HEADER (rw) : ORIGIN = 0x00000000, LENGTH = 0x3000
+ RAM (rwx) : ORIGIN = STM32MP1_BINARY_BASE, LENGTH = STM32MP1_BINARY_SIZE
+}
+
+SECTIONS
+{
+ /*
+ * TF mapping must conform to ROM code specification.
+ */
+ .header : {
+ __HEADER_START__ = .;
+ KEEP(*(.header))
+ . = ALIGN(4);
+ __HEADER_END__ = .;
+ } >HEADER
+
+ . = STM32MP1_BINARY_BASE;
+ .data . : {
+ . = ALIGN(PAGE_SIZE);
+ __DATA_START__ = .;
+ *(.data*)
+
+ /*
+ * dtb.
+ * The strongest and only alignment contraint is MMU 4K page.
+ * Indeed as images below will be removed, 4K pages will be re-used.
+ */
+ . = ( STM32MP1_DTB_BASE - STM32MP1_BINARY_BASE );
+ __DTB_IMAGE_START__ = .;
+ *(.dtb_image*)
+ __DTB_IMAGE_END__ = .;
+
+ /*
+ * bl2.
+ * The strongest and only alignment contraint is MMU 4K page.
+ * Indeed as images below will be removed, 4K pages will be re-used.
+ */
+ . = ( STM32MP1_BL2_BASE - STM32MP1_BINARY_BASE );
+ __BL2_IMAGE_START__ = .;
+ *(.bl2_image*)
+ __BL2_IMAGE_END__ = .;
+
+ /*
+ * bl32 will be settled by bl2.
+ * The strongest and only alignment constraint is 8 words to simplify
+ * memraise8 assembly code.
+ */
+ . = ( STM32MP1_BL32_BASE - STM32MP1_BINARY_BASE );
+ __BL32_IMAGE_START__ = .;
+ *(.bl32_image*)
+ __BL32_IMAGE_END__ = .;
+
+ __DATA_END__ = .;
+ } >RAM
+
+ __TF_END__ = .;
+
+}
+#endif /*__STM32MP1_LD_S__*/