Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4

Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611

MUST ONLY BE SUBMITTED BY AUTOMERGER

Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62

15 files changed, 191 insertions, 252 deletions

diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/common/aarch64/plat_helpers.S
index 083c30e71..f045e2113 100644
--- a/plat/rpi/rpi4/aarch64/plat_helpers.S
+++ b/plat/rpi/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,8 +10,6 @@
 #include <platform_def.h>
 #include <cortex_a72.h>
 
-#include "../include/rpi_hw.h"
-
 	.globl	plat_crash_console_flush
 	.globl	plat_crash_console_init
 	.globl	plat_crash_console_putc
@@ -22,6 +20,7 @@
 	.globl	plat_reset_handler
 	.globl	plat_rpi3_calc_core_pos
 	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_rpi_get_model
 
 	/* -----------------------------------------------------
 	 *  unsigned int plat_my_core_pos(void)
@@ -58,27 +57,29 @@ endfunc plat_rpi3_calc_core_pos
 func plat_is_my_cpu_primary
 	mrs	x0, mpidr_el1
 	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #RPI4_PRIMARY_CPU
+	cmp	x0, #RPI_PRIMARY_CPU
 	cset	w0, eq
 	ret
 endfunc plat_is_my_cpu_primary
 
 	/* -----------------------------------------------------
-	 * void plat_secondary_cold_boot_setup (void);
+	 * void plat_wait_for_warm_boot (void);
 	 *
 	 * This function performs any platform specific actions
-	 * needed for a secondary cpu after a cold reset e.g
-	 * mark the cpu's presence, mechanism to place it in a
-	 * holding pen etc.
+	 * needed for a CPU to be put into holding pen to wait
+	 * for a warm boot request.
+	 * The function will never return.
 	 * -----------------------------------------------------
 	 */
-func plat_secondary_cold_boot_setup
-	/* Calculate address of our hold entry */
+func plat_wait_for_warm_boot
+	/*
+	 * Calculate address of our hold entry.
+	 * As the function will never return, there is no need to save LR.
+	 */
 	bl	plat_my_core_pos
 	lsl	x0, x0, #3
 	mov_imm	x2, PLAT_RPI3_TM_HOLD_BASE
 	add	x0, x0, x2
-
 	/*
 	 * This code runs way before requesting the warmboot of this core,
 	 * so it is possible to clear the mailbox before getting a request
@@ -98,6 +99,19 @@ poll_mailbox:
 	mov_imm	x0, PLAT_RPI3_TM_ENTRYPOINT
 	ldr	x1, [x0]
 	br	x1
+endfunc plat_wait_for_warm_boot
+
+	/* -----------------------------------------------------
+	 * void plat_secondary_cold_boot_setup (void);
+	 *
+	 * This function performs any platform specific actions
+	 * needed for a secondary cpu after a cold reset e.g
+	 * mark the cpu's presence, mechanism to place it in a
+	 * holding pen etc.
+	 * -----------------------------------------------------
+	 */
+func plat_secondary_cold_boot_setup
+	b	plat_wait_for_warm_boot
 endfunc plat_secondary_cold_boot_setup
 
 	/* ---------------------------------------------------------------------
@@ -112,9 +126,24 @@ endfunc plat_secondary_cold_boot_setup
 	 * ---------------------------------------------------------------------
 	 */
 func plat_get_my_entrypoint
-	/* TODO: support warm boot */
-	mov	x0, #0
-	ret
+	mov	x1, x30
+	bl	plat_is_my_cpu_primary
+	/*
+	 * Secondaries always cold boot.
+	*/
+	cbz	w0, 1f
+	/*
+	 * Primaries warm boot if they are requested
+	 * to power off.
+	 */
+	mov_imm	x0, PLAT_RPI3_TM_HOLD_BASE
+	ldr	x0, [x0]
+	cmp	x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF
+	adr	x0, plat_wait_for_warm_boot
+	csel	x0, x0, xzr, eq
+	ret	x1
+1:	mov	x0, #0
+	ret	x1
 endfunc plat_get_my_entrypoint
 
 	/* ---------------------------------------------
@@ -135,7 +164,7 @@ endfunc platform_mem_init
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_init
-	mov_imm	x0, PLAT_RPI3_UART_BASE
+	mov_imm	x0, PLAT_RPI_MINI_UART_BASE
 	mov	x1, xzr
 	mov	x2, xzr
 	b	console_16550_core_init
@@ -149,28 +178,55 @@ endfunc plat_crash_console_init
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_putc
-	mov_imm	x1, PLAT_RPI3_UART_BASE
+	mov_imm	x1, PLAT_RPI_MINI_UART_BASE
 	b	console_16550_core_putc
 endfunc plat_crash_console_putc
 
 	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
+	 * void plat_crash_console_flush()
 	 * Function to force a write of all buffered
 	 * data that hasn't been output.
-	 * Out : return -1 on error else return 0.
+	 * Out : void.
 	 * Clobber list : x0, x1
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_flush
-	mov_imm	x0, PLAT_RPI3_UART_BASE
+	mov_imm	x0, PLAT_RPI_MINI_UART_BASE
 	b	console_16550_core_flush
 endfunc plat_crash_console_flush
 
 	/* ---------------------------------------------
+	 * int plat_rpi_get_model()
+	 * Macro to determine whether we are running on
+	 * a Raspberry Pi 3 or 4. Just checks the MIDR for
+	 * being either a Cortex-A72 or a Cortex-A53.
+	 * Out : return 4 if RPi4, 3 otherwise.
+	 * Clobber list : x0
+	 * ---------------------------------------------
+	 */
+	.macro _plat_rpi_get_model
+	mrs	x0, midr_el1
+	and	x0, x0, #0xf0	/* Isolate low byte of part number */
+	cmp	w0, #0x80	/* Cortex-A72 (RPi4) is 0xd08, A53 is 0xd03 */
+	mov	w0, #3
+	csinc	w0, w0, w0, ne
+	.endm
+
+	func plat_rpi_get_model
+	_plat_rpi_get_model
+	ret
+	endfunc plat_rpi_get_model
+
+	/* ---------------------------------------------
 	 * void plat_reset_handler(void);
 	 * ---------------------------------------------
 	 */
 func plat_reset_handler
+	/* L2 cache setup only needed on RPi4 */
+	_plat_rpi_get_model
+	cmp	w0, #4
+	b.ne	1f
+
 	/* ------------------------------------------------
 	 * Set L2 read/write cache latency:
 	 * - L2 Data RAM latency: 3 cycles (0b010)
@@ -183,5 +239,6 @@ func plat_reset_handler
 	msr	CORTEX_A72_L2CTLR_EL1, x0
 	isb
 
+1:
 	ret
 endfunc plat_reset_handler
diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h
index de8357162..ddf239eb5 100644
--- a/plat/rpi/common/include/rpi_shared.h
+++ b/plat/rpi/common/include/rpi_shared.h
@@ -14,7 +14,7 @@
  ******************************************************************************/
 
 /* Utility functions */
-void rpi3_console_init(unsigned int base_clk_rate);
+void rpi3_console_init(void);
 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
 			    uintptr_t code_start, uintptr_t code_limit,
 			    uintptr_t rodata_start, uintptr_t rodata_limit
@@ -36,4 +36,6 @@ void plat_rpi3_io_setup(void);
 /* VideoCore firmware commands */
 int rpi3_vc_hardware_get_board_revision(uint32_t *revision);
 
+int plat_rpi_get_model(void);
+
 #endif /* RPI3_PRIVATE_H */
diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c
index ff3369427..ef88bf10e 100644
--- a/plat/rpi/common/rpi3_common.c
+++ b/plat/rpi/common/rpi3_common.c
@@ -13,7 +13,9 @@
 #include <common/debug.h>
 #include <bl31/interrupt_mgmt.h>
 #include <drivers/console.h>
+#include <drivers/rpi3/gpio/rpi3_gpio.h>
 #include <drivers/ti/uart/uart_16550.h>
+#include <drivers/arm/pl011.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 
 #include <rpi_hw.h>
@@ -102,18 +104,35 @@ static const mmap_region_t plat_rpi3_mmap[] = {
 /*******************************************************************************
  * Function that sets up the console
  ******************************************************************************/
-static console_16550_t rpi3_console;
+static console_t rpi3_console;
 
-void rpi3_console_init(unsigned int base_clk_rate)
+
+static bool rpi3_use_mini_uart(void)
+{
+	return rpi3_gpio_get_select(14) == RPI3_GPIO_FUNC_ALT5;
+}
+
+void rpi3_console_init(void)
 {
 	int console_scope = CONSOLE_FLAG_BOOT;
-#if RPI3_RUNTIME_UART != -1
-	console_scope |= CONSOLE_FLAG_RUNTIME;
-#endif
-	int rc = console_16550_register(PLAT_RPI3_UART_BASE,
-					base_clk_rate,
-					PLAT_RPI3_UART_BAUDRATE,
-					&rpi3_console);
+	int rc;
+
+	if (RPI3_RUNTIME_UART != -1)
+		console_scope |= CONSOLE_FLAG_RUNTIME;
+
+	rpi3_gpio_init();
+
+	if (rpi3_use_mini_uart())
+		rc = console_16550_register(PLAT_RPI_MINI_UART_BASE,
+					    0,
+					    PLAT_RPI_UART_BAUDRATE,
+					    &rpi3_console);
+	else
+		rc = console_pl011_register(PLAT_RPI_PL011_UART_BASE,
+					    PLAT_RPI_PL011_UART_CLOCK,
+					    PLAT_RPI_UART_BAUDRATE,
+					    &rpi3_console);
+
 	if (rc == 0) {
 		/*
 		 * The crash console doesn't use the multi console API, it uses
@@ -123,7 +142,7 @@ void rpi3_console_init(unsigned int base_clk_rate)
 		panic();
 	}
 
-	console_set_scope(&rpi3_console.console, console_scope);
+	console_set_scope(&rpi3_console, console_scope);
 }
 
 /*******************************************************************************
diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c
index 2a6bf076b..86c61f7a6 100644
--- a/plat/rpi/common/rpi3_pm.c
+++ b/plat/rpi/common/rpi3_pm.c
@@ -140,11 +140,14 @@ static int rpi3_pwr_domain_on(u_register_t mpidr)
 {
 	int rc = PSCI_E_SUCCESS;
 	unsigned int pos = plat_core_pos_by_mpidr(mpidr);
-	uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
+	uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
 
 	assert(pos < PLATFORM_CORE_COUNT);
 
-	hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO;
+	hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE;
+
+	mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO);
+	/* No cache maintenance here, hold_base is mapped as device memory. */
 
 	/* Make sure that the write has completed */
 	dsb();
@@ -171,6 +174,32 @@ static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state)
 #endif
 }
 
+static void __dead2 rpi3_pwr_down_wfi(
+		const psci_power_state_t *target_state)
+{
+	uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
+	unsigned int pos = plat_my_core_pos();
+
+	if (pos == 0) {
+		/*
+		 * The secondaries will always be in a wait
+		 * for warm boot on reset, but the BSP needs
+		 * to be able to distinguish between waiting
+		 * for warm boot (e.g. after psci_off, waiting
+		 * for psci_on) and a cold boot.
+		 */
+		mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF);
+		/* No cache maintenance here, we run with caches off already. */
+		dsb();
+		isb();
+	}
+
+	write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
+
+	while (1)
+		;
+}
+
 /*******************************************************************************
  * Platform handlers for system reset and system off.
  ******************************************************************************/
@@ -236,6 +265,7 @@ static const plat_psci_ops_t plat_rpi3_psci_pm_ops = {
 	.pwr_domain_pwr_down_wfi = rpi3_pwr_domain_pwr_down_wfi,
 	.pwr_domain_on = rpi3_pwr_domain_on,
 	.pwr_domain_on_finish = rpi3_pwr_domain_on_finish,
+	.pwr_domain_pwr_down_wfi = rpi3_pwr_down_wfi,
 	.system_off = rpi3_system_off,
 	.system_reset = rpi3_system_reset,
 	.validate_power_state = rpi3_validate_power_state,
diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S
deleted file mode 100644
index 24278bdf6..000000000
--- a/plat/rpi/rpi3/aarch64/plat_helpers.S
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <platform_def.h>
-
-#include "../include/rpi_hw.h"
-
-	.globl	plat_crash_console_flush
-	.globl	plat_crash_console_init
-	.globl	plat_crash_console_putc
-	.globl	platform_mem_init
-	.globl	plat_get_my_entrypoint
-	.globl	plat_is_my_cpu_primary
-	.globl	plat_my_core_pos
-	.globl	plat_rpi3_calc_core_pos
-	.globl	plat_secondary_cold_boot_setup
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_my_core_pos(void)
-	 *
-	 *  This function uses the plat_rpi3_calc_core_pos()
-	 *  definition to get the index of the calling CPU.
-	 * -----------------------------------------------------
-	 */
-func plat_my_core_pos
-	mrs	x0, mpidr_el1
-	b	plat_rpi3_calc_core_pos
-endfunc plat_my_core_pos
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
-	 *
-	 *  CorePos = (ClusterId * 4) + CoreId
-	 * -----------------------------------------------------
-	 */
-func plat_rpi3_calc_core_pos
-	and	x1, x0, #MPIDR_CPU_MASK
-	and	x0, x0, #MPIDR_CLUSTER_MASK
-	add	x0, x1, x0, LSR #6
-	ret
-endfunc plat_rpi3_calc_core_pos
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_is_my_cpu_primary (void);
-	 *
-	 * Find out whether the current cpu is the primary
-	 * cpu.
-	 * -----------------------------------------------------
-	 */
-func plat_is_my_cpu_primary
-	mrs	x0, mpidr_el1
-	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #RPI3_PRIMARY_CPU
-	cset	w0, eq
-	ret
-endfunc plat_is_my_cpu_primary
-
-	/* -----------------------------------------------------
-	 * void plat_secondary_cold_boot_setup (void);
-	 *
-	 * This function performs any platform specific actions
-	 * needed for a secondary cpu after a cold reset e.g
-	 * mark the cpu's presence, mechanism to place it in a
-	 * holding pen etc.
-	 * -----------------------------------------------------
-	 */
-func plat_secondary_cold_boot_setup
-	/* Calculate address of our hold entry */
-	bl	plat_my_core_pos
-	lsl	x0, x0, #3
-	mov_imm	x2, PLAT_RPI3_TM_HOLD_BASE
-	add	x0, x0, x2
-
-	/*
-	 * This code runs way before requesting the warmboot of this core,
-	 * so it is possible to clear the mailbox before getting a request
-	 * to boot.
-	 */
-	mov	x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
-	str	x1,[x0]
-
-	/* Wait until we have a go */
-poll_mailbox:
-	wfe
-	ldr	x1, [x0]
-	cmp	x1, PLAT_RPI3_TM_HOLD_STATE_GO
-	bne	poll_mailbox
-
-	/* Jump to the provided entrypoint */
-	mov_imm	x0, PLAT_RPI3_TM_ENTRYPOINT
-	ldr	x1, [x0]
-	br	x1
-endfunc plat_secondary_cold_boot_setup
-
-	/* ---------------------------------------------------------------------
-	 * uintptr_t plat_get_my_entrypoint (void);
-	 *
-	 * Main job of this routine is to distinguish between a cold and a warm
-	 * boot.
-	 *
-	 * This functions returns:
-	 *  - 0 for a cold boot.
-	 *  - Any other value for a warm boot.
-	 * ---------------------------------------------------------------------
-	 */
-func plat_get_my_entrypoint
-	/* TODO: support warm boot */
-	mov	x0, #0
-	ret
-endfunc plat_get_my_entrypoint
-
-	/* ---------------------------------------------
-	 * void platform_mem_init (void);
-	 *
-	 * No need to carry out any memory initialization.
-	 * ---------------------------------------------
-	 */
-func platform_mem_init
-	ret
-endfunc platform_mem_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Function to initialize the crash console
-	 * without a C Runtime to print crash report.
-	 * Clobber list : x0 - x3
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_init
-	mov_imm	x0, PLAT_RPI3_UART_BASE
-	mov_imm	x1, PLAT_RPI3_UART_CLK_IN_HZ
-	mov_imm	x2, PLAT_RPI3_UART_BAUDRATE
-	b	console_16550_core_init
-endfunc plat_crash_console_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_putc(int c)
-	 * Function to print a character on the crash
-	 * console without a C Runtime.
-	 * Clobber list : x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_putc
-	mov_imm	x1, PLAT_RPI3_UART_BASE
-	b	console_16550_core_putc
-endfunc plat_crash_console_putc
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
-	 * Function to force a write of all buffered
-	 * data that hasn't been output.
-	 * Out : return -1 on error else return 0.
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_flush
-	mov_imm	x0, PLAT_RPI3_UART_BASE
-	b	console_16550_core_flush
-endfunc plat_crash_console_flush
diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h
index e308f70a6..f44d1f526 100644
--- a/plat/rpi/rpi3/include/platform_def.h
+++ b/plat/rpi/rpi3/include/platform_def.h
@@ -24,7 +24,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define RPI3_PRIMARY_CPU		U(0)
+#define RPI_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
@@ -153,6 +153,7 @@
 
 #define PLAT_RPI3_TM_HOLD_STATE_WAIT	ULL(0)
 #define PLAT_RPI3_TM_HOLD_STATE_GO	ULL(1)
+#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF	ULL(2)
 
 /*
  * BL1 specific defines.
@@ -249,9 +250,10 @@
 /*
  * Serial-related constants.
  */
-#define PLAT_RPI3_UART_BASE		RPI3_MINI_UART_BASE
-#define PLAT_RPI3_UART_CLK_IN_HZ	RPI3_MINI_UART_CLK_IN_HZ
-#define PLAT_RPI3_UART_BAUDRATE		ULL(115200)
+#define PLAT_RPI_MINI_UART_BASE		RPI3_MINI_UART_BASE
+#define PLAT_RPI_PL011_UART_BASE	RPI3_PL011_UART_BASE
+#define PLAT_RPI_PL011_UART_CLOCK	RPI3_PL011_UART_CLOCK
+#define PLAT_RPI_UART_BAUDRATE		ULL(115200)
 
 /*
  * System counter
diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h
index 01d5b4a0f..2aecab379 100644
--- a/plat/rpi/rpi3/include/rpi_hw.h
+++ b/plat/rpi/rpi3/include/rpi_hw.h
@@ -77,11 +77,15 @@
 #define RPI3_RNG_INT_MASK_DISABLE	U(0x1)
 
 /*
- * Serial port (called 'Mini UART' in the BCM docucmentation).
+ * Serial ports:
+ * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
+ * There is also a PL011 UART, multiplexed to the same pins.
  */
 #define RPI3_IO_MINI_UART_OFFSET	ULL(0x00215040)
 #define RPI3_MINI_UART_BASE		(RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
-#define RPI3_MINI_UART_CLK_IN_HZ	ULL(500000000)
+#define RPI3_IO_PL011_UART_OFFSET	ULL(0x00201000)
+#define RPI3_PL011_UART_BASE		(RPI_IO_BASE + RPI3_IO_PL011_UART_OFFSET)
+#define RPI3_PL011_UART_CLOCK		ULL(48000000)
 
 /*
  * GPIO controller
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index a21a7709a..6c239230d 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -11,6 +11,11 @@ PLAT_INCLUDES		:=	-Iplat/rpi/common/include		\
 				-Iplat/rpi/rpi3/include
 
 PLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/aarch64/16550_console.S	\
+				drivers/arm/pl011/aarch64/pl011_console.S \
+				drivers/gpio/gpio.c			\
+				drivers/delay_timer/delay_timer.c	\
+				drivers/rpi3/gpio/rpi3_gpio.c		\
+				plat/rpi/common/aarch64/plat_helpers.S	\
 				plat/rpi/common/rpi3_common.c		\
 				${XLAT_TABLES_LIB_SRCS}
 
@@ -19,7 +24,6 @@ BL1_SOURCES		+=	drivers/io/io_fip.c			\
 				drivers/io/io_storage.c			\
 				lib/cpus/aarch64/cortex_a53.S		\
 				plat/common/aarch64/platform_mp_stack.S	\
-				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/rpi3_bl1_setup.c		\
 				plat/rpi/common/rpi3_io_storage.c	\
 				drivers/rpi3/mailbox/rpi3_mbox.c	\
@@ -29,15 +33,11 @@ BL2_SOURCES		+=	common/desc_image_load.c		\
 				drivers/io/io_fip.c			\
 				drivers/io/io_memmap.c			\
 				drivers/io/io_storage.c			\
-				drivers/gpio/gpio.c			\
-				drivers/delay_timer/delay_timer.c	\
 				drivers/delay_timer/generic_delay_timer.c \
-				drivers/rpi3/gpio/rpi3_gpio.c		\
 				drivers/io/io_block.c			\
 				drivers/mmc/mmc.c			\
 				drivers/rpi3/sdhost/rpi3_sdhost.c	\
 				plat/common/aarch64/platform_mp_stack.S	\
-				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \
 				plat/rpi/rpi3/rpi3_bl2_setup.c		\
 				plat/rpi/common/rpi3_image_load.c	\
@@ -45,7 +45,6 @@ BL2_SOURCES		+=	common/desc_image_load.c		\
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
 				plat/common/plat_psci_common.c		\
-				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/rpi3_bl31_setup.c		\
 				plat/rpi/common/rpi3_pm.c		\
 				plat/rpi/common/rpi3_topology.c		\
@@ -186,18 +185,20 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
     AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
 				drivers/auth/crypto_mod.c		\
 				drivers/auth/img_parser_mod.c		\
-				drivers/auth/tbbr/tbbr_cot.c
+				drivers/auth/tbbr/tbbr_cot_common.c
 
     BL1_SOURCES		+=	${AUTH_SOURCES}				\
 				bl1/tbbr/tbbr_img_desc.c		\
 				plat/common/tbbr/plat_tbbr.c		\
 				plat/rpi/common/rpi3_trusted_boot.c    	\
-				plat/rpi/common/rpi3_rotpk.S
+				plat/rpi/common/rpi3_rotpk.S		\
+				drivers/auth/tbbr/tbbr_cot_bl1.c
 
     BL2_SOURCES		+=	${AUTH_SOURCES}				\
 				plat/common/tbbr/plat_tbbr.c		\
 				plat/rpi/common/rpi3_trusted_boot.c    	\
-				plat/rpi/common/rpi3_rotpk.S
+				plat/rpi/common/rpi3_rotpk.S		\
+				drivers/auth/tbbr/tbbr_cot_bl2.c
 
     ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
     ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
@@ -209,7 +210,7 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
 
     certificates: $(ROT_KEY)
 
-    $(ROT_KEY):
+    $(ROT_KEY): | $(BUILD_PLAT)
 	@echo "  OPENSSL $@"
 	$(Q)openssl genrsa 2048 > $@ 2>/dev/null
 
diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c
index dcce76e47..3ac30e0f0 100644
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@@ -35,7 +35,7 @@ void bl1_early_platform_setup(void)
 		      0x80000000);
 
 	/* Initialize the console to provide early debug support */
-	rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+	rpi3_console_init();
 
 	/* Allow BL1 to see the whole Trusted RAM */
 	bl1_tzram_layout.total_base = BL_RAM_BASE;
diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c
index 44827c63a..db7181794 100644
--- a/plat/rpi/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl2_setup.c
@@ -24,17 +24,6 @@
 /* Data structure which holds the extents of the trusted SRAM for BL2 */
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
 
-/* rpi3 GPIO setup function. */
-static void rpi3_gpio_setup(void)
-{
-	struct rpi3_gpio_params params;
-
-	memset(&params, 0, sizeof(struct rpi3_gpio_params));
-	params.reg_base = RPI3_GPIO_BASE;
-
-	rpi3_gpio_init(&params);
-}
-
 /* Data structure which holds the MMC info */
 static struct mmc_device_info mmc_info;
 
@@ -62,13 +51,13 @@ void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	meminfo_t *mem_layout = (meminfo_t *) arg1;
 
 	/* Initialize the console to provide early debug support */
-	rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+	rpi3_console_init();
 
 	/* Enable arch timer */
 	generic_delay_timer_init();
 
 	/* Setup GPIO driver */
-	rpi3_gpio_setup();
+	rpi3_gpio_init();
 
 	/* Setup the BL2 memory layout */
 	bl2_tzram_layout = *mem_layout;
diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c
index 24a56139b..59157536b 100644
--- a/plat/rpi/rpi3/rpi3_bl31_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl31_setup.c
@@ -72,7 +72,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 {
 	/* Initialize the console to provide early debug support */
-	rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+	rpi3_console_init();
 
 	/*
 	 * In debug builds, a special value is passed in 'arg1' to verify
diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h
index a9ecdba20..6787ebfee 100644
--- a/plat/rpi/rpi4/include/platform_def.h
+++ b/plat/rpi/rpi4/include/platform_def.h
@@ -24,7 +24,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define RPI4_PRIMARY_CPU		U(0)
+#define RPI_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
@@ -93,6 +93,7 @@
 
 #define PLAT_RPI3_TM_HOLD_STATE_WAIT	ULL(0)
 #define PLAT_RPI3_TM_HOLD_STATE_GO	ULL(1)
+#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF	ULL(2)
 
 /*
  * BL31 specific defines.
@@ -126,8 +127,10 @@
 /*
  * Serial-related constants.
  */
-#define PLAT_RPI3_UART_BASE		RPI3_MINI_UART_BASE
-#define PLAT_RPI3_UART_BAUDRATE		ULL(115200)
+#define PLAT_RPI_MINI_UART_BASE		RPI4_MINI_UART_BASE
+#define PLAT_RPI_PL011_UART_BASE	RPI4_PL011_UART_BASE
+#define PLAT_RPI_PL011_UART_CLOCK       RPI4_PL011_UART_CLOCK
+#define PLAT_RPI_UART_BAUDRATE          ULL(115200)
 
 /*
  * System counter
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index b1dd4e92e..718510610 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -77,10 +77,15 @@
 #define RPI3_RNG_INT_MASK_DISABLE	U(0x1)
 
 /*
- * Serial port (called 'Mini UART' in the Broadcom documentation).
+ * Serial ports:
+ * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
+ * There is also a PL011 UART, multiplexed to the same pins.
  */
-#define RPI3_IO_MINI_UART_OFFSET	ULL(0x00215040)
-#define RPI3_MINI_UART_BASE		(RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
+#define RPI4_IO_MINI_UART_OFFSET	ULL(0x00215040)
+#define RPI4_MINI_UART_BASE		(RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET)
+#define RPI4_IO_PL011_UART_OFFSET	ULL(0x00201000)
+#define RPI4_PL011_UART_BASE		(RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET)
+#define RPI4_PL011_UART_CLOCK		ULL(48000000)
 
 /*
  * GPIO controller
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index 2038021a0..0744bceb4 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -11,15 +11,19 @@ PLAT_INCLUDES		:=	-Iplat/rpi/common/include		\
 				-Iplat/rpi/rpi4/include
 
 PLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/aarch64/16550_console.S	\
+				drivers/arm/pl011/aarch64/pl011_console.S \
 				plat/rpi/common/rpi3_common.c		\
 				${XLAT_TABLES_LIB_SRCS}
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		\
-				plat/rpi/rpi4/aarch64/plat_helpers.S	\
+				plat/rpi/common/aarch64/plat_helpers.S	\
 				plat/rpi/rpi4/aarch64/armstub8_header.S	\
 				drivers/arm/gic/common/gic_common.c     \
 				drivers/arm/gic/v2/gicv2_helpers.c      \
 				drivers/arm/gic/v2/gicv2_main.c         \
+				drivers/delay_timer/delay_timer.c	\
+				drivers/gpio/gpio.c			\
+				drivers/rpi3/gpio/rpi3_gpio.c		\
 				plat/common/plat_gicv2.c                \
 				plat/rpi/rpi4/rpi4_bl31_setup.c		\
 				plat/rpi/common/rpi3_pm.c		\
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
index 9e3b53979..cfacd1fe1 100644
--- a/plat/rpi/rpi4/rpi4_bl31_setup.c
+++ b/plat/rpi/rpi4/rpi4_bl31_setup.c
@@ -17,6 +17,7 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 #include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
 #include <libfdt.h>
 
 #include <drivers/arm/gicv2.h>
@@ -132,14 +133,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	/* Early GPU firmware revisions need a little break here. */
 	ldelay(100000);
 
-	/*
-	 * Initialize the console to provide early debug support.
-	 * We rely on the GPU firmware to have initialised the UART correctly,
-	 * as the baud base clock rate differs across GPU firmware revisions.
-	 * Providing a base clock of 0 lets the 16550 UART init routine skip
-	 * the initial enablement and baud rate setup.
-	 */
-	rpi3_console_init(0);
+	/* Initialize the console to provide early debug support. */
+	rpi3_console_init();
 
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 	bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
@@ -206,13 +201,6 @@ void bl31_plat_arch_setup(void)
 	enable_mmu_el3(0);
 }
 
-static uint32_t dtb_size(const void *dtb)
-{
-	const uint32_t *dtb_header = dtb;
-
-	return fdt32_to_cpu(dtb_header[1]);
-}
-
 static void rpi4_prepare_dtb(void)
 {
 	void *dtb = (void *)rpi4_get_dtb_address();
@@ -256,7 +244,7 @@ static void rpi4_prepare_dtb(void)
 	if (ret < 0)
 		ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
 
-	clean_dcache_range((uintptr_t)dtb, dtb_size(dtb));
+	clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
 	INFO("Changed device tree to advertise PSCI.\n");
 }