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| author | Harvey Hsieh <hhsieh@nvidia.com> | 2016-11-23 19:15:02 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-11-13 13:28:03 -0800 |
| commit | d191573e6ae616adb3b6ce2404a4cff9bf4c0052 (patch) | |
| tree | 43da6740244ac7fd1edd276e372b9b85787cef2e /plat/nvidia | |
| parent | 2e446f50bde561913276ef6d930a20dfeadf416d (diff) | |
| download | platform_external_arm-trusted-firmware-d191573e6ae616adb3b6ce2404a4cff9bf4c0052.tar.gz platform_external_arm-trusted-firmware-d191573e6ae616adb3b6ce2404a4cff9bf4c0052.tar.bz2 platform_external_arm-trusted-firmware-d191573e6ae616adb3b6ce2404a4cff9bf4c0052.zip | |
Tegra194: remove L2 ECC parity protection setting
This patch removes the code to enable L2 ECC parity protection
bit, as Tegra194 does not have any Cortex-A57 CPUs.
Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_setup.c | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 7ca65dd06..a3a2515ca 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -25,9 +25,6 @@ #include <tegra_private.h> #include <lib/xlat_tables/xlat_tables_v2.h> -DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) -extern uint64_t tegra_enable_l2_ecc_parity_prot; - /******************************************************************************* * The Tegra power domain tree has a single system level power domain i.e. a * single root node. The first entry in the power domain descriptor specifies @@ -145,49 +142,15 @@ uint32_t plat_get_console_from_id(int id) return tegra186_uart_addresses[id]; } -/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ -#define TEGRA186_VER_A02P 0x1201 - /******************************************************************************* * Handler for early platform setup ******************************************************************************/ void plat_early_platform_setup(void) { - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; - uint32_t chip_subrev, val; /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); - /* - * Enable ECC and Parity Protection for Cortex-A57 CPUs - * for Tegra A02p SKUs - */ - if (impl != DENVER_IMPL) { - - /* get the major, minor and sub-version values */ - chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & - SUBREVISION_MASK; - - /* prepare chip version number */ - val = (tegra_get_chipid_major() << 12) | - (tegra_get_chipid_minor() << 8) | - chip_subrev; - - /* enable L2 ECC for Tegra186 A02P and beyond */ - if (val >= TEGRA186_VER_A02P) { - - val = read_l2ctlr_el1(); - val |= L2_ECC_PARITY_PROTECTION_BIT; - write_l2ctlr_el1(val); - - /* - * Set the flag to enable ECC/Parity Protection - * when we exit System Suspend or Cluster Powerdn - */ - tegra_enable_l2_ecc_parity_prot = 1; - } - } } /* Secure IRQs for Tegra186 */ |