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| author | Alistair Delva <adelva@google.com> | 2021-02-16 21:01:22 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2021-02-16 21:01:22 +0000 |
| commit | efb2826bb8160e2d8e0fcec85133a7468484f9fd (patch) | |
| tree | 37a21c69306801ee7cdda5167a30896c8740155b /plat/nvidia/tegra/include/plat_macros.S | |
| parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
| parent | faa476c0caaa598afa5a6109d17102db5fe35ec6 (diff) | |
| download | platform_external_arm-trusted-firmware-master.tar.gz platform_external_arm-trusted-firmware-master.tar.bz2 platform_external_arm-trusted-firmware-master.zip | |
Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611
MUST ONLY BE SUBMITTED BY AUTOMERGER
Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
Diffstat (limited to 'plat/nvidia/tegra/include/plat_macros.S')
| -rw-r--r-- | plat/nvidia/tegra/include/plat_macros.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S index 4f01e3306..2dc3b4152 100644 --- a/plat/nvidia/tegra/include/plat_macros.S +++ b/plat/nvidia/tegra/include/plat_macros.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,6 +28,7 @@ spacer: * --------------------------------------------- */ .macro plat_crash_print_regs +#ifdef TEGRA_GICC_BASE mov_imm x16, TEGRA_GICC_BASE /* gicc base address is now in x16 */ @@ -37,7 +39,7 @@ spacer: ldr w10, [x16, #GICC_CTLR] /* Store to the crash buf and print to cosole */ bl str_in_crash_buf_print - +#endif /* Print the GICD_ISPENDR regs */ mov_imm x16, TEGRA_GICD_BASE add x7, x16, #GICD_ISPENDR |